[444] | 1 | /* |
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| 2 | * The authors hereby grant permission to use, copy, modify, distribute, |
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| 3 | * and license this software and its documentation for any purpose, provided |
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| 4 | * that existing copyright notices are retained in all copies and that this |
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| 5 | * notice is included verbatim in any distributions. No written agreement, |
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| 6 | * license, or royalty fee is required for any of the authorized uses. |
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| 7 | * Modifications to this software may be copyrighted by their authors |
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| 8 | * and need not follow the licensing terms described here, provided that |
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| 9 | * the new terms are clearly indicated on the first page of each file where |
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| 10 | * they apply. |
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| 11 | */ |
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| 12 | |
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| 13 | /************************************************************************ |
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| 14 | ** |
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| 15 | ** defBF538.h |
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| 16 | ** |
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| 17 | ** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved. |
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| 18 | ** |
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| 19 | *************************************************************************/ |
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| 20 | |
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| 21 | /* |
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| 22 | ** This include file contains a list of macro "defines" to enable the |
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| 23 | ** programmer to use symbolic names for ADSP-BF538 peripherals. |
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| 24 | */ |
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| 25 | |
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| 26 | #ifndef _DEF_BF538_H |
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| 27 | #define _DEF_BF538_H |
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| 28 | |
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| 29 | /* Include all Core registers and bit definitions */ |
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| 30 | #include <def_LPBlackfin.h> |
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| 31 | |
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| 32 | /* Include all System registers and bit definitions common to ADSP-BF532 */ |
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| 33 | #include <defBF532.h> |
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| 34 | |
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| 35 | #ifdef _MISRA_RULES |
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| 36 | #pragma diag(push) |
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| 37 | #pragma diag(suppress:misra_rule_19_4) |
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| 38 | #pragma diag(suppress:misra_rule_19_6) |
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| 39 | #pragma diag(suppress:misra_rule_19_7) |
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| 40 | #endif /* _MISRA_RULES */ |
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| 41 | |
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| 42 | |
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| 43 | /******************************************************************************** |
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| 44 | * System MMR Register Map |
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| 45 | ********************************************************************************/ |
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| 46 | /* Define MMR Space for Additional BF538 Peripherals */ |
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| 47 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ |
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| 48 | /* SIC0 on ADSP-BF538 Is Same As SIC on ADSP-BF532 */ |
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| 49 | #define SIC_IMASK0 SIC_IMASK /* Interrupt Mask Register 0 */ |
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| 50 | #define SIC_ISR0 SIC_ISR /* Interrupt Status Register 0 */ |
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| 51 | #define SIC_IWR0 SIC_IWR /* Interrupt Wakeup Register 0 */ |
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| 52 | |
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| 53 | /* Add SIC1 MMRs for ADSP-BF538 Processors */ |
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| 54 | #define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */ |
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| 55 | #define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */ |
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| 56 | #define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */ |
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| 57 | |
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| 58 | /* Add SIC1 Interrupt Sources for ADSP-BF538 Processors */ |
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| 59 | #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ |
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| 60 | #define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */ |
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| 61 | #define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */ |
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| 62 | #define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */ |
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| 63 | |
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| 64 | |
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| 65 | /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ |
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| 66 | /* UART0 on ADSP-BF538 Is Same As UART on ADSP-BF532 */ |
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| 67 | #define UART0_THR UART_THR /* Transmit Holding register */ |
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| 68 | #define UART0_RBR UART_RBR /* Receive Buffer register */ |
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| 69 | #define UART0_DLL UART_DLL /* Divisor Latch (Low-Byte) */ |
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| 70 | #define UART0_IER UART_IER /* Interrupt Enable Register */ |
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| 71 | #define UART0_DLH UART_DLH /* Divisor Latch (High-Byte) */ |
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| 72 | #define UART0_IIR UART_IIR /* Interrupt Identification Register */ |
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| 73 | #define UART0_LCR UART_LCR /* Line Control Register */ |
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| 74 | #define UART0_MCR UART_MCR /* Modem Control Register */ |
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| 75 | #define UART0_LSR UART_LSR /* Line Status Register */ |
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| 76 | #define UART0_SCR UART_SCR /* SCR Scratch Register */ |
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| 77 | #define UART0_GCTL UART_GCTL /* Global Control Register */ |
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| 78 | |
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| 79 | |
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| 80 | /* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ |
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| 81 | /* SPI0 on ADSP-BF538 Is Same As SPI on ADSP-BF532 */ |
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| 82 | #define SPI0_CTL SPI_CTL /* SPI0 Control Register */ |
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| 83 | #define SPI0_FLG SPI_FLG /* SPI0 Flag register */ |
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| 84 | #define SPI0_STAT SPI_STAT /* SPI0 Status register */ |
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| 85 | #define SPI0_TDBR SPI_TDBR /* SPI0 Transmit Data Buffer Register */ |
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| 86 | #define SPI0_RDBR SPI_RDBR /* SPI0 Receive Data Buffer Register */ |
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| 87 | #define SPI0_BAUD SPI_BAUD /* SPI0 Baud rate Register */ |
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| 88 | #define SPI0_SHADOW SPI_SHADOW /* SPI0_RDBR Shadow Register */ |
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| 89 | |
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| 90 | |
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| 91 | /* General-Purpose Port F (0xFFC00700 - 0xFFC007FF) */ |
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| 92 | /* ADSP-BF538 Refers to FIO as GPIO Port F */ |
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| 93 | #define PORTFIO FIO_FLAG_D /* GPIO Port F Pin State Specify Register */ |
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| 94 | #define PORTFIO_CLEAR FIO_FLAG_C /* Peripheral Interrupt GPIO Clear Register */ |
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| 95 | #define PORTFIO_SET FIO_FLAG_S /* Peripheral Interrupt GPIO Set Register */ |
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| 96 | #define PORTFIO_TOGGLE FIO_FLAG_T /* GPIO Port F Pin State Toggle Register */ |
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| 97 | #define PORTFIO_MASKA FIO_MASKA_D /* GPIO Port F Mask State Specify Interrupt A Register */ |
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| 98 | #define PORTFIO_MASKA_CLEAR FIO_MASKA_C /* GPIO Port F Mask Disable Interrupt A Register */ |
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| 99 | #define PORTFIO_MASKA_SET FIO_MASKA_S /* GPIO Port F Mask Enable Interrupt A Register */ |
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| 100 | #define PORTFIO_MASKA_TOGGLE FIO_MASKA_T /* GPIO Port F Mask Toggle Enable Interrupt A Register */ |
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| 101 | #define PORTFIO_MASKB FIO_MASKB_D /* GPIO Port F Mask State Specify Interrupt B Register */ |
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| 102 | #define PORTFIO_MASKB_CLEAR FIO_MASKB_C /* GPIO Port F Mask Disable Interrupt B Register */ |
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| 103 | #define PORTFIO_MASKB_SET FIO_MASKB_S /* GPIO Port F Mask Enable Interrupt B Register */ |
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| 104 | #define PORTFIO_MASKB_TOGGLE FIO_MASKB_T /* GPIO Port F Mask Toggle Enable Interrupt B Register */ |
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| 105 | #define PORTFIO_DIR FIO_DIR /* GPIO Port F Direction Register */ |
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| 106 | #define PORTFIO_POLAR FIO_POLAR /* GPIO Port F Source Polarity Register */ |
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| 107 | #define PORTFIO_EDGE FIO_EDGE /* GPIO Port F Source Sensitivity Register */ |
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| 108 | #define PORTFIO_BOTH FIO_BOTH /* GPIO Port F Set on BOTH Edges Register */ |
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| 109 | #define PORTFIO_INEN FIO_INEN /* GPIO Port F Input Enable Register */ |
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| 110 | |
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| 111 | |
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| 112 | /* DMA0 Test Registers (0xFFC00B00 - 0xFFC00BFF) */ |
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| 113 | /* ADSP-BF538 DMA0 Controller Is Same As ADSP-BF532 DMA Controller */ |
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| 114 | #define DMAC0_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ |
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| 115 | #define DMAC0_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ |
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| 116 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ |
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| 117 | #define DMA0_TC_PER DMAC0_TC_PER /* Traffic Control Periods Register */ |
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| 118 | #define DMA0_TC_CNT DMAC0_TC_CNT /* Traffic Control Current Counts Register */ |
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| 119 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ |
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| 120 | #define DMA0_TCPER DMA0_TC_PER /* Traffic Control Periods Register */ |
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| 121 | #define DMA0_TCCNT DMA0_TC_CNT /* Traffic Control Current Counts Register */ |
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| 122 | |
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| 123 | /* ADSP-BF538 Must Enumerate Memory DMA Channels By Controller */ |
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| 124 | #define MDMA0_D0_NEXT_DESC_PTR MDMA_D0_NEXT_DESC_PTR /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */ |
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| 125 | #define MDMA0_D0_START_ADDR MDMA_D0_START_ADDR /* MemDMA0 Stream 0 Destination Start Address Register */ |
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| 126 | #define MDMA0_D0_CONFIG MDMA_D0_CONFIG /* MemDMA0 Stream 0 Destination Configuration Register */ |
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| 127 | #define MDMA0_D0_X_COUNT MDMA_D0_X_COUNT /* MemDMA0 Stream 0 Destination X Count Register */ |
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| 128 | #define MDMA0_D0_X_MODIFY MDMA_D0_X_MODIFY /* MemDMA0 Stream 0 Destination X Modify Register */ |
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| 129 | #define MDMA0_D0_Y_COUNT MDMA_D0_Y_COUNT /* MemDMA0 Stream 0 Destination Y Count Register */ |
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| 130 | #define MDMA0_D0_Y_MODIFY MDMA_D0_Y_MODIFY /* MemDMA0 Stream 0 Destination Y Modify Register */ |
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| 131 | #define MDMA0_D0_CURR_DESC_PTR MDMA_D0_CURR_DESC_PTR /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */ |
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| 132 | #define MDMA0_D0_CURR_ADDR MDMA_D0_CURR_ADDR /* MemDMA0 Stream 0 Destination Current Address Register */ |
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| 133 | #define MDMA0_D0_IRQ_STATUS MDMA_D0_IRQ_STATUS /* MemDMA0 Stream 0 Destination Interrupt/Status Register */ |
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| 134 | #define MDMA0_D0_PERIPHERAL_MAP MDMA_D0_PERIPHERAL_MAP /* MemDMA0 Stream 0 Destination Peripheral Map Register */ |
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| 135 | #define MDMA0_D0_CURR_X_COUNT MDMA_D0_CURR_X_COUNT /* MemDMA0 Stream 0 Destination Current X Count Register */ |
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| 136 | #define MDMA0_D0_CURR_Y_COUNT MDMA_D0_CURR_Y_COUNT /* MemDMA0 Stream 0 Destination Current Y Count Register */ |
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| 137 | |
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| 138 | #define MDMA0_S0_NEXT_DESC_PTR MDMA_S0_NEXT_DESC_PTR /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */ |
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| 139 | #define MDMA0_S0_START_ADDR MDMA_S0_START_ADDR /* MemDMA0 Stream 0 Source Start Address Register */ |
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| 140 | #define MDMA0_S0_CONFIG MDMA_S0_CONFIG /* MemDMA0 Stream 0 Source Configuration Register */ |
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| 141 | #define MDMA0_S0_X_COUNT MDMA_S0_X_COUNT /* MemDMA Stream 0 Source X Count Register */ |
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| 142 | #define MDMA0_S0_X_MODIFY MDMA_S0_X_MODIFY /* MemDMA0 Stream 0 Source X Modify Register */ |
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| 143 | #define MDMA0_S0_Y_COUNT MDMA_S0_Y_COUNT /* MemDMA0 Stream 0 Source Y Count Register */ |
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| 144 | #define MDMA0_S0_Y_MODIFY MDMA_S0_Y_MODIFY /* MemDMA0 Stream 0 Source Y Modify Register */ |
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| 145 | #define MDMA0_S0_CURR_DESC_PTR MDMA_S0_CURR_DESC_PTR /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */ |
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| 146 | #define MDMA0_S0_CURR_ADDR MDMA_S0_CURR_ADDR /* MemDMA0 Stream 0 Source Current Address Register */ |
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| 147 | #define MDMA0_S0_IRQ_STATUS MDMA_S0_IRQ_STATUS /* MemDMA0 Stream 0 Source Interrupt/Status Register */ |
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| 148 | #define MDMA0_S0_PERIPHERAL_MAP MDMA_S0_PERIPHERAL_MAP /* MemDMA0 Stream 0 Source Peripheral Map Register */ |
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| 149 | #define MDMA0_S0_CURR_X_COUNT MDMA_S0_CURR_X_COUNT /* MemDMA0 Stream 0 Source Current X Count Register */ |
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| 150 | #define MDMA0_S0_CURR_Y_COUNT MDMA_S0_CURR_Y_COUNT /* MemDMA0 Stream 0 Source Current Y Count Register */ |
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| 151 | |
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| 152 | #define MDMA0_D1_NEXT_DESC_PTR MDMA_D1_NEXT_DESC_PTR /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */ |
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| 153 | #define MDMA0_D1_START_ADDR MDMA_D1_START_ADDR /* MemDMA0 Stream 1 Destination Start Address Register */ |
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| 154 | #define MDMA0_D1_CONFIG MDMA_D1_CONFIG /* MemDMA0 Stream 1 Destination Configuration Register */ |
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| 155 | #define MDMA0_D1_X_COUNT MDMA_D1_X_COUNT /* MemDMA0 Stream 1 Destination X Count Register */ |
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| 156 | #define MDMA0_D1_X_MODIFY MDMA_D1_X_MODIFY /* MemDMA0 Stream 1 Destination X Modify Register */ |
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| 157 | #define MDMA0_D1_Y_COUNT MDMA_D1_Y_COUNT /* MemDMA0 Stream 1 Destination Y Count Register */ |
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| 158 | #define MDMA0_D1_Y_MODIFY MDMA_D1_Y_MODIFY /* MemDMA0 Stream 1 Destination Y Modify Register */ |
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| 159 | #define MDMA0_D1_CURR_DESC_PTR MDMA_D1_CURR_DESC_PTR /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */ |
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| 160 | #define MDMA0_D1_CURR_ADDR MDMA_D1_CURR_ADDR /* MemDMA0 Stream 1 Destination Current Address Register */ |
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| 161 | #define MDMA0_D1_IRQ_STATUS MDMA_D1_IRQ_STATUS /* MemDMA0 Stream 1 Destination Interrupt/Status Register */ |
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| 162 | #define MDMA0_D1_PERIPHERAL_MAP MDMA_D1_PERIPHERAL_MAP /* MemDMA0 Stream 1 Destination Peripheral Map Register */ |
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| 163 | #define MDMA0_D1_CURR_X_COUNT MDMA_D1_CURR_X_COUNT /* MemDMA0 Stream 1 Destination Current X Count Register */ |
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| 164 | #define MDMA0_D1_CURR_Y_COUNT MDMA_D1_CURR_Y_COUNT /* MemDMA0 Stream 1 Destination Current Y Count Register */ |
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| 165 | |
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| 166 | #define MDMA0_S1_NEXT_DESC_PTR MDMA_S1_NEXT_DESC_PTR /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */ |
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| 167 | #define MDMA0_S1_START_ADDR MDMA_S1_START_ADDR /* MemDMA0 Stream 1 Source Start Address Register */ |
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| 168 | #define MDMA0_S1_CONFIG MDMA_S1_CONFIG /* MemDMA0 Stream 1 Source Configuration Register */ |
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| 169 | #define MDMA0_S1_X_COUNT MDMA_S1_X_COUNT /* MemDMA0 Stream 1 Source X Count Register */ |
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| 170 | #define MDMA0_S1_X_MODIFY MDMA_S1_X_MODIFY /* MemDMA0 Stream 1 Source X Modify Register */ |
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| 171 | #define MDMA0_S1_Y_COUNT MDMA_S1_Y_COUNT /* MemDMA0 Stream 1 Source Y Count Register */ |
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| 172 | #define MDMA0_S1_Y_MODIFY MDMA_S1_Y_MODIFY /* MemDMA0 Stream 1 Source Y Modify Register */ |
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| 173 | #define MDMA0_S1_CURR_DESC_PTR MDMA_S1_CURR_DESC_PTR /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */ |
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| 174 | #define MDMA0_S1_CURR_ADDR MDMA_S1_CURR_ADDR /* MemDMA0 Stream 1 Source Current Address Register */ |
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| 175 | #define MDMA0_S1_IRQ_STATUS MDMA_S1_IRQ_STATUS /* MemDMA0 Stream 1 Source Interrupt/Status Register */ |
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| 176 | #define MDMA0_S1_PERIPHERAL_MAP MDMA_S1_PERIPHERAL_MAP /* MemDMA0 Stream 1 Source Peripheral Map Register */ |
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| 177 | #define MDMA0_S1_CURR_X_COUNT MDMA_S1_CURR_X_COUNT /* MemDMA0 Stream 1 Source Current X Count Register */ |
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| 178 | #define MDMA0_S1_CURR_Y_COUNT MDMA_S1_CURR_Y_COUNT /* MemDMA0 Stream 1 Source Current Y Count Register */ |
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| 179 | |
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| 180 | |
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| 181 | /* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */ |
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| 182 | #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ |
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| 183 | #define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */ |
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| 184 | #define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */ |
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| 185 | #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ |
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| 186 | #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ |
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| 187 | #define TWI0_MASTER_CTRL 0xFFC01414 /* Master Mode Control Register */ |
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| 188 | #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ |
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| 189 | #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ |
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| 190 | #define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ |
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| 191 | #define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */ |
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| 192 | #define TWI0_FIFO_CTRL 0xFFC01428 /* FIFO Control Register */ |
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| 193 | #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ |
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| 194 | #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ |
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| 195 | #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ |
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| 196 | #define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ |
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| 197 | #define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ |
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| 198 | |
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| 199 | |
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| 200 | /* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */ |
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| 201 | /* Port C */ |
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| 202 | #define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */ |
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| 203 | #define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */ |
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| 204 | #define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */ |
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| 205 | #define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */ |
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| 206 | #define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */ |
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| 207 | #define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */ |
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| 208 | #define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */ |
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| 209 | |
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| 210 | /* Port D */ |
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| 211 | #define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */ |
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| 212 | #define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */ |
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| 213 | #define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */ |
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| 214 | #define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */ |
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| 215 | #define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */ |
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| 216 | #define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */ |
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| 217 | #define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */ |
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| 218 | |
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| 219 | /* Port E */ |
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| 220 | #define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */ |
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| 221 | #define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */ |
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| 222 | #define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */ |
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| 223 | #define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */ |
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| 224 | #define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */ |
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| 225 | #define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */ |
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| 226 | #define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */ |
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| 227 | |
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| 228 | |
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| 229 | /* ADSP-BF538 Adds DMA1 Controller */ |
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| 230 | /* DMA1 Test Registers (0xFFC01B00 - 0xFFC01BFF) */ |
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| 231 | #define DMAC1_TC_PER 0xFFC01B0C /* Traffic Control Periods Register */ |
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| 232 | #define DMAC1_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts Register */ |
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| 233 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ |
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| 234 | #define DMA1_TC_PER DMAC1_TC_PER /* Traffic Control Periods Register */ |
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| 235 | #define DMA1_TC_CNT DMAC1_TC_CNT /* Traffic Control Current Counts Register */ |
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| 236 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ |
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| 237 | #define DMA1_TCPER DMA1_TC_PER /* Traffic Control Periods Register */ |
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| 238 | #define DMA1_TCCNT DMA1_TC_CNT /* Traffic Control Current Counts Register */ |
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| 239 | |
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| 240 | /* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */ |
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| 241 | #define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */ |
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| 242 | #define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */ |
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| 243 | #define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */ |
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| 244 | #define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */ |
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| 245 | #define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */ |
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| 246 | #define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */ |
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| 247 | #define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */ |
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| 248 | #define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */ |
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| 249 | #define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */ |
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| 250 | #define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */ |
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| 251 | #define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */ |
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| 252 | #define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */ |
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| 253 | #define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */ |
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| 254 | |
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| 255 | #define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */ |
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| 256 | #define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */ |
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| 257 | #define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */ |
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| 258 | #define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */ |
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| 259 | #define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */ |
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| 260 | #define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */ |
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| 261 | #define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */ |
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| 262 | #define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */ |
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| 263 | #define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */ |
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| 264 | #define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */ |
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| 265 | #define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */ |
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| 266 | #define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */ |
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| 267 | #define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */ |
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| 268 | |
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| 269 | #define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */ |
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| 270 | #define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */ |
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| 271 | #define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */ |
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| 272 | #define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */ |
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| 273 | #define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */ |
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| 274 | #define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */ |
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| 275 | #define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */ |
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| 276 | #define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */ |
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| 277 | #define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */ |
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| 278 | #define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */ |
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| 279 | #define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */ |
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| 280 | #define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */ |
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| 281 | #define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */ |
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| 282 | |
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| 283 | #define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */ |
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| 284 | #define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */ |
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| 285 | #define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */ |
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| 286 | #define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */ |
---|
| 287 | #define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */ |
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| 288 | #define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */ |
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| 289 | #define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */ |
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| 290 | #define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */ |
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| 291 | #define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */ |
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| 292 | #define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */ |
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| 293 | #define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */ |
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| 294 | #define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */ |
---|
| 295 | #define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */ |
---|
| 296 | |
---|
| 297 | #define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */ |
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| 298 | #define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */ |
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| 299 | #define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */ |
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| 300 | #define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */ |
---|
| 301 | #define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */ |
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| 302 | #define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */ |
---|
| 303 | #define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */ |
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| 304 | #define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */ |
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| 305 | #define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */ |
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| 306 | #define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */ |
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| 307 | #define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */ |
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| 308 | #define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */ |
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| 309 | #define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */ |
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| 310 | |
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| 311 | #define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */ |
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| 312 | #define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */ |
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| 313 | #define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */ |
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| 314 | #define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */ |
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| 315 | #define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */ |
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| 316 | #define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */ |
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| 317 | #define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */ |
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| 318 | #define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */ |
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| 319 | #define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */ |
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| 320 | #define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */ |
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| 321 | #define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */ |
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| 322 | #define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */ |
---|
| 323 | #define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */ |
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| 324 | |
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| 325 | #define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */ |
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| 326 | #define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */ |
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| 327 | #define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */ |
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| 328 | #define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */ |
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| 329 | #define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */ |
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| 330 | #define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */ |
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| 331 | #define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */ |
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| 332 | #define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */ |
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| 333 | #define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */ |
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| 334 | #define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */ |
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| 335 | #define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */ |
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| 336 | #define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */ |
---|
| 337 | #define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */ |
---|
| 338 | |
---|
| 339 | #define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */ |
---|
| 340 | #define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */ |
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| 341 | #define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */ |
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| 342 | #define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */ |
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| 343 | #define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */ |
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| 344 | #define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */ |
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| 345 | #define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */ |
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| 346 | #define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */ |
---|
| 347 | #define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */ |
---|
| 348 | #define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */ |
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| 349 | #define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */ |
---|
| 350 | #define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */ |
---|
| 351 | #define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */ |
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| 352 | |
---|
| 353 | #define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */ |
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| 354 | #define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */ |
---|
| 355 | #define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */ |
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| 356 | #define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */ |
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| 357 | #define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */ |
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| 358 | #define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */ |
---|
| 359 | #define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */ |
---|
| 360 | #define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */ |
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| 361 | #define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */ |
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| 362 | #define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */ |
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| 363 | #define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */ |
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| 364 | #define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */ |
---|
| 365 | #define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */ |
---|
| 366 | |
---|
| 367 | #define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */ |
---|
| 368 | #define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */ |
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| 369 | #define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */ |
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| 370 | #define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */ |
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| 371 | #define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */ |
---|
| 372 | #define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */ |
---|
| 373 | #define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */ |
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| 374 | #define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */ |
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| 375 | #define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */ |
---|
| 376 | #define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */ |
---|
| 377 | #define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */ |
---|
| 378 | #define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */ |
---|
| 379 | #define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */ |
---|
| 380 | |
---|
| 381 | #define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */ |
---|
| 382 | #define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */ |
---|
| 383 | #define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */ |
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| 384 | #define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */ |
---|
| 385 | #define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */ |
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| 386 | #define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */ |
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| 387 | #define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */ |
---|
| 388 | #define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */ |
---|
| 389 | #define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */ |
---|
| 390 | #define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */ |
---|
| 391 | #define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */ |
---|
| 392 | #define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */ |
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| 393 | #define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */ |
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| 394 | |
---|
| 395 | #define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */ |
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| 396 | #define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */ |
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| 397 | #define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */ |
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| 398 | #define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */ |
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| 399 | #define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */ |
---|
| 400 | #define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */ |
---|
| 401 | #define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */ |
---|
| 402 | #define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */ |
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| 403 | #define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */ |
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| 404 | #define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */ |
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| 405 | #define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */ |
---|
| 406 | #define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */ |
---|
| 407 | #define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */ |
---|
| 408 | |
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| 409 | #define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */ |
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| 410 | #define MDMA1_D0_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */ |
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| 411 | #define MDMA1_D0_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */ |
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| 412 | #define MDMA1_D0_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */ |
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| 413 | #define MDMA1_D0_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */ |
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| 414 | #define MDMA1_D0_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */ |
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| 415 | #define MDMA1_D0_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */ |
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| 416 | #define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */ |
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| 417 | #define MDMA1_D0_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */ |
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| 418 | #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */ |
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| 419 | #define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */ |
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| 420 | #define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */ |
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| 421 | #define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */ |
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| 422 | |
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| 423 | #define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */ |
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| 424 | #define MDMA1_S0_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */ |
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| 425 | #define MDMA1_S0_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */ |
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| 426 | #define MDMA1_S0_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */ |
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| 427 | #define MDMA1_S0_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */ |
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| 428 | #define MDMA1_S0_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */ |
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| 429 | #define MDMA1_S0_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */ |
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| 430 | #define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */ |
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| 431 | #define MDMA1_S0_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */ |
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| 432 | #define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */ |
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| 433 | #define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */ |
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| 434 | #define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */ |
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| 435 | #define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */ |
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| 436 | |
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| 437 | #define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */ |
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| 438 | #define MDMA1_D1_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */ |
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| 439 | #define MDMA1_D1_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */ |
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| 440 | #define MDMA1_D1_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */ |
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| 441 | #define MDMA1_D1_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */ |
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| 442 | #define MDMA1_D1_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */ |
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| 443 | #define MDMA1_D1_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */ |
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| 444 | #define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */ |
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| 445 | #define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */ |
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| 446 | #define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */ |
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| 447 | #define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */ |
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| 448 | #define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */ |
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| 449 | #define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */ |
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| 450 | |
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| 451 | #define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */ |
---|
| 452 | #define MDMA1_S1_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */ |
---|
| 453 | #define MDMA1_S1_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */ |
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| 454 | #define MDMA1_S1_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */ |
---|
| 455 | #define MDMA1_S1_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */ |
---|
| 456 | #define MDMA1_S1_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */ |
---|
| 457 | #define MDMA1_S1_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */ |
---|
| 458 | #define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */ |
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| 459 | #define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */ |
---|
| 460 | #define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */ |
---|
| 461 | #define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */ |
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| 462 | #define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */ |
---|
| 463 | #define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */ |
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| 464 | |
---|
| 465 | |
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| 466 | /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ |
---|
| 467 | #define UART1_THR 0xFFC02000 /* Transmit Holding register */ |
---|
| 468 | #define UART1_RBR 0xFFC02000 /* Receive Buffer register */ |
---|
| 469 | #define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ |
---|
| 470 | #define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ |
---|
| 471 | #define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ |
---|
| 472 | #define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ |
---|
| 473 | #define UART1_LCR 0xFFC0200C /* Line Control Register */ |
---|
| 474 | #define UART1_MCR 0xFFC02010 /* Modem Control Register */ |
---|
| 475 | #define UART1_LSR 0xFFC02014 /* Line Status Register */ |
---|
| 476 | #define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ |
---|
| 477 | #define UART1_GCTL 0xFFC02024 /* Global Control Register */ |
---|
| 478 | |
---|
| 479 | |
---|
| 480 | /* UART2 Controller (0xFFC02100 - 0xFFC021FF) */ |
---|
| 481 | #define UART2_THR 0xFFC02100 /* Transmit Holding register */ |
---|
| 482 | #define UART2_RBR 0xFFC02100 /* Receive Buffer register */ |
---|
| 483 | #define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */ |
---|
| 484 | #define UART2_IER 0xFFC02104 /* Interrupt Enable Register */ |
---|
| 485 | #define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */ |
---|
| 486 | #define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */ |
---|
| 487 | #define UART2_LCR 0xFFC0210C /* Line Control Register */ |
---|
| 488 | #define UART2_MCR 0xFFC02110 /* Modem Control Register */ |
---|
| 489 | #define UART2_LSR 0xFFC02114 /* Line Status Register */ |
---|
| 490 | #define UART2_SCR 0xFFC0211C /* SCR Scratch Register */ |
---|
| 491 | #define UART2_GCTL 0xFFC02124 /* Global Control Register */ |
---|
| 492 | |
---|
| 493 | |
---|
| 494 | /* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */ |
---|
| 495 | #define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ |
---|
| 496 | #define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ |
---|
| 497 | #define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */ |
---|
| 498 | #define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ |
---|
| 499 | #define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ |
---|
| 500 | #define TWI1_MASTER_CTRL 0xFFC02214 /* Master Mode Control Register */ |
---|
| 501 | #define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ |
---|
| 502 | #define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ |
---|
| 503 | #define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ |
---|
| 504 | #define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ |
---|
| 505 | #define TWI1_FIFO_CTRL 0xFFC02228 /* FIFO Control Register */ |
---|
| 506 | #define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ |
---|
| 507 | #define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ |
---|
| 508 | #define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ |
---|
| 509 | #define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */ |
---|
| 510 | #define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */ |
---|
| 511 | |
---|
| 512 | |
---|
| 513 | /* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */ |
---|
| 514 | #define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */ |
---|
| 515 | #define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */ |
---|
| 516 | #define SPI1_STAT 0xFFC02308 /* SPI1 Status register */ |
---|
| 517 | #define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */ |
---|
| 518 | #define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */ |
---|
| 519 | #define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */ |
---|
| 520 | #define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */ |
---|
| 521 | |
---|
| 522 | |
---|
| 523 | /* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */ |
---|
| 524 | #define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */ |
---|
| 525 | #define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */ |
---|
| 526 | #define SPI2_STAT 0xFFC02408 /* SPI2 Status register */ |
---|
| 527 | #define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */ |
---|
| 528 | #define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */ |
---|
| 529 | #define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */ |
---|
| 530 | #define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */ |
---|
| 531 | |
---|
| 532 | |
---|
| 533 | /* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */ |
---|
| 534 | #define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */ |
---|
| 535 | #define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */ |
---|
| 536 | #define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */ |
---|
| 537 | #define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */ |
---|
| 538 | #define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */ |
---|
| 539 | #define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */ |
---|
| 540 | #define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */ |
---|
| 541 | #define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */ |
---|
| 542 | #define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */ |
---|
| 543 | #define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */ |
---|
| 544 | #define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */ |
---|
| 545 | #define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */ |
---|
| 546 | #define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */ |
---|
| 547 | #define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */ |
---|
| 548 | #define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */ |
---|
| 549 | #define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */ |
---|
| 550 | #define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */ |
---|
| 551 | #define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */ |
---|
| 552 | #define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */ |
---|
| 553 | #define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */ |
---|
| 554 | #define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */ |
---|
| 555 | #define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */ |
---|
| 556 | |
---|
| 557 | |
---|
| 558 | /* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */ |
---|
| 559 | #define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */ |
---|
| 560 | #define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */ |
---|
| 561 | #define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */ |
---|
| 562 | #define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */ |
---|
| 563 | #define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */ |
---|
| 564 | #define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */ |
---|
| 565 | #define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */ |
---|
| 566 | #define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */ |
---|
| 567 | #define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */ |
---|
| 568 | #define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */ |
---|
| 569 | #define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */ |
---|
| 570 | #define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */ |
---|
| 571 | #define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */ |
---|
| 572 | #define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */ |
---|
| 573 | #define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */ |
---|
| 574 | #define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */ |
---|
| 575 | #define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */ |
---|
| 576 | #define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */ |
---|
| 577 | #define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */ |
---|
| 578 | #define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */ |
---|
| 579 | #define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */ |
---|
| 580 | #define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */ |
---|
| 581 | |
---|
| 582 | |
---|
| 583 | /* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */ |
---|
| 584 | /* For Mailboxes 0-15 */ |
---|
| 585 | #define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ |
---|
| 586 | #define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ |
---|
| 587 | #define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ |
---|
| 588 | #define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ |
---|
| 589 | #define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ |
---|
| 590 | #define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ |
---|
| 591 | #define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ |
---|
| 592 | #define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ |
---|
| 593 | #define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ |
---|
| 594 | #define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ |
---|
| 595 | #define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ |
---|
| 596 | #define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ |
---|
| 597 | #define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */ |
---|
| 598 | |
---|
| 599 | /* For Mailboxes 16-31 */ |
---|
| 600 | #define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ |
---|
| 601 | #define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ |
---|
| 602 | #define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ |
---|
| 603 | #define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ |
---|
| 604 | #define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ |
---|
| 605 | #define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ |
---|
| 606 | #define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ |
---|
| 607 | #define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ |
---|
| 608 | #define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ |
---|
| 609 | #define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ |
---|
| 610 | #define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ |
---|
| 611 | #define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ |
---|
| 612 | #define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */ |
---|
| 613 | |
---|
| 614 | #define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ |
---|
| 615 | #define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ |
---|
| 616 | #define CAN_DEBUG 0xFFC02A88 /* Debug Register */ |
---|
| 617 | #define CAN_STATUS 0xFFC02A8C /* Global Status Register */ |
---|
| 618 | #define CAN_CEC 0xFFC02A90 /* Error Counter Register */ |
---|
| 619 | #define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ |
---|
| 620 | #define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ |
---|
| 621 | #define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ |
---|
| 622 | #define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ |
---|
| 623 | #define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ |
---|
| 624 | #define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ |
---|
| 625 | #define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ |
---|
| 626 | #define CAN_ESR 0xFFC02AB4 /* Error Status Register */ |
---|
| 627 | #define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ |
---|
| 628 | #define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */ |
---|
| 629 | #define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ |
---|
| 630 | |
---|
| 631 | /* Mailbox Acceptance Masks */ |
---|
| 632 | #define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ |
---|
| 633 | #define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ |
---|
| 634 | #define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ |
---|
| 635 | #define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ |
---|
| 636 | #define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ |
---|
| 637 | #define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ |
---|
| 638 | #define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ |
---|
| 639 | #define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ |
---|
| 640 | #define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ |
---|
| 641 | #define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ |
---|
| 642 | #define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ |
---|
| 643 | #define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ |
---|
| 644 | #define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ |
---|
| 645 | #define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ |
---|
| 646 | #define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ |
---|
| 647 | #define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ |
---|
| 648 | #define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ |
---|
| 649 | #define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ |
---|
| 650 | #define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ |
---|
| 651 | #define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ |
---|
| 652 | #define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ |
---|
| 653 | #define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ |
---|
| 654 | #define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ |
---|
| 655 | #define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ |
---|
| 656 | #define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ |
---|
| 657 | #define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ |
---|
| 658 | #define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ |
---|
| 659 | #define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ |
---|
| 660 | #define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ |
---|
| 661 | #define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ |
---|
| 662 | #define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ |
---|
| 663 | #define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ |
---|
| 664 | |
---|
| 665 | #define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ |
---|
| 666 | #define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ |
---|
| 667 | #define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ |
---|
| 668 | #define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ |
---|
| 669 | #define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ |
---|
| 670 | #define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ |
---|
| 671 | #define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ |
---|
| 672 | #define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ |
---|
| 673 | #define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ |
---|
| 674 | #define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ |
---|
| 675 | #define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ |
---|
| 676 | #define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ |
---|
| 677 | #define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ |
---|
| 678 | #define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ |
---|
| 679 | #define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ |
---|
| 680 | #define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ |
---|
| 681 | #define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ |
---|
| 682 | #define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ |
---|
| 683 | #define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ |
---|
| 684 | #define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ |
---|
| 685 | #define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ |
---|
| 686 | #define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ |
---|
| 687 | #define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ |
---|
| 688 | #define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ |
---|
| 689 | #define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ |
---|
| 690 | #define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ |
---|
| 691 | #define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ |
---|
| 692 | #define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ |
---|
| 693 | #define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ |
---|
| 694 | #define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ |
---|
| 695 | #define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ |
---|
| 696 | #define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ |
---|
| 697 | |
---|
| 698 | /* CAN Acceptance Mask Macros */ |
---|
| 699 | #define CAN_AM_L(x) (CAN_AM00L+((x)*0x8)) |
---|
| 700 | #define CAN_AM_H(x) (CAN_AM00H+((x)*0x8)) |
---|
| 701 | |
---|
| 702 | /* Mailbox Registers */ |
---|
| 703 | #define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ |
---|
| 704 | #define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ |
---|
| 705 | #define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ |
---|
| 706 | #define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ |
---|
| 707 | #define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ |
---|
| 708 | #define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ |
---|
| 709 | #define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ |
---|
| 710 | #define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ |
---|
| 711 | |
---|
| 712 | #define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ |
---|
| 713 | #define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ |
---|
| 714 | #define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ |
---|
| 715 | #define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ |
---|
| 716 | #define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ |
---|
| 717 | #define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ |
---|
| 718 | #define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ |
---|
| 719 | #define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ |
---|
| 720 | |
---|
| 721 | #define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ |
---|
| 722 | #define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ |
---|
| 723 | #define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ |
---|
| 724 | #define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ |
---|
| 725 | #define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ |
---|
| 726 | #define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ |
---|
| 727 | #define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ |
---|
| 728 | #define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ |
---|
| 729 | |
---|
| 730 | #define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ |
---|
| 731 | #define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ |
---|
| 732 | #define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ |
---|
| 733 | #define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ |
---|
| 734 | #define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ |
---|
| 735 | #define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ |
---|
| 736 | #define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ |
---|
| 737 | #define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ |
---|
| 738 | |
---|
| 739 | #define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ |
---|
| 740 | #define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ |
---|
| 741 | #define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ |
---|
| 742 | #define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ |
---|
| 743 | #define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ |
---|
| 744 | #define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ |
---|
| 745 | #define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ |
---|
| 746 | #define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ |
---|
| 747 | |
---|
| 748 | #define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ |
---|
| 749 | #define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ |
---|
| 750 | #define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ |
---|
| 751 | #define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ |
---|
| 752 | #define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ |
---|
| 753 | #define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ |
---|
| 754 | #define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ |
---|
| 755 | #define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ |
---|
| 756 | |
---|
| 757 | #define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ |
---|
| 758 | #define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ |
---|
| 759 | #define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ |
---|
| 760 | #define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ |
---|
| 761 | #define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ |
---|
| 762 | #define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ |
---|
| 763 | #define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ |
---|
| 764 | #define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ |
---|
| 765 | |
---|
| 766 | #define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ |
---|
| 767 | #define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ |
---|
| 768 | #define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ |
---|
| 769 | #define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ |
---|
| 770 | #define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ |
---|
| 771 | #define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ |
---|
| 772 | #define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ |
---|
| 773 | #define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ |
---|
| 774 | |
---|
| 775 | #define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ |
---|
| 776 | #define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ |
---|
| 777 | #define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ |
---|
| 778 | #define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ |
---|
| 779 | #define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ |
---|
| 780 | #define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ |
---|
| 781 | #define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ |
---|
| 782 | #define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ |
---|
| 783 | |
---|
| 784 | #define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ |
---|
| 785 | #define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ |
---|
| 786 | #define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ |
---|
| 787 | #define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ |
---|
| 788 | #define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ |
---|
| 789 | #define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ |
---|
| 790 | #define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ |
---|
| 791 | #define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ |
---|
| 792 | |
---|
| 793 | #define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ |
---|
| 794 | #define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ |
---|
| 795 | #define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ |
---|
| 796 | #define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ |
---|
| 797 | #define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ |
---|
| 798 | #define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ |
---|
| 799 | #define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ |
---|
| 800 | #define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ |
---|
| 801 | |
---|
| 802 | #define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ |
---|
| 803 | #define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ |
---|
| 804 | #define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ |
---|
| 805 | #define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ |
---|
| 806 | #define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ |
---|
| 807 | #define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ |
---|
| 808 | #define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ |
---|
| 809 | #define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ |
---|
| 810 | |
---|
| 811 | #define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ |
---|
| 812 | #define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ |
---|
| 813 | #define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ |
---|
| 814 | #define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ |
---|
| 815 | #define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ |
---|
| 816 | #define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ |
---|
| 817 | #define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ |
---|
| 818 | #define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ |
---|
| 819 | |
---|
| 820 | #define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ |
---|
| 821 | #define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ |
---|
| 822 | #define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ |
---|
| 823 | #define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ |
---|
| 824 | #define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ |
---|
| 825 | #define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ |
---|
| 826 | #define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ |
---|
| 827 | #define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ |
---|
| 828 | |
---|
| 829 | #define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ |
---|
| 830 | #define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ |
---|
| 831 | #define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ |
---|
| 832 | #define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ |
---|
| 833 | #define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ |
---|
| 834 | #define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ |
---|
| 835 | #define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ |
---|
| 836 | #define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ |
---|
| 837 | |
---|
| 838 | #define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ |
---|
| 839 | #define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ |
---|
| 840 | #define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ |
---|
| 841 | #define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ |
---|
| 842 | #define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ |
---|
| 843 | #define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ |
---|
| 844 | #define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ |
---|
| 845 | #define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ |
---|
| 846 | |
---|
| 847 | #define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ |
---|
| 848 | #define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ |
---|
| 849 | #define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ |
---|
| 850 | #define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ |
---|
| 851 | #define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ |
---|
| 852 | #define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ |
---|
| 853 | #define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ |
---|
| 854 | #define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ |
---|
| 855 | |
---|
| 856 | #define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ |
---|
| 857 | #define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ |
---|
| 858 | #define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ |
---|
| 859 | #define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ |
---|
| 860 | #define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ |
---|
| 861 | #define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ |
---|
| 862 | #define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ |
---|
| 863 | #define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ |
---|
| 864 | |
---|
| 865 | #define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ |
---|
| 866 | #define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ |
---|
| 867 | #define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ |
---|
| 868 | #define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ |
---|
| 869 | #define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ |
---|
| 870 | #define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ |
---|
| 871 | #define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ |
---|
| 872 | #define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ |
---|
| 873 | |
---|
| 874 | #define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ |
---|
| 875 | #define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ |
---|
| 876 | #define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ |
---|
| 877 | #define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ |
---|
| 878 | #define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ |
---|
| 879 | #define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ |
---|
| 880 | #define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ |
---|
| 881 | #define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ |
---|
| 882 | |
---|
| 883 | #define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ |
---|
| 884 | #define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ |
---|
| 885 | #define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ |
---|
| 886 | #define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ |
---|
| 887 | #define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ |
---|
| 888 | #define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ |
---|
| 889 | #define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ |
---|
| 890 | #define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ |
---|
| 891 | |
---|
| 892 | #define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ |
---|
| 893 | #define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ |
---|
| 894 | #define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ |
---|
| 895 | #define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ |
---|
| 896 | #define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ |
---|
| 897 | #define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ |
---|
| 898 | #define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ |
---|
| 899 | #define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ |
---|
| 900 | |
---|
| 901 | #define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ |
---|
| 902 | #define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ |
---|
| 903 | #define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ |
---|
| 904 | #define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ |
---|
| 905 | #define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ |
---|
| 906 | #define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ |
---|
| 907 | #define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ |
---|
| 908 | #define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ |
---|
| 909 | |
---|
| 910 | #define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ |
---|
| 911 | #define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ |
---|
| 912 | #define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ |
---|
| 913 | #define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ |
---|
| 914 | #define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ |
---|
| 915 | #define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ |
---|
| 916 | #define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ |
---|
| 917 | #define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ |
---|
| 918 | |
---|
| 919 | #define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ |
---|
| 920 | #define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ |
---|
| 921 | #define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ |
---|
| 922 | #define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ |
---|
| 923 | #define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ |
---|
| 924 | #define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ |
---|
| 925 | #define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ |
---|
| 926 | #define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ |
---|
| 927 | |
---|
| 928 | #define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ |
---|
| 929 | #define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ |
---|
| 930 | #define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ |
---|
| 931 | #define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ |
---|
| 932 | #define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ |
---|
| 933 | #define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ |
---|
| 934 | #define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ |
---|
| 935 | #define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ |
---|
| 936 | |
---|
| 937 | #define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ |
---|
| 938 | #define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ |
---|
| 939 | #define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ |
---|
| 940 | #define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ |
---|
| 941 | #define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ |
---|
| 942 | #define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ |
---|
| 943 | #define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ |
---|
| 944 | #define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ |
---|
| 945 | |
---|
| 946 | #define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ |
---|
| 947 | #define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ |
---|
| 948 | #define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ |
---|
| 949 | #define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ |
---|
| 950 | #define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ |
---|
| 951 | #define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ |
---|
| 952 | #define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ |
---|
| 953 | #define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ |
---|
| 954 | |
---|
| 955 | #define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ |
---|
| 956 | #define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ |
---|
| 957 | #define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ |
---|
| 958 | #define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ |
---|
| 959 | #define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ |
---|
| 960 | #define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ |
---|
| 961 | #define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ |
---|
| 962 | #define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ |
---|
| 963 | |
---|
| 964 | #define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ |
---|
| 965 | #define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ |
---|
| 966 | #define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ |
---|
| 967 | #define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ |
---|
| 968 | #define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ |
---|
| 969 | #define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ |
---|
| 970 | #define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ |
---|
| 971 | #define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ |
---|
| 972 | |
---|
| 973 | #define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ |
---|
| 974 | #define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ |
---|
| 975 | #define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ |
---|
| 976 | #define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ |
---|
| 977 | #define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ |
---|
| 978 | #define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ |
---|
| 979 | #define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ |
---|
| 980 | #define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ |
---|
| 981 | |
---|
| 982 | #define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ |
---|
| 983 | #define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ |
---|
| 984 | #define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ |
---|
| 985 | #define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ |
---|
| 986 | #define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ |
---|
| 987 | #define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ |
---|
| 988 | #define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ |
---|
| 989 | #define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ |
---|
| 990 | |
---|
| 991 | /* CAN Mailbox Area Macros */ |
---|
| 992 | #define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20)) |
---|
| 993 | #define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20)) |
---|
| 994 | #define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20)) |
---|
| 995 | #define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20)) |
---|
| 996 | #define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20)) |
---|
| 997 | #define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20)) |
---|
| 998 | #define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20)) |
---|
| 999 | #define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20)) |
---|
| 1000 | |
---|
| 1001 | |
---|
| 1002 | /************************************************************************************ |
---|
| 1003 | ** System MMR Register Bits And Macros |
---|
| 1004 | ************************************************************************************* |
---|
| 1005 | **/ |
---|
| 1006 | |
---|
| 1007 | /* ********************* PLL AND RESET MASKS ****************************************/ |
---|
| 1008 | |
---|
| 1009 | /* PLL_CTL Masks (IN_DELAY and OUT_DELAY bit field definitions differ from BF533/BF532/BF531) */ |
---|
| 1010 | #define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ |
---|
| 1011 | #define IN_DELAY 0x0014 /* EBIU Input Delay Select */ |
---|
| 1012 | #define OUT_DELAY 0x00C0 /* EBIU Output Delay Select */ |
---|
| 1013 | |
---|
| 1014 | #ifdef _MISRA_RULES |
---|
| 1015 | #define SET_OUT_DELAY(x) (((x)&0x03u) << 0x6) |
---|
| 1016 | #define SET_IN_DELAY(x) ((((x)&0x02u) << 0x3) | (((x)&0x01u) << 0x2)) |
---|
| 1017 | #else |
---|
| 1018 | #define SET_OUT_DELAY(x) (((x)&0x03) << 0x6) |
---|
| 1019 | #define SET_IN_DELAY(x) ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2)) |
---|
| 1020 | #endif /* _MISRA_RULES */ |
---|
| 1021 | |
---|
| 1022 | /* VR_CTL Masks (Additional WakeUp Events) */ |
---|
| 1023 | #define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ |
---|
| 1024 | #define GPWE 0x0400 /* Enable General-Purpose Wakeup From Hibernate */ |
---|
| 1025 | |
---|
| 1026 | |
---|
| 1027 | /* ********************** SYSTEM INTERRUPT CONTROLLER MASKS ********************** */ |
---|
| 1028 | /* Peripheral Masks For SIC_ISR0, SIC_IWR0, SIC_IMASK0 */ |
---|
| 1029 | #define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */ |
---|
| 1030 | #define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */ |
---|
| 1031 | #define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */ |
---|
| 1032 | #define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */ |
---|
| 1033 | #define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */ |
---|
| 1034 | #define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */ |
---|
| 1035 | #define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */ |
---|
| 1036 | #define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */ |
---|
| 1037 | #define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */ |
---|
| 1038 | #define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */ |
---|
| 1039 | #define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */ |
---|
| 1040 | #define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */ |
---|
| 1041 | |
---|
| 1042 | #define DMA0_ERR_IRQ DMAC0_ERR_IRQ /* legacy */ |
---|
| 1043 | #define DMA1_ERR_IRQ DMAC1_ERR_IRQ /* legacy */ |
---|
| 1044 | |
---|
| 1045 | /* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */ |
---|
| 1046 | #define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */ |
---|
| 1047 | #define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */ |
---|
| 1048 | #define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */ |
---|
| 1049 | #define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */ |
---|
| 1050 | #define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */ |
---|
| 1051 | #define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */ |
---|
| 1052 | #define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */ |
---|
| 1053 | #define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */ |
---|
| 1054 | #define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */ |
---|
| 1055 | #define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */ |
---|
| 1056 | #define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */ |
---|
| 1057 | #define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */ |
---|
| 1058 | #define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */ |
---|
| 1059 | #define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */ |
---|
| 1060 | #define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */ |
---|
| 1061 | #define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */ |
---|
| 1062 | #define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */ |
---|
| 1063 | #define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */ |
---|
| 1064 | #define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */ |
---|
| 1065 | |
---|
| 1066 | #ifdef _MISRA_RULES |
---|
| 1067 | #define _MF15 0xFu |
---|
| 1068 | #define _MF7 7u |
---|
| 1069 | #else |
---|
| 1070 | #define _MF15 0xF |
---|
| 1071 | #define _MF7 7 |
---|
| 1072 | #endif /* _MISRA_RULES */ |
---|
| 1073 | /* SIC_IAR3 Macros */ |
---|
| 1074 | #define P24_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #24 assigned IVG #x */ |
---|
| 1075 | #define P25_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #25 assigned IVG #x */ |
---|
| 1076 | #define P26_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #26 assigned IVG #x */ |
---|
| 1077 | #define P27_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #27 assigned IVG #x */ |
---|
| 1078 | #define P28_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #28 assigned IVG #x */ |
---|
| 1079 | #define P29_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #29 assigned IVG #x */ |
---|
| 1080 | #define P30_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #30 assigned IVG #x */ |
---|
| 1081 | #define P31_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #31 assigned IVG #x */ |
---|
| 1082 | |
---|
| 1083 | /* SIC_IAR4 Macros */ |
---|
| 1084 | #define P32_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #32 assigned IVG #x */ |
---|
| 1085 | #define P33_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #33 assigned IVG #x */ |
---|
| 1086 | #define P34_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #34 assigned IVG #x */ |
---|
| 1087 | #define P35_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #35 assigned IVG #x */ |
---|
| 1088 | #define P36_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #36 assigned IVG #x */ |
---|
| 1089 | #define P37_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #37 assigned IVG #x */ |
---|
| 1090 | #define P38_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #38 assigned IVG #x */ |
---|
| 1091 | #define P39_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #39 assigned IVG #x */ |
---|
| 1092 | |
---|
| 1093 | /* SIC_IAR5 Macros */ |
---|
| 1094 | #define P40_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #40 assigned IVG #x */ |
---|
| 1095 | #define P41_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #41 assigned IVG #x */ |
---|
| 1096 | #define P42_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #42 assigned IVG #x */ |
---|
| 1097 | #define P43_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #43 assigned IVG #x */ |
---|
| 1098 | #define P44_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #44 assigned IVG #x */ |
---|
| 1099 | #define P45_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #45 assigned IVG #x */ |
---|
| 1100 | #define P46_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #46 assigned IVG #x */ |
---|
| 1101 | #define P47_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #47 assigned IVG #x */ |
---|
| 1102 | |
---|
| 1103 | /* SIC_IAR6 Macros */ |
---|
| 1104 | #define P48_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #48 assigned IVG #x */ |
---|
| 1105 | #define P49_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #49 assigned IVG #x */ |
---|
| 1106 | #define P50_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #50 assigned IVG #x */ |
---|
| 1107 | #define P51_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #51 assigned IVG #x */ |
---|
| 1108 | #define P52_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #52 assigned IVG #x */ |
---|
| 1109 | #define P53_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #53 assigned IVG #x */ |
---|
| 1110 | #define P54_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #54 assigned IVG #x */ |
---|
| 1111 | #define P55_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #55 assigned IVG #x */ |
---|
| 1112 | |
---|
| 1113 | |
---|
| 1114 | /******************* GPIO MASKS *********************/ |
---|
| 1115 | /* Port C Masks */ |
---|
| 1116 | #define PC0 0x0001 |
---|
| 1117 | #define PC1 0x0002 |
---|
| 1118 | #define PC4 0x0010 |
---|
| 1119 | #define PC5 0x0020 |
---|
| 1120 | #define PC6 0x0040 |
---|
| 1121 | #define PC7 0x0080 |
---|
| 1122 | #define PC8 0x0100 |
---|
| 1123 | #define PC9 0x0200 |
---|
| 1124 | /* Port C Bit Positions */ |
---|
| 1125 | #define PC0_P 0x0 |
---|
| 1126 | #define PC1_P 0x1 |
---|
| 1127 | #define PC4_P 0x4 |
---|
| 1128 | #define PC5_P 0x5 |
---|
| 1129 | #define PC6_P 0x6 |
---|
| 1130 | #define PC7_P 0x7 |
---|
| 1131 | #define PC8_P 0x8 |
---|
| 1132 | #define PC9_P 0x9 |
---|
| 1133 | |
---|
| 1134 | /* Port D */ |
---|
| 1135 | #define PD0 0x0001 |
---|
| 1136 | #define PD1 0x0002 |
---|
| 1137 | #define PD2 0x0004 |
---|
| 1138 | #define PD3 0x0008 |
---|
| 1139 | #define PD4 0x0010 |
---|
| 1140 | #define PD5 0x0020 |
---|
| 1141 | #define PD6 0x0040 |
---|
| 1142 | #define PD7 0x0080 |
---|
| 1143 | #define PD8 0x0100 |
---|
| 1144 | #define PD9 0x0200 |
---|
| 1145 | #define PD10 0x0400 |
---|
| 1146 | #define PD11 0x0800 |
---|
| 1147 | #define PD12 0x1000 |
---|
| 1148 | #define PD13 0x2000 |
---|
| 1149 | #define PD14 0x4000 |
---|
| 1150 | #define PD15 0x8000 |
---|
| 1151 | /* Port D Bit Positions */ |
---|
| 1152 | #define PD0_P 0x0 |
---|
| 1153 | #define PD1_P 0x1 |
---|
| 1154 | #define PD2_P 0x2 |
---|
| 1155 | #define PD3_P 0x3 |
---|
| 1156 | #define PD4_P 0x4 |
---|
| 1157 | #define PD5_P 0x5 |
---|
| 1158 | #define PD6_P 0x6 |
---|
| 1159 | #define PD7_P 0x7 |
---|
| 1160 | #define PD8_P 0x8 |
---|
| 1161 | #define PD9_P 0x9 |
---|
| 1162 | #define PD10_P 0xA |
---|
| 1163 | #define PD11_P 0xB |
---|
| 1164 | #define PD12_P 0xC |
---|
| 1165 | #define PD13_P 0xD |
---|
| 1166 | #define PD14_P 0xE |
---|
| 1167 | #define PD15_P 0xF |
---|
| 1168 | |
---|
| 1169 | /* Port E */ |
---|
| 1170 | #define PE0 0x0001 |
---|
| 1171 | #define PE1 0x0002 |
---|
| 1172 | #define PE2 0x0004 |
---|
| 1173 | #define PE3 0x0008 |
---|
| 1174 | #define PE4 0x0010 |
---|
| 1175 | #define PE5 0x0020 |
---|
| 1176 | #define PE6 0x0040 |
---|
| 1177 | #define PE7 0x0080 |
---|
| 1178 | #define PE8 0x0100 |
---|
| 1179 | #define PE9 0x0200 |
---|
| 1180 | #define PE10 0x0400 |
---|
| 1181 | #define PE11 0x0800 |
---|
| 1182 | #define PE12 0x1000 |
---|
| 1183 | #define PE13 0x2000 |
---|
| 1184 | #define PE14 0x4000 |
---|
| 1185 | #define PE15 0x8000 |
---|
| 1186 | /* Port E Bit Positions */ |
---|
| 1187 | #define PE0_P 0x0 |
---|
| 1188 | #define PE1_P 0x1 |
---|
| 1189 | #define PE2_P 0x2 |
---|
| 1190 | #define PE3_P 0x3 |
---|
| 1191 | #define PE4_P 0x4 |
---|
| 1192 | #define PE5_P 0x5 |
---|
| 1193 | #define PE6_P 0x6 |
---|
| 1194 | #define PE7_P 0x7 |
---|
| 1195 | #define PE8_P 0x8 |
---|
| 1196 | #define PE9_P 0x9 |
---|
| 1197 | #define PE10_P 0xA |
---|
| 1198 | #define PE11_P 0xB |
---|
| 1199 | #define PE12_P 0xC |
---|
| 1200 | #define PE13_P 0xD |
---|
| 1201 | #define PE14_P 0xE |
---|
| 1202 | #define PE15_P 0xF |
---|
| 1203 | |
---|
| 1204 | |
---|
| 1205 | /* **************** DMA CONTROLLER 0 (DMAC0) MASKS ***************************/ |
---|
| 1206 | /* PMAP Encodings For DMA Controller 0 */ |
---|
| 1207 | #define PMAP_SPI0 PMAP_SPI /* PMAP SPI0 DMA */ |
---|
| 1208 | #define PMAP_UART0RX PMAP_UARTRX /* PMAP UART0 Receive DMA */ |
---|
| 1209 | #define PMAP_UART0TX PMAP_UARTTX /* PMAP UART0 Transmit DMA */ |
---|
| 1210 | |
---|
| 1211 | /* **************** DMA CONTROLLER 1 (DMAC1) MASKS ***************************/ |
---|
| 1212 | /* PMAP Encodings For DMA Controller 1 */ |
---|
| 1213 | #define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */ |
---|
| 1214 | #define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */ |
---|
| 1215 | #define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */ |
---|
| 1216 | #define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */ |
---|
| 1217 | #define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */ |
---|
| 1218 | #define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */ |
---|
| 1219 | #define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */ |
---|
| 1220 | #define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */ |
---|
| 1221 | #define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */ |
---|
| 1222 | #define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */ |
---|
| 1223 | |
---|
| 1224 | /* EBIU_SDBCTL Masks */ |
---|
| 1225 | #define EBSZ 0x0006 /* SDRAM external bank size */ |
---|
| 1226 | #define EBCAW 0x0030 /* SDRAM external bank column address width */ |
---|
| 1227 | |
---|
| 1228 | /* EBIU_SDGCTL Masks */ |
---|
| 1229 | #define CL 0x0000000C /* SDRAM CAS latency */ |
---|
| 1230 | #define PASR 0x00000030 /* SDRAM partial array self-refresh */ |
---|
| 1231 | #define TRAS 0x000003C0 /* SDRAM tRAS in SCLK cycles */ |
---|
| 1232 | #define TRP 0x00003800 /* SDRAM tRP in SCLK cycles */ |
---|
| 1233 | #define TRCD 0x00030000 /* SDRAM tRCD in SCLK cycles */ |
---|
| 1234 | #define TWR 0x00180000 /* SDRAM tWR in SCLK cycles */ |
---|
| 1235 | |
---|
| 1236 | /* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/ |
---|
| 1237 | /* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ |
---|
| 1238 | #ifdef _MISRA_RULES |
---|
| 1239 | #define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */ |
---|
| 1240 | #define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */ |
---|
| 1241 | #else |
---|
| 1242 | #define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ |
---|
| 1243 | #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ |
---|
| 1244 | #endif /* _MISRA_RULES */ |
---|
| 1245 | |
---|
| 1246 | /* TWIx_PRESCALE Masks */ |
---|
| 1247 | #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ |
---|
| 1248 | #define TWI_ENA 0x0080 /* TWI Enable */ |
---|
| 1249 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ |
---|
| 1250 | |
---|
| 1251 | /* TWIx_SLAVE_CTRL Masks */ |
---|
| 1252 | #define SEN 0x0001 /* Slave Enable */ |
---|
| 1253 | #define SADD_LEN 0x0002 /* Slave Address Length */ |
---|
| 1254 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ |
---|
| 1255 | #define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ |
---|
| 1256 | #define GEN 0x0010 /* General Call Adrress Matching Enabled */ |
---|
| 1257 | |
---|
| 1258 | /* TWIx_SLAVE_STAT Masks */ |
---|
| 1259 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ |
---|
| 1260 | #define GCALL 0x0002 /* General Call Indicator */ |
---|
| 1261 | |
---|
| 1262 | /* TWIx_MASTER_CTRL Masks */ |
---|
| 1263 | #define MEN 0x0001 /* Master Mode Enable */ |
---|
| 1264 | #define MADD_LEN 0x0002 /* Master Address Length */ |
---|
| 1265 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ |
---|
| 1266 | #define FAST 0x0008 /* Use Fast Mode Timing Specs */ |
---|
| 1267 | #define STOP 0x0010 /* Issue Stop Condition */ |
---|
| 1268 | #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ |
---|
| 1269 | #define DCNT 0x3FC0 /* Data Bytes To Transfer */ |
---|
| 1270 | #define SDAOVR 0x4000 /* Serial Data Override */ |
---|
| 1271 | #define SCLOVR 0x8000 /* Serial Clock Override */ |
---|
| 1272 | |
---|
| 1273 | /* TWIx_MASTER_STAT Masks */ |
---|
| 1274 | #define MPROG 0x0001 /* Master Transfer In Progress */ |
---|
| 1275 | #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ |
---|
| 1276 | #define ANAK 0x0004 /* Address Not Acknowledged */ |
---|
| 1277 | #define DNAK 0x0008 /* Data Not Acknowledged */ |
---|
| 1278 | #define BUFRDERR 0x0010 /* Buffer Read Error */ |
---|
| 1279 | #define BUFWRERR 0x0020 /* Buffer Write Error */ |
---|
| 1280 | #define SDASEN 0x0040 /* Serial Data Sense */ |
---|
| 1281 | #define SCLSEN 0x0080 /* Serial Clock Sense */ |
---|
| 1282 | #define BUSBUSY 0x0100 /* Bus Busy Indicator */ |
---|
| 1283 | |
---|
| 1284 | /* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */ |
---|
| 1285 | #define SINIT 0x0001 /* Slave Transfer Initiated */ |
---|
| 1286 | #define SCOMP 0x0002 /* Slave Transfer Complete */ |
---|
| 1287 | #define SERR 0x0004 /* Slave Transfer Error */ |
---|
| 1288 | #define SOVF 0x0008 /* Slave Overflow */ |
---|
| 1289 | #define MCOMP 0x0010 /* Master Transfer Complete */ |
---|
| 1290 | #define MERR 0x0020 /* Master Transfer Error */ |
---|
| 1291 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ |
---|
| 1292 | #define RCVSERV 0x0080 /* Receive FIFO Service */ |
---|
| 1293 | |
---|
| 1294 | /* TWIx_FIFO_CTRL Masks */ |
---|
| 1295 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ |
---|
| 1296 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ |
---|
| 1297 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ |
---|
| 1298 | #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ |
---|
| 1299 | |
---|
| 1300 | /* TWIx_FIFO_STAT Masks */ |
---|
| 1301 | #define XMTSTAT 0x0003 /* Transmit FIFO Status */ |
---|
| 1302 | #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ |
---|
| 1303 | #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ |
---|
| 1304 | #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ |
---|
| 1305 | |
---|
| 1306 | #define RCVSTAT 0x000C /* Receive FIFO Status */ |
---|
| 1307 | #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ |
---|
| 1308 | #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ |
---|
| 1309 | #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ |
---|
| 1310 | |
---|
| 1311 | |
---|
| 1312 | /* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/ |
---|
| 1313 | /* CAN_CONTROL Masks */ |
---|
| 1314 | #define SRS 0x0001 /* Software Reset */ |
---|
| 1315 | #define DNM 0x0002 /* Device Net Mode */ |
---|
| 1316 | #define ABO 0x0004 /* Auto-Bus On Enable */ |
---|
| 1317 | #define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */ |
---|
| 1318 | #define SMR 0x0020 /* Sleep Mode Request */ |
---|
| 1319 | #define CSR 0x0040 /* CAN Suspend Mode Request */ |
---|
| 1320 | #define CCR 0x0080 /* CAN Configuration Mode Request */ |
---|
| 1321 | |
---|
| 1322 | /* CAN_STATUS Masks */ |
---|
| 1323 | #define WT 0x0001 /* TX Warning Flag */ |
---|
| 1324 | #define WR 0x0002 /* RX Warning Flag */ |
---|
| 1325 | #define EP 0x0004 /* Error Passive Mode */ |
---|
| 1326 | #define EBO 0x0008 /* Error Bus Off Mode */ |
---|
| 1327 | #define CSA 0x0040 /* Suspend Mode Acknowledge */ |
---|
| 1328 | #define CCA 0x0080 /* Configuration Mode Acknowledge */ |
---|
| 1329 | #define MBPTR 0x1F00 /* Mailbox Pointer */ |
---|
| 1330 | #define TRM 0x4000 /* Transmit Mode */ |
---|
| 1331 | #define REC 0x8000 /* Receive Mode */ |
---|
| 1332 | |
---|
| 1333 | /* CAN_CLOCK Masks */ |
---|
| 1334 | #define BRP 0x03FF /* Bit-Rate Pre-Scaler */ |
---|
| 1335 | |
---|
| 1336 | /* CAN_TIMING Masks */ |
---|
| 1337 | #define TSEG1 0x000F /* Time Segment 1 */ |
---|
| 1338 | #define TSEG2 0x0070 /* Time Segment 2 */ |
---|
| 1339 | #define SAM 0x0080 /* Sampling */ |
---|
| 1340 | #define SJW 0x0300 /* Synchronization Jump Width */ |
---|
| 1341 | |
---|
| 1342 | /* CAN_DEBUG Masks */ |
---|
| 1343 | #define DEC 0x0001 /* Disable CAN Error Counters */ |
---|
| 1344 | #define DRI 0x0002 /* Disable CAN RX Input */ |
---|
| 1345 | #define DTO 0x0004 /* Disable CAN TX Output */ |
---|
| 1346 | #define DIL 0x0008 /* Disable CAN Internal Loop */ |
---|
| 1347 | #define MAA 0x0010 /* Mode Auto-Acknowledge Enable */ |
---|
| 1348 | #define MRB 0x0020 /* Mode Read Back Enable */ |
---|
| 1349 | #define CDE 0x8000 /* CAN Debug Enable */ |
---|
| 1350 | |
---|
| 1351 | /* CAN_CEC Masks */ |
---|
| 1352 | #define RXECNT 0x00FF /* Receive Error Counter */ |
---|
| 1353 | #define TXECNT 0xFF00 /* Transmit Error Counter */ |
---|
| 1354 | |
---|
| 1355 | /* CAN_INTR Masks */ |
---|
| 1356 | #define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */ |
---|
| 1357 | #define MBRIF MBRIRQ /* legacy */ |
---|
| 1358 | #define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */ |
---|
| 1359 | #define MBTIF MBTIRQ /* legacy */ |
---|
| 1360 | #define GIRQ 0x0004 /* Global Interrupt */ |
---|
| 1361 | #define SMACK 0x0008 /* Sleep Mode Acknowledge */ |
---|
| 1362 | #define CANTX 0x0040 /* CAN TX Bus Value */ |
---|
| 1363 | #define CANRX 0x0080 /* CAN RX Bus Value */ |
---|
| 1364 | |
---|
| 1365 | /* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */ |
---|
| 1366 | #define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */ |
---|
| 1367 | #define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */ |
---|
| 1368 | #define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */ |
---|
| 1369 | #define BASEID 0x1FFC /* Base Identifier */ |
---|
| 1370 | #define IDE 0x2000 /* Identifier Extension */ |
---|
| 1371 | #define RTR 0x4000 /* Remote Frame Transmission Request */ |
---|
| 1372 | #define AME 0x8000 /* Acceptance Mask Enable */ |
---|
| 1373 | |
---|
| 1374 | /* CAN_MBxx_TIMESTAMP Masks */ |
---|
| 1375 | #define TSV 0xFFFF /* Timestamp */ |
---|
| 1376 | |
---|
| 1377 | /* CAN_MBxx_LENGTH Masks */ |
---|
| 1378 | #define DLC 0x000F /* Data Length Code */ |
---|
| 1379 | |
---|
| 1380 | /* CAN_AMxxH and CAN_AMxxL Masks */ |
---|
| 1381 | #define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */ |
---|
| 1382 | #define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */ |
---|
| 1383 | #define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */ |
---|
| 1384 | #define BASEID 0x1FFC /* Base Identifier */ |
---|
| 1385 | #define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */ |
---|
| 1386 | #define FMD 0x4000 /* Full Mask Data Field Enable */ |
---|
| 1387 | #define FDF 0x8000 /* Filter On Data Field Enable */ |
---|
| 1388 | |
---|
| 1389 | /* CAN_MC1 Masks */ |
---|
| 1390 | #define MC0 0x0001 /* Enable Mailbox 0 */ |
---|
| 1391 | #define MC1 0x0002 /* Enable Mailbox 1 */ |
---|
| 1392 | #define MC2 0x0004 /* Enable Mailbox 2 */ |
---|
| 1393 | #define MC3 0x0008 /* Enable Mailbox 3 */ |
---|
| 1394 | #define MC4 0x0010 /* Enable Mailbox 4 */ |
---|
| 1395 | #define MC5 0x0020 /* Enable Mailbox 5 */ |
---|
| 1396 | #define MC6 0x0040 /* Enable Mailbox 6 */ |
---|
| 1397 | #define MC7 0x0080 /* Enable Mailbox 7 */ |
---|
| 1398 | #define MC8 0x0100 /* Enable Mailbox 8 */ |
---|
| 1399 | #define MC9 0x0200 /* Enable Mailbox 9 */ |
---|
| 1400 | #define MC10 0x0400 /* Enable Mailbox 10 */ |
---|
| 1401 | #define MC11 0x0800 /* Enable Mailbox 11 */ |
---|
| 1402 | #define MC12 0x1000 /* Enable Mailbox 12 */ |
---|
| 1403 | #define MC13 0x2000 /* Enable Mailbox 13 */ |
---|
| 1404 | #define MC14 0x4000 /* Enable Mailbox 14 */ |
---|
| 1405 | #define MC15 0x8000 /* Enable Mailbox 15 */ |
---|
| 1406 | |
---|
| 1407 | /* CAN_MC2 Masks */ |
---|
| 1408 | #define MC16 0x0001 /* Enable Mailbox 16 */ |
---|
| 1409 | #define MC17 0x0002 /* Enable Mailbox 17 */ |
---|
| 1410 | #define MC18 0x0004 /* Enable Mailbox 18 */ |
---|
| 1411 | #define MC19 0x0008 /* Enable Mailbox 19 */ |
---|
| 1412 | #define MC20 0x0010 /* Enable Mailbox 20 */ |
---|
| 1413 | #define MC21 0x0020 /* Enable Mailbox 21 */ |
---|
| 1414 | #define MC22 0x0040 /* Enable Mailbox 22 */ |
---|
| 1415 | #define MC23 0x0080 /* Enable Mailbox 23 */ |
---|
| 1416 | #define MC24 0x0100 /* Enable Mailbox 24 */ |
---|
| 1417 | #define MC25 0x0200 /* Enable Mailbox 25 */ |
---|
| 1418 | #define MC26 0x0400 /* Enable Mailbox 26 */ |
---|
| 1419 | #define MC27 0x0800 /* Enable Mailbox 27 */ |
---|
| 1420 | #define MC28 0x1000 /* Enable Mailbox 28 */ |
---|
| 1421 | #define MC29 0x2000 /* Enable Mailbox 29 */ |
---|
| 1422 | #define MC30 0x4000 /* Enable Mailbox 30 */ |
---|
| 1423 | #define MC31 0x8000 /* Enable Mailbox 31 */ |
---|
| 1424 | |
---|
| 1425 | /* CAN_MD1 Masks */ |
---|
| 1426 | #define MD0 0x0001 /* Enable Mailbox 0 For Receive */ |
---|
| 1427 | #define MD1 0x0002 /* Enable Mailbox 1 For Receive */ |
---|
| 1428 | #define MD2 0x0004 /* Enable Mailbox 2 For Receive */ |
---|
| 1429 | #define MD3 0x0008 /* Enable Mailbox 3 For Receive */ |
---|
| 1430 | #define MD4 0x0010 /* Enable Mailbox 4 For Receive */ |
---|
| 1431 | #define MD5 0x0020 /* Enable Mailbox 5 For Receive */ |
---|
| 1432 | #define MD6 0x0040 /* Enable Mailbox 6 For Receive */ |
---|
| 1433 | #define MD7 0x0080 /* Enable Mailbox 7 For Receive */ |
---|
| 1434 | #define MD8 0x0100 /* Enable Mailbox 8 For Receive */ |
---|
| 1435 | #define MD9 0x0200 /* Enable Mailbox 9 For Receive */ |
---|
| 1436 | #define MD10 0x0400 /* Enable Mailbox 10 For Receive */ |
---|
| 1437 | #define MD11 0x0800 /* Enable Mailbox 11 For Receive */ |
---|
| 1438 | #define MD12 0x1000 /* Enable Mailbox 12 For Receive */ |
---|
| 1439 | #define MD13 0x2000 /* Enable Mailbox 13 For Receive */ |
---|
| 1440 | #define MD14 0x4000 /* Enable Mailbox 14 For Receive */ |
---|
| 1441 | #define MD15 0x8000 /* Enable Mailbox 15 For Receive */ |
---|
| 1442 | |
---|
| 1443 | /* CAN_MD2 Masks */ |
---|
| 1444 | #define MD16 0x0001 /* Enable Mailbox 16 For Receive */ |
---|
| 1445 | #define MD17 0x0002 /* Enable Mailbox 17 For Receive */ |
---|
| 1446 | #define MD18 0x0004 /* Enable Mailbox 18 For Receive */ |
---|
| 1447 | #define MD19 0x0008 /* Enable Mailbox 19 For Receive */ |
---|
| 1448 | #define MD20 0x0010 /* Enable Mailbox 20 For Receive */ |
---|
| 1449 | #define MD21 0x0020 /* Enable Mailbox 21 For Receive */ |
---|
| 1450 | #define MD22 0x0040 /* Enable Mailbox 22 For Receive */ |
---|
| 1451 | #define MD23 0x0080 /* Enable Mailbox 23 For Receive */ |
---|
| 1452 | #define MD24 0x0100 /* Enable Mailbox 24 For Receive */ |
---|
| 1453 | #define MD25 0x0200 /* Enable Mailbox 25 For Receive */ |
---|
| 1454 | #define MD26 0x0400 /* Enable Mailbox 26 For Receive */ |
---|
| 1455 | #define MD27 0x0800 /* Enable Mailbox 27 For Receive */ |
---|
| 1456 | #define MD28 0x1000 /* Enable Mailbox 28 For Receive */ |
---|
| 1457 | #define MD29 0x2000 /* Enable Mailbox 29 For Receive */ |
---|
| 1458 | #define MD30 0x4000 /* Enable Mailbox 30 For Receive */ |
---|
| 1459 | #define MD31 0x8000 /* Enable Mailbox 31 For Receive */ |
---|
| 1460 | |
---|
| 1461 | /* CAN_RMP1 Masks */ |
---|
| 1462 | #define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */ |
---|
| 1463 | #define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */ |
---|
| 1464 | #define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */ |
---|
| 1465 | #define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */ |
---|
| 1466 | #define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */ |
---|
| 1467 | #define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */ |
---|
| 1468 | #define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */ |
---|
| 1469 | #define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */ |
---|
| 1470 | #define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */ |
---|
| 1471 | #define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */ |
---|
| 1472 | #define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */ |
---|
| 1473 | #define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */ |
---|
| 1474 | #define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */ |
---|
| 1475 | #define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */ |
---|
| 1476 | #define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */ |
---|
| 1477 | #define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */ |
---|
| 1478 | |
---|
| 1479 | /* CAN_RMP2 Masks */ |
---|
| 1480 | #define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */ |
---|
| 1481 | #define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */ |
---|
| 1482 | #define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */ |
---|
| 1483 | #define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */ |
---|
| 1484 | #define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */ |
---|
| 1485 | #define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */ |
---|
| 1486 | #define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */ |
---|
| 1487 | #define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */ |
---|
| 1488 | #define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */ |
---|
| 1489 | #define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */ |
---|
| 1490 | #define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */ |
---|
| 1491 | #define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */ |
---|
| 1492 | #define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */ |
---|
| 1493 | #define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */ |
---|
| 1494 | #define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */ |
---|
| 1495 | #define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */ |
---|
| 1496 | |
---|
| 1497 | /* CAN_RML1 Masks */ |
---|
| 1498 | #define RML0 0x0001 /* RX Message Lost In Mailbox 0 */ |
---|
| 1499 | #define RML1 0x0002 /* RX Message Lost In Mailbox 1 */ |
---|
| 1500 | #define RML2 0x0004 /* RX Message Lost In Mailbox 2 */ |
---|
| 1501 | #define RML3 0x0008 /* RX Message Lost In Mailbox 3 */ |
---|
| 1502 | #define RML4 0x0010 /* RX Message Lost In Mailbox 4 */ |
---|
| 1503 | #define RML5 0x0020 /* RX Message Lost In Mailbox 5 */ |
---|
| 1504 | #define RML6 0x0040 /* RX Message Lost In Mailbox 6 */ |
---|
| 1505 | #define RML7 0x0080 /* RX Message Lost In Mailbox 7 */ |
---|
| 1506 | #define RML8 0x0100 /* RX Message Lost In Mailbox 8 */ |
---|
| 1507 | #define RML9 0x0200 /* RX Message Lost In Mailbox 9 */ |
---|
| 1508 | #define RML10 0x0400 /* RX Message Lost In Mailbox 10 */ |
---|
| 1509 | #define RML11 0x0800 /* RX Message Lost In Mailbox 11 */ |
---|
| 1510 | #define RML12 0x1000 /* RX Message Lost In Mailbox 12 */ |
---|
| 1511 | #define RML13 0x2000 /* RX Message Lost In Mailbox 13 */ |
---|
| 1512 | #define RML14 0x4000 /* RX Message Lost In Mailbox 14 */ |
---|
| 1513 | #define RML15 0x8000 /* RX Message Lost In Mailbox 15 */ |
---|
| 1514 | |
---|
| 1515 | /* CAN_RML2 Masks */ |
---|
| 1516 | #define RML16 0x0001 /* RX Message Lost In Mailbox 16 */ |
---|
| 1517 | #define RML17 0x0002 /* RX Message Lost In Mailbox 17 */ |
---|
| 1518 | #define RML18 0x0004 /* RX Message Lost In Mailbox 18 */ |
---|
| 1519 | #define RML19 0x0008 /* RX Message Lost In Mailbox 19 */ |
---|
| 1520 | #define RML20 0x0010 /* RX Message Lost In Mailbox 20 */ |
---|
| 1521 | #define RML21 0x0020 /* RX Message Lost In Mailbox 21 */ |
---|
| 1522 | #define RML22 0x0040 /* RX Message Lost In Mailbox 22 */ |
---|
| 1523 | #define RML23 0x0080 /* RX Message Lost In Mailbox 23 */ |
---|
| 1524 | #define RML24 0x0100 /* RX Message Lost In Mailbox 24 */ |
---|
| 1525 | #define RML25 0x0200 /* RX Message Lost In Mailbox 25 */ |
---|
| 1526 | #define RML26 0x0400 /* RX Message Lost In Mailbox 26 */ |
---|
| 1527 | #define RML27 0x0800 /* RX Message Lost In Mailbox 27 */ |
---|
| 1528 | #define RML28 0x1000 /* RX Message Lost In Mailbox 28 */ |
---|
| 1529 | #define RML29 0x2000 /* RX Message Lost In Mailbox 29 */ |
---|
| 1530 | #define RML30 0x4000 /* RX Message Lost In Mailbox 30 */ |
---|
| 1531 | #define RML31 0x8000 /* RX Message Lost In Mailbox 31 */ |
---|
| 1532 | |
---|
| 1533 | /* CAN_OPSS1 Masks */ |
---|
| 1534 | #define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */ |
---|
| 1535 | #define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */ |
---|
| 1536 | #define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */ |
---|
| 1537 | #define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */ |
---|
| 1538 | #define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */ |
---|
| 1539 | #define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */ |
---|
| 1540 | #define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */ |
---|
| 1541 | #define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */ |
---|
| 1542 | #define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */ |
---|
| 1543 | #define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */ |
---|
| 1544 | #define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */ |
---|
| 1545 | #define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */ |
---|
| 1546 | #define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */ |
---|
| 1547 | #define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */ |
---|
| 1548 | #define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */ |
---|
| 1549 | #define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */ |
---|
| 1550 | |
---|
| 1551 | /* CAN_OPSS2 Masks */ |
---|
| 1552 | #define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */ |
---|
| 1553 | #define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */ |
---|
| 1554 | #define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */ |
---|
| 1555 | #define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */ |
---|
| 1556 | #define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */ |
---|
| 1557 | #define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */ |
---|
| 1558 | #define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */ |
---|
| 1559 | #define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */ |
---|
| 1560 | #define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */ |
---|
| 1561 | #define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */ |
---|
| 1562 | #define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */ |
---|
| 1563 | #define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */ |
---|
| 1564 | #define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */ |
---|
| 1565 | #define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */ |
---|
| 1566 | #define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */ |
---|
| 1567 | #define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */ |
---|
| 1568 | |
---|
| 1569 | /* CAN_TRR1 Masks */ |
---|
| 1570 | #define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */ |
---|
| 1571 | #define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */ |
---|
| 1572 | #define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */ |
---|
| 1573 | #define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */ |
---|
| 1574 | #define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */ |
---|
| 1575 | #define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */ |
---|
| 1576 | #define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */ |
---|
| 1577 | #define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */ |
---|
| 1578 | #define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */ |
---|
| 1579 | #define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */ |
---|
| 1580 | #define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */ |
---|
| 1581 | #define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */ |
---|
| 1582 | #define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */ |
---|
| 1583 | #define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */ |
---|
| 1584 | #define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */ |
---|
| 1585 | #define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */ |
---|
| 1586 | |
---|
| 1587 | /* CAN_TRR2 Masks */ |
---|
| 1588 | #define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */ |
---|
| 1589 | #define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */ |
---|
| 1590 | #define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */ |
---|
| 1591 | #define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */ |
---|
| 1592 | #define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */ |
---|
| 1593 | #define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */ |
---|
| 1594 | #define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */ |
---|
| 1595 | #define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */ |
---|
| 1596 | #define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */ |
---|
| 1597 | #define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */ |
---|
| 1598 | #define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */ |
---|
| 1599 | #define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */ |
---|
| 1600 | #define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */ |
---|
| 1601 | #define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */ |
---|
| 1602 | #define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */ |
---|
| 1603 | #define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */ |
---|
| 1604 | |
---|
| 1605 | /* CAN_TRS1 Masks */ |
---|
| 1606 | #define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */ |
---|
| 1607 | #define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */ |
---|
| 1608 | #define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */ |
---|
| 1609 | #define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */ |
---|
| 1610 | #define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */ |
---|
| 1611 | #define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */ |
---|
| 1612 | #define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */ |
---|
| 1613 | #define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */ |
---|
| 1614 | #define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */ |
---|
| 1615 | #define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */ |
---|
| 1616 | #define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */ |
---|
| 1617 | #define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */ |
---|
| 1618 | #define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */ |
---|
| 1619 | #define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */ |
---|
| 1620 | #define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */ |
---|
| 1621 | #define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */ |
---|
| 1622 | |
---|
| 1623 | /* CAN_TRS2 Masks */ |
---|
| 1624 | #define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */ |
---|
| 1625 | #define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */ |
---|
| 1626 | #define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */ |
---|
| 1627 | #define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */ |
---|
| 1628 | #define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */ |
---|
| 1629 | #define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */ |
---|
| 1630 | #define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */ |
---|
| 1631 | #define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */ |
---|
| 1632 | #define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */ |
---|
| 1633 | #define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */ |
---|
| 1634 | #define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */ |
---|
| 1635 | #define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */ |
---|
| 1636 | #define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */ |
---|
| 1637 | #define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */ |
---|
| 1638 | #define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */ |
---|
| 1639 | #define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */ |
---|
| 1640 | |
---|
| 1641 | /* CAN_AA1 Masks */ |
---|
| 1642 | #define AA0 0x0001 /* Aborted Message In Mailbox 0 */ |
---|
| 1643 | #define AA1 0x0002 /* Aborted Message In Mailbox 1 */ |
---|
| 1644 | #define AA2 0x0004 /* Aborted Message In Mailbox 2 */ |
---|
| 1645 | #define AA3 0x0008 /* Aborted Message In Mailbox 3 */ |
---|
| 1646 | #define AA4 0x0010 /* Aborted Message In Mailbox 4 */ |
---|
| 1647 | #define AA5 0x0020 /* Aborted Message In Mailbox 5 */ |
---|
| 1648 | #define AA6 0x0040 /* Aborted Message In Mailbox 6 */ |
---|
| 1649 | #define AA7 0x0080 /* Aborted Message In Mailbox 7 */ |
---|
| 1650 | #define AA8 0x0100 /* Aborted Message In Mailbox 8 */ |
---|
| 1651 | #define AA9 0x0200 /* Aborted Message In Mailbox 9 */ |
---|
| 1652 | #define AA10 0x0400 /* Aborted Message In Mailbox 10 */ |
---|
| 1653 | #define AA11 0x0800 /* Aborted Message In Mailbox 11 */ |
---|
| 1654 | #define AA12 0x1000 /* Aborted Message In Mailbox 12 */ |
---|
| 1655 | #define AA13 0x2000 /* Aborted Message In Mailbox 13 */ |
---|
| 1656 | #define AA14 0x4000 /* Aborted Message In Mailbox 14 */ |
---|
| 1657 | #define AA15 0x8000 /* Aborted Message In Mailbox 15 */ |
---|
| 1658 | |
---|
| 1659 | /* CAN_AA2 Masks */ |
---|
| 1660 | #define AA16 0x0001 /* Aborted Message In Mailbox 16 */ |
---|
| 1661 | #define AA17 0x0002 /* Aborted Message In Mailbox 17 */ |
---|
| 1662 | #define AA18 0x0004 /* Aborted Message In Mailbox 18 */ |
---|
| 1663 | #define AA19 0x0008 /* Aborted Message In Mailbox 19 */ |
---|
| 1664 | #define AA20 0x0010 /* Aborted Message In Mailbox 20 */ |
---|
| 1665 | #define AA21 0x0020 /* Aborted Message In Mailbox 21 */ |
---|
| 1666 | #define AA22 0x0040 /* Aborted Message In Mailbox 22 */ |
---|
| 1667 | #define AA23 0x0080 /* Aborted Message In Mailbox 23 */ |
---|
| 1668 | #define AA24 0x0100 /* Aborted Message In Mailbox 24 */ |
---|
| 1669 | #define AA25 0x0200 /* Aborted Message In Mailbox 25 */ |
---|
| 1670 | #define AA26 0x0400 /* Aborted Message In Mailbox 26 */ |
---|
| 1671 | #define AA27 0x0800 /* Aborted Message In Mailbox 27 */ |
---|
| 1672 | #define AA28 0x1000 /* Aborted Message In Mailbox 28 */ |
---|
| 1673 | #define AA29 0x2000 /* Aborted Message In Mailbox 29 */ |
---|
| 1674 | #define AA30 0x4000 /* Aborted Message In Mailbox 30 */ |
---|
| 1675 | #define AA31 0x8000 /* Aborted Message In Mailbox 31 */ |
---|
| 1676 | |
---|
| 1677 | /* CAN_TA1 Masks */ |
---|
| 1678 | #define TA0 0x0001 /* Transmit Successful From Mailbox 0 */ |
---|
| 1679 | #define TA1 0x0002 /* Transmit Successful From Mailbox 1 */ |
---|
| 1680 | #define TA2 0x0004 /* Transmit Successful From Mailbox 2 */ |
---|
| 1681 | #define TA3 0x0008 /* Transmit Successful From Mailbox 3 */ |
---|
| 1682 | #define TA4 0x0010 /* Transmit Successful From Mailbox 4 */ |
---|
| 1683 | #define TA5 0x0020 /* Transmit Successful From Mailbox 5 */ |
---|
| 1684 | #define TA6 0x0040 /* Transmit Successful From Mailbox 6 */ |
---|
| 1685 | #define TA7 0x0080 /* Transmit Successful From Mailbox 7 */ |
---|
| 1686 | #define TA8 0x0100 /* Transmit Successful From Mailbox 8 */ |
---|
| 1687 | #define TA9 0x0200 /* Transmit Successful From Mailbox 9 */ |
---|
| 1688 | #define TA10 0x0400 /* Transmit Successful From Mailbox 10 */ |
---|
| 1689 | #define TA11 0x0800 /* Transmit Successful From Mailbox 11 */ |
---|
| 1690 | #define TA12 0x1000 /* Transmit Successful From Mailbox 12 */ |
---|
| 1691 | #define TA13 0x2000 /* Transmit Successful From Mailbox 13 */ |
---|
| 1692 | #define TA14 0x4000 /* Transmit Successful From Mailbox 14 */ |
---|
| 1693 | #define TA15 0x8000 /* Transmit Successful From Mailbox 15 */ |
---|
| 1694 | |
---|
| 1695 | /* CAN_TA2 Masks */ |
---|
| 1696 | #define TA16 0x0001 /* Transmit Successful From Mailbox 16 */ |
---|
| 1697 | #define TA17 0x0002 /* Transmit Successful From Mailbox 17 */ |
---|
| 1698 | #define TA18 0x0004 /* Transmit Successful From Mailbox 18 */ |
---|
| 1699 | #define TA19 0x0008 /* Transmit Successful From Mailbox 19 */ |
---|
| 1700 | #define TA20 0x0010 /* Transmit Successful From Mailbox 20 */ |
---|
| 1701 | #define TA21 0x0020 /* Transmit Successful From Mailbox 21 */ |
---|
| 1702 | #define TA22 0x0040 /* Transmit Successful From Mailbox 22 */ |
---|
| 1703 | #define TA23 0x0080 /* Transmit Successful From Mailbox 23 */ |
---|
| 1704 | #define TA24 0x0100 /* Transmit Successful From Mailbox 24 */ |
---|
| 1705 | #define TA25 0x0200 /* Transmit Successful From Mailbox 25 */ |
---|
| 1706 | #define TA26 0x0400 /* Transmit Successful From Mailbox 26 */ |
---|
| 1707 | #define TA27 0x0800 /* Transmit Successful From Mailbox 27 */ |
---|
| 1708 | #define TA28 0x1000 /* Transmit Successful From Mailbox 28 */ |
---|
| 1709 | #define TA29 0x2000 /* Transmit Successful From Mailbox 29 */ |
---|
| 1710 | #define TA30 0x4000 /* Transmit Successful From Mailbox 30 */ |
---|
| 1711 | #define TA31 0x8000 /* Transmit Successful From Mailbox 31 */ |
---|
| 1712 | |
---|
| 1713 | /* CAN_MBTD Masks */ |
---|
| 1714 | #define TDPTR 0x001F /* Mailbox To Temporarily Disable */ |
---|
| 1715 | #define TDA 0x0040 /* Temporary Disable Acknowledge */ |
---|
| 1716 | #define TDR 0x0080 /* Temporary Disable Request */ |
---|
| 1717 | |
---|
| 1718 | /* CAN_RFH1 Masks */ |
---|
| 1719 | #define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */ |
---|
| 1720 | #define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */ |
---|
| 1721 | #define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */ |
---|
| 1722 | #define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */ |
---|
| 1723 | #define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */ |
---|
| 1724 | #define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */ |
---|
| 1725 | #define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */ |
---|
| 1726 | #define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */ |
---|
| 1727 | #define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */ |
---|
| 1728 | #define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */ |
---|
| 1729 | #define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */ |
---|
| 1730 | #define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */ |
---|
| 1731 | #define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */ |
---|
| 1732 | #define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */ |
---|
| 1733 | #define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */ |
---|
| 1734 | #define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */ |
---|
| 1735 | |
---|
| 1736 | /* CAN_RFH2 Masks */ |
---|
| 1737 | #define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */ |
---|
| 1738 | #define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */ |
---|
| 1739 | #define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */ |
---|
| 1740 | #define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */ |
---|
| 1741 | #define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */ |
---|
| 1742 | #define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */ |
---|
| 1743 | #define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */ |
---|
| 1744 | #define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */ |
---|
| 1745 | #define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */ |
---|
| 1746 | #define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */ |
---|
| 1747 | #define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */ |
---|
| 1748 | #define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */ |
---|
| 1749 | #define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */ |
---|
| 1750 | #define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */ |
---|
| 1751 | #define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */ |
---|
| 1752 | #define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */ |
---|
| 1753 | |
---|
| 1754 | /* CAN_MBTIF1 Masks */ |
---|
| 1755 | #define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */ |
---|
| 1756 | #define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */ |
---|
| 1757 | #define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */ |
---|
| 1758 | #define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */ |
---|
| 1759 | #define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */ |
---|
| 1760 | #define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */ |
---|
| 1761 | #define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */ |
---|
| 1762 | #define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */ |
---|
| 1763 | #define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */ |
---|
| 1764 | #define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */ |
---|
| 1765 | #define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */ |
---|
| 1766 | #define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */ |
---|
| 1767 | #define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */ |
---|
| 1768 | #define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */ |
---|
| 1769 | #define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */ |
---|
| 1770 | #define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */ |
---|
| 1771 | |
---|
| 1772 | /* CAN_MBTIF2 Masks */ |
---|
| 1773 | #define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */ |
---|
| 1774 | #define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */ |
---|
| 1775 | #define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */ |
---|
| 1776 | #define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */ |
---|
| 1777 | #define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */ |
---|
| 1778 | #define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */ |
---|
| 1779 | #define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */ |
---|
| 1780 | #define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */ |
---|
| 1781 | #define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */ |
---|
| 1782 | #define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */ |
---|
| 1783 | #define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */ |
---|
| 1784 | #define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */ |
---|
| 1785 | #define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */ |
---|
| 1786 | #define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */ |
---|
| 1787 | #define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */ |
---|
| 1788 | #define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */ |
---|
| 1789 | |
---|
| 1790 | /* CAN_MBRIF1 Masks */ |
---|
| 1791 | #define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */ |
---|
| 1792 | #define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */ |
---|
| 1793 | #define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */ |
---|
| 1794 | #define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */ |
---|
| 1795 | #define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */ |
---|
| 1796 | #define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */ |
---|
| 1797 | #define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */ |
---|
| 1798 | #define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */ |
---|
| 1799 | #define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */ |
---|
| 1800 | #define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */ |
---|
| 1801 | #define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */ |
---|
| 1802 | #define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */ |
---|
| 1803 | #define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */ |
---|
| 1804 | #define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */ |
---|
| 1805 | #define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */ |
---|
| 1806 | #define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */ |
---|
| 1807 | |
---|
| 1808 | /* CAN_MBRIF2 Masks */ |
---|
| 1809 | #define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */ |
---|
| 1810 | #define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */ |
---|
| 1811 | #define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */ |
---|
| 1812 | #define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */ |
---|
| 1813 | #define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */ |
---|
| 1814 | #define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */ |
---|
| 1815 | #define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */ |
---|
| 1816 | #define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */ |
---|
| 1817 | #define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */ |
---|
| 1818 | #define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */ |
---|
| 1819 | #define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */ |
---|
| 1820 | #define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */ |
---|
| 1821 | #define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */ |
---|
| 1822 | #define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */ |
---|
| 1823 | #define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */ |
---|
| 1824 | #define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */ |
---|
| 1825 | |
---|
| 1826 | /* CAN_MBIM1 Masks */ |
---|
| 1827 | #define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */ |
---|
| 1828 | #define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */ |
---|
| 1829 | #define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */ |
---|
| 1830 | #define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */ |
---|
| 1831 | #define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */ |
---|
| 1832 | #define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */ |
---|
| 1833 | #define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */ |
---|
| 1834 | #define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */ |
---|
| 1835 | #define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */ |
---|
| 1836 | #define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */ |
---|
| 1837 | #define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */ |
---|
| 1838 | #define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */ |
---|
| 1839 | #define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */ |
---|
| 1840 | #define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */ |
---|
| 1841 | #define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */ |
---|
| 1842 | #define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */ |
---|
| 1843 | |
---|
| 1844 | /* CAN_MBIM2 Masks */ |
---|
| 1845 | #define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */ |
---|
| 1846 | #define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */ |
---|
| 1847 | #define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */ |
---|
| 1848 | #define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */ |
---|
| 1849 | #define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */ |
---|
| 1850 | #define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */ |
---|
| 1851 | #define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */ |
---|
| 1852 | #define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */ |
---|
| 1853 | #define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */ |
---|
| 1854 | #define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */ |
---|
| 1855 | #define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */ |
---|
| 1856 | #define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */ |
---|
| 1857 | #define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */ |
---|
| 1858 | #define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */ |
---|
| 1859 | #define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */ |
---|
| 1860 | #define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */ |
---|
| 1861 | |
---|
| 1862 | /* CAN_GIM Masks */ |
---|
| 1863 | #define EWTIM 0x0001 /* Enable TX Error Count Interrupt */ |
---|
| 1864 | #define EWRIM 0x0002 /* Enable RX Error Count Interrupt */ |
---|
| 1865 | #define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */ |
---|
| 1866 | #define BOIM 0x0008 /* Enable Bus Off Interrupt */ |
---|
| 1867 | #define WUIM 0x0010 /* Enable Wake-Up Interrupt */ |
---|
| 1868 | #define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */ |
---|
| 1869 | #define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */ |
---|
| 1870 | #define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */ |
---|
| 1871 | #define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */ |
---|
| 1872 | #define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */ |
---|
| 1873 | #define ADIM 0x0400 /* Enable Access Denied Interrupt */ |
---|
| 1874 | |
---|
| 1875 | /* CAN_GIS Masks */ |
---|
| 1876 | #define EWTIS 0x0001 /* TX Error Count IRQ Status */ |
---|
| 1877 | #define EWRIS 0x0002 /* RX Error Count IRQ Status */ |
---|
| 1878 | #define EPIS 0x0004 /* Error-Passive Mode IRQ Status */ |
---|
| 1879 | #define BOIS 0x0008 /* Bus Off IRQ Status */ |
---|
| 1880 | #define WUIS 0x0010 /* Wake-Up IRQ Status */ |
---|
| 1881 | #define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */ |
---|
| 1882 | #define AAIS 0x0040 /* Abort Acknowledge IRQ Status */ |
---|
| 1883 | #define RMLIS 0x0080 /* RX Message Lost IRQ Status */ |
---|
| 1884 | #define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */ |
---|
| 1885 | #define EXTIS 0x0200 /* External Trigger Output IRQ Status */ |
---|
| 1886 | #define ADIS 0x0400 /* Access Denied IRQ Status */ |
---|
| 1887 | |
---|
| 1888 | /* CAN_GIF Masks */ |
---|
| 1889 | #define EWTIF 0x0001 /* TX Error Count IRQ Flag */ |
---|
| 1890 | #define EWRIF 0x0002 /* RX Error Count IRQ Flag */ |
---|
| 1891 | #define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */ |
---|
| 1892 | #define BOIF 0x0008 /* Bus Off IRQ Flag */ |
---|
| 1893 | #define WUIF 0x0010 /* Wake-Up IRQ Flag */ |
---|
| 1894 | #define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */ |
---|
| 1895 | #define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */ |
---|
| 1896 | #define RMLIF 0x0080 /* RX Message Lost IRQ Flag */ |
---|
| 1897 | #define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */ |
---|
| 1898 | #define EXTIF 0x0200 /* External Trigger Output IRQ Flag */ |
---|
| 1899 | #define ADIF 0x0400 /* Access Denied IRQ Flag */ |
---|
| 1900 | |
---|
| 1901 | /* CAN_UCCNF Masks */ |
---|
| 1902 | #define UCCNF 0x000F /* Universal Counter Mode */ |
---|
| 1903 | #define UC_STAMP 0x0001 /* Timestamp Mode */ |
---|
| 1904 | #define UC_WDOG 0x0002 /* Watchdog Mode */ |
---|
| 1905 | #define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */ |
---|
| 1906 | #define UC_ERROR 0x0006 /* CAN Error Frame Count */ |
---|
| 1907 | #define UC_OVER 0x0007 /* CAN Overload Frame Count */ |
---|
| 1908 | #define UC_LOST 0x0008 /* Arbitration Lost During TX Count */ |
---|
| 1909 | #define UC_AA 0x0009 /* TX Abort Count */ |
---|
| 1910 | #define UC_TA 0x000A /* TX Successful Count */ |
---|
| 1911 | #define UC_REJECT 0x000B /* RX Message Rejected Count */ |
---|
| 1912 | #define UC_RML 0x000C /* RX Message Lost Count */ |
---|
| 1913 | #define UC_RX 0x000D /* Total Successful RX Messages Count */ |
---|
| 1914 | #define UC_RMP 0x000E /* Successful RX W/Matching ID Count */ |
---|
| 1915 | #define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */ |
---|
| 1916 | #define UCRC 0x0020 /* Universal Counter Reload/Clear */ |
---|
| 1917 | #define UCCT 0x0040 /* Universal Counter CAN Trigger */ |
---|
| 1918 | #define UCE 0x0080 /* Universal Counter Enable */ |
---|
| 1919 | |
---|
| 1920 | /* CAN_ESR Masks */ |
---|
| 1921 | #define ACKE 0x0004 /* Acknowledge Error */ |
---|
| 1922 | #define SER 0x0008 /* Stuff Error */ |
---|
| 1923 | #define CRCE 0x0010 /* CRC Error */ |
---|
| 1924 | #define SA0 0x0020 /* Stuck At Dominant Error */ |
---|
| 1925 | #define BEF 0x0040 /* Bit Error Flag */ |
---|
| 1926 | #define FER 0x0080 /* Form Error Flag */ |
---|
| 1927 | |
---|
| 1928 | /* CAN_EWR Masks */ |
---|
| 1929 | #define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */ |
---|
| 1930 | #define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */ |
---|
| 1931 | |
---|
| 1932 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ |
---|
| 1933 | #define CAN_CNF CAN_DEBUG |
---|
| 1934 | #define TWI0_PRESCALE TWI0_CONTROL |
---|
| 1935 | #define TWI0_INT_SRC TWI0_INT_STAT |
---|
| 1936 | #define TWI0_INT_ENABLE TWI0_INT_MASK |
---|
| 1937 | #define TWI1_PRESCALE TWI1_CONTROL |
---|
| 1938 | #define TWI1_INT_SRC TWI1_INT_STAT |
---|
| 1939 | #define TWI1_INT_ENABLE TWI1_INT_MASK |
---|
| 1940 | #define TOVL_ERR0 TOVF_ERR0 |
---|
| 1941 | #define TOVL_ERR1 TOVF_ERR1 |
---|
| 1942 | #define TOVL_ERR2 TOVF_ERR2 |
---|
| 1943 | |
---|
| 1944 | #ifdef _MISRA_RULES |
---|
| 1945 | #pragma diag(pop) |
---|
| 1946 | #endif /* _MISRA_RULES */ |
---|
| 1947 | |
---|
| 1948 | #endif /* _DEF_BF538_H */ |
---|