Context Navigation

← Previous Revision
Latest Revision
Next Revision →
Blame
Revision Log

defBF542.h @ 615

Last change on this file since 615 was 444, checked in by satin@…, 7 years ago
add newlib,libalmos-mkh, restructure shared_syscalls.h and mini-libc
File size: 69.6 KB

Line
1	/*
2	* The authors hereby grant permission to use, copy, modify, distribute,
3	* and license this software and its documentation for any purpose, provided
4	* that existing copyright notices are retained in all copies and that this
5	* notice is included verbatim in any distributions. No written agreement,
6	* license, or royalty fee is required for any of the authorized uses.
7	* Modifications to this software may be copyrighted by their authors
8	* and need not follow the licensing terms described here, provided that
9	* the new terms are clearly indicated on the first page of each file where
10	* they apply.
11	*/
12
13	/*
14	** defBF542.h
15	**
16	** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
17	**
18	************************************************************************************
19	**
20	** This include file contains a list of macro "defines" to enable the programmer
21	** to use symbolic names for register-access and bit-manipulation.
22	**
23	**/
24	#ifndef _DEF_BF542_H
25	#define _DEF_BF542_H
26
27	/* Include all Core registers and bit definitions */
28	#include <def_LPBlackfin.h>
29
30	/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
31
32	/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
33	#include <defBF54x_base.h>
34
35	#ifdef _MISRA_RULES
36	#pragma diag(push)
37	#pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4")
38	#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ")
39	#endif /* _MISRA_RULES */
40
41	/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
42
43	/* ATAPI Registers */
44
45	#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
46	#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
47	#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
48	#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
49	#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
50	#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
51	#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
52	#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
53	#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
54	#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
55	#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
56	#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
57	#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
58	#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
59	#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
60	#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
61	#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
62	#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
63	#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
64	#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
65	#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
66	#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
67	#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
68	#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
69	#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
70
71	/* SDH Registers */
72
73	#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
74	#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
75	#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
76	#define SDH_COMMAND 0xffc0390c /* SDH Command */
77	#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
78	#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
79	#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
80	#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
81	#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
82	#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
83	#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
84	#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
85	#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
86	#define SDH_STATUS 0xffc03934 /* SDH Status */
87	#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
88	#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
89	#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
90	#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
91	#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
92	#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
93	#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
94	#define SDH_CFG 0xffc039c8 /* SDH Configuration */
95	#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
96	#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
97	#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
98	#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
99	#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
100	#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
101	#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
102	#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
103	#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
104
105	/* USB Control Registers */
106
107	#define USB_FADDR 0xffc03c00 /* Function address register */
108	#define USB_POWER 0xffc03c04 /* Power management register */
109	#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
110	#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
111	#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
112	#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
113	#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
114	#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
115	#define USB_FRAME 0xffc03c20 /* USB frame number */
116	#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
117	#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
118	#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
119	#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
120
121	/* USB Packet Control Registers */
122
123	#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
124	#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
125	#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
126	#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
127	#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
128	#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
129	#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
130	#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
131	#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
132	#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
133	#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
134	#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
135	#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
136
137	/* USB Endpoint FIFO Registers */
138
139	#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
140	#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
141	#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
142	#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
143	#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
144	#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
145	#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
146	#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
147
148	/* USB OTG Control Registers */
149
150	#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
151	#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
152	#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
153
154	/* USB Phy Control Registers */
155
156	#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
157	#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
158	#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
159	#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
160	#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
161
162	/* (APHY_CNTRL is for ADI usage only) */
163
164	#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
165
166	/* (APHY_CALIB is for ADI usage only) */
167
168	#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
169	#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
170
171	/* (PHY_TEST is for ADI usage only) */
172
173	#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
174	#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
175	#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
176
177	/* USB Endpoint 0 Control Registers */
178
179	#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
180	#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
181	#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
182	#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
183	#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
184	#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
185	#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
186	#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
187	#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
188
189	/* USB Endpoint 1 Control Registers */
190
191	#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
192	#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
193	#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
194	#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
195	#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
196	#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
197	#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
198	#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
199	#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
200	#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
201
202	/* USB Endpoint 2 Control Registers */
203
204	#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
205	#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
206	#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
207	#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
208	#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
209	#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
210	#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
211	#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
212	#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
213	#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
214
215	/* USB Endpoint 3 Control Registers */
216
217	#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
218	#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
219	#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
220	#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
221	#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
222	#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
223	#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
224	#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
225	#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
226	#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
227
228	/* USB Endpoint 4 Control Registers */
229
230	#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
231	#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
232	#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
233	#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
234	#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
235	#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
236	#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
237	#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
238	#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
239	#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
240
241	/* USB Endpoint 5 Control Registers */
242
243	#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
244	#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
245	#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
246	#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
247	#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
248	#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
249	#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
250	#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
251	#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
252	#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
253
254	/* USB Endpoint 6 Control Registers */
255
256	#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
257	#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
258	#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
259	#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
260	#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
261	#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
262	#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
263	#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
264	#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
265	#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
266
267	/* USB Endpoint 7 Control Registers */
268
269	#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
270	#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
271	#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
272	#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
273	#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
274	#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
275	#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
276	#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
277	#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
278	#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
279	#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
280	#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
281
282	/* USB Channel 0 Config Registers */
283
284	#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
285	#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
286	#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
287	#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
288	#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
289
290	/* USB Channel 1 Config Registers */
291
292	#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
293	#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
294	#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
295	#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
296	#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
297
298	/* USB Channel 2 Config Registers */
299
300	#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
301	#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
302	#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
303	#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
304	#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
305
306	/* USB Channel 3 Config Registers */
307
308	#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
309	#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
310	#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
311	#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
312	#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
313
314	/* USB Channel 4 Config Registers */
315
316	#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
317	#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
318	#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
319	#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
320	#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
321
322	/* USB Channel 5 Config Registers */
323
324	#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
325	#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
326	#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
327	#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
328	#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
329
330	/* USB Channel 6 Config Registers */
331
332	#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
333	#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
334	#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
335	#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
336	#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
337
338	/* USB Channel 7 Config Registers */
339
340	#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
341	#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
342	#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
343	#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
344	#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
345
346	/* Keypad Registers */
347
348	#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
349	#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
350	#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
351	#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
352	#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
353	#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
354
355
356	/* ********************************************************** */
357	/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
358	/* and MULTI BIT READ MACROS */
359	/* ********************************************************** */
360
361	/* Bit masks for KPAD_CTL */
362
363	#define KPAD_EN 0x1 /* Keypad Enable */
364	#define nKPAD_EN 0x0
365	#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
366	#define nKPAD_IRQMODE 0x0 /* Interrupt Disabled */
367	#define KPAD_IRQMODE_SK 0x2 /* Single key (single row, single column) press interrupt enable */
368	#define KPAD_IRQMODE_MK 0x4 /* Single key press multiple key press interrupt enable */
369
370	#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
371	#define KPAD_COLEN 0xe000 /* Column Enable Width */
372
373	#ifdef _MISRA_RULES
374	#define SET_KPAD_ROWEN(x) (((x)&0x7u)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
375	#define SET_KPAD_COLEN(x) (((x)&0x7u)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
376	#else
377	#define SET_KPAD_ROWEN(x) (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
378	#define SET_KPAD_COLEN(x) (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
379	#endif /* _MISRA_RULES */
380
381	/* Bit masks for KPAD_PRESCALE */
382
383	#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
384
385	#ifdef _MISRA_RULES
386	#define SET_KPAD_PRESCALE(x) ((x)&0x3Fu) /* KPAD_PRESCALE_VAL (Key Prescale) Key Prescale Value (5:0) */
387	#else
388	#define SET_KPAD_PRESCALE(x) ((x)&0x3F) /* KPAD_PRESCALE_VAL (Key Prescale) Key Prescale Value (5:0) */
389	#endif /* _MISRA_RULES */
390
391	/* Bit masks for KPAD_MSEL */
392
393	#define DBON_SCALE 0xff /* Debounce Scale Value */
394	#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
395
396	/* Bit masks for KPAD_ROWCOL */
397
398	#define KPAD_ROW 0xff /* Rows Pressed */
399	#define KPAD_COL 0xff00 /* Columns Pressed */
400
401	#ifdef _MISRA_RULES
402	#define SET_KPAD_DBON_SCALE(x) ((x)&0xFFu) /* DBON_SCALE (Debounce Scale) Debounce Delay Multiplier Select [7:0] */
403	#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFFu)<<8) /* COLDRV_SCALE (Column Driver Scale) Column Driver Period Multiplier Select [15:8] */
404	#else
405	#define SET_KPAD_DBON_SCALE(x) ((x)&0xFF) /* DBON_SCALE (Debounce Scale) Debounce Delay Multiplier Select [7:0] */
406	#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale) Column Driver Period Multiplier Select [15:8] */
407	#endif /* _MISRA_RULES */
408
409	/* Bit masks for KPAD_STAT */
410
411	#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
412	#define nKPAD_IRQ 0x0
413	#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
414	#define KPAD_PRESSED 0x8 /* Key press current status */
415	#define nKPAD_PRESSED 0x0
416	#define KPAD_NO_KEY 0x0 /* No Keypress Status*/
417	#define KPAD_SINGLE_KEY 0x2 /* Single Keypress Status */
418	#define KPAD_MKSROWCOL 0x4 /* Multiple Keypress in the same row or column Status */
419	#define KPAD_MKMROWCOL 0x6 /* Multiple Keypress in the same multiple rows and multiple columns Status */
420
421	/* Bit masks for KPAD_SOFTEVAL */
422
423	#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
424	#define nKPAD_SOFTEVAL_E 0x0
425
426	/* Bit masks for SDH_COMMAND */
427
428	#define CMD_IDX 0x3f /* Command Index */
429	#define CMD_RSP 0x40 /* Response */
430	#define nCMD_RSP 0x0
431	#define CMD_L_RSP 0x80 /* Long Response */
432	#define nCMD_L_RSP 0x0
433	#define CMD_INT_E 0x100 /* Command Interrupt */
434	#define nCMD_INT_E 0x0
435	#define CMD_PEND_E 0x200 /* Command Pending */
436	#define nCMD_PEND_E 0x0
437	#define CMD_E 0x400 /* Command Enable */
438	#define nCMD_E 0x0
439
440	/* Bit masks for SDH_PWR_CTL */
441
442	#define PWR_ON 0x3 /* Power On */
443	#if 0
444	#define TBD 0x3c /* TBD */
445	#endif
446	#define SD_CMD_OD 0x40 /* Open Drain Output */
447	#define nSD_CMD_OD 0x0
448	#define ROD_CTL 0x80 /* Rod Control */
449	#define nROD_CTL 0x0
450
451	/* Bit masks for SDH_CLK_CTL */
452
453	#define CLKDIV 0xff /* MC_CLK Divisor */
454	#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
455	#define nCLK_E 0x0
456	#define PWR_SV_E 0x200 /* Power Save Enable */
457	#define nPWR_SV_E 0x0
458	#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
459	#define nCLKDIV_BYPASS 0x0
460	#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
461	#define nWIDE_BUS 0x0
462
463	/* Bit masks for SDH_RESP_CMD */
464
465	#define RESP_CMD 0x3f /* Response Command */
466
467	/* Bit masks for SDH_DATA_CTL */
468
469	#define DTX_E 0x1 /* Data Transfer Enable */
470	#define nDTX_E 0x0
471	#define DTX_DIR 0x2 /* Data Transfer Direction */
472	#define nDTX_DIR 0x0
473	#define DTX_MODE 0x4 /* Data Transfer Mode */
474	#define nDTX_MODE 0x0
475	#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
476	#define nDTX_DMA_E 0x0
477	#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
478
479	/* Bit masks for SDH_STATUS */
480
481	#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
482	#define nCMD_CRC_FAIL 0x0
483	#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
484	#define nDAT_CRC_FAIL 0x0
485	#define CMD_TIMEOUT 0x4 /* CMD Time Out */
486	#define nCMD_TIMEOUT 0x0
487	#define DAT_TIMEOUT 0x8 /* Data Time Out */
488	#define nDAT_TIMEOUT 0x0
489	#define TX_UNDERRUN 0x10 /* Transmit Underrun */
490	#define nTX_UNDERRUN 0x0
491	#define RX_OVERRUN 0x20 /* Receive Overrun */
492	#define nRX_OVERRUN 0x0
493	#define CMD_RESP_END 0x40 /* CMD Response End */
494	#define nCMD_RESP_END 0x0
495	#define CMD_SENT 0x80 /* CMD Sent */
496	#define nCMD_SENT 0x0
497	#define DAT_END 0x100 /* Data End */
498	#define nDAT_END 0x0
499	#define START_BIT_ERR 0x200 /* Start Bit Error */
500	#define nSTART_BIT_ERR 0x0
501	#define DAT_BLK_END 0x400 /* Data Block End */
502	#define nDAT_BLK_END 0x0
503	#define CMD_ACT 0x800 /* CMD Active */
504	#define nCMD_ACT 0x0
505	#define TX_ACT 0x1000 /* Transmit Active */
506	#define nTX_ACT 0x0
507	#define RX_ACT 0x2000 /* Receive Active */
508	#define nRX_ACT 0x0
509	#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
510	#define nTX_FIFO_STAT 0x0
511	#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
512	#define nRX_FIFO_STAT 0x0
513	#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
514	#define nTX_FIFO_FULL 0x0
515	#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
516	#define nRX_FIFO_FULL 0x0
517	#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
518	#define nTX_FIFO_ZERO 0x0
519	#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
520	#define nRX_DAT_ZERO 0x0
521	#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
522	#define nTX_DAT_RDY 0x0
523	#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
524	#define nRX_FIFO_RDY 0x0
525
526	/* Bit masks for SDH_STATUS_CLR */
527
528	#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
529	#define nCMD_CRC_FAIL_STAT 0x0
530	#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
531	#define nDAT_CRC_FAIL_STAT 0x0
532	#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
533	#define nCMD_TIMEOUT_STAT 0x0
534	#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
535	#define nDAT_TIMEOUT_STAT 0x0
536	#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
537	#define nTX_UNDERRUN_STAT 0x0
538	#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
539	#define nRX_OVERRUN_STAT 0x0
540	#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
541	#define nCMD_RESP_END_STAT 0x0
542	#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
543	#define nCMD_SENT_STAT 0x0
544	#define DAT_END_STAT 0x100 /* Data End Status */
545	#define nDAT_END_STAT 0x0
546	#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
547	#define nSTART_BIT_ERR_STAT 0x0
548	#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
549	#define nDAT_BLK_END_STAT 0x0
550
551	/* Bit masks for SDH_MASK0 */
552
553	#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
554	#define nCMD_CRC_FAIL_MASK 0x0
555	#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
556	#define nDAT_CRC_FAIL_MASK 0x0
557	#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
558	#define nCMD_TIMEOUT_MASK 0x0
559	#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
560	#define nDAT_TIMEOUT_MASK 0x0
561	#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
562	#define nTX_UNDERRUN_MASK 0x0
563	#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
564	#define nRX_OVERRUN_MASK 0x0
565	#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
566	#define nCMD_RESP_END_MASK 0x0
567	#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
568	#define nCMD_SENT_MASK 0x0
569	#define DAT_END_MASK 0x100 /* Data End Mask */
570	#define nDAT_END_MASK 0x0
571	#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
572	#define nSTART_BIT_ERR_MASK 0x0
573	#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
574	#define nDAT_BLK_END_MASK 0x0
575	#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
576	#define nCMD_ACT_MASK 0x0
577	#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
578	#define nTX_ACT_MASK 0x0
579	#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
580	#define nRX_ACT_MASK 0x0
581	#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
582	#define nTX_FIFO_STAT_MASK 0x0
583	#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
584	#define nRX_FIFO_STAT_MASK 0x0
585	#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
586	#define nTX_FIFO_FULL_MASK 0x0
587	#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
588	#define nRX_FIFO_FULL_MASK 0x0
589	#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
590	#define nTX_FIFO_ZERO_MASK 0x0
591	#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
592	#define nRX_DAT_ZERO_MASK 0x0
593	#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
594	#define nTX_DAT_RDY_MASK 0x0
595	#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
596	#define nRX_FIFO_RDY_MASK 0x0
597
598	/* Bit masks for SDH_FIFO_CNT */
599
600	#define FIFO_COUNT 0x7fff /* FIFO Count */
601
602	/* Bit masks for SDH_E_STATUS */
603
604	#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
605	#define nSDIO_INT_DET 0x0
606	#define SD_CARD_DET 0x10 /* SD Card Detect */
607	#define nSD_CARD_DET 0x0
608
609	/* Bit masks for SDH_E_MASK */
610
611	#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
612	#define nSDIO_MSK 0x0
613	#define SCD_MSK 0x40 /* Mask Card Detect */
614	#define nSCD_MSK 0x0
615
616	/* Bit masks for SDH_CFG */
617
618	#define CLKS_EN 0x1 /* Clocks Enable */
619	#define nCLKS_EN 0x0
620	#define SD4E 0x4 /* SDIO 4-Bit Enable */
621	#define nSD4E 0x0
622	#define MWE 0x8 /* Moving Window Enable */
623	#define nMWE 0x0
624	#define SD_RST 0x10 /* SDMMC Reset */
625	#define nSD_RST 0x0
626	#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
627	#define nPUP_SDDAT 0x0
628	#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
629	#define nPUP_SDDAT3 0x0
630	#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
631	#define nPD_SDDAT3 0x0
632
633	/* Bit masks for SDH_RD_WAIT_EN */
634
635	#define RWR 0x1 /* Read Wait Request */
636	#define nRWR 0x0
637
638	/* Bit masks for ATAPI_CONTROL */
639
640	#define PIO_START 0x1 /* Start PIO/Reg Op */
641	#define nPIO_START 0x0
642	#define MULTI_START 0x2 /* Start Multi-DMA Op */
643	#define nMULTI_START 0x0
644	#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
645	#define nULTRA_START 0x0
646	#define XFER_DIR 0x8 /* Transfer Direction */
647	#define nXFER_DIR 0x0
648	#define IORDY_EN 0x10 /* IORDY Enable */
649	#define nIORDY_EN 0x0
650	#define FIFO_FLUSH 0x20 /* Flush FIFOs */
651	#define nFIFO_FLUSH 0x0
652	#define SOFT_RST 0x40 /* Soft Reset */
653	#define nSOFT_RST 0x0
654	#define DEV_RST 0x80 /* Device Reset */
655	#define nDEV_RST 0x0
656	#define TFRCNT_RST 0x100 /* Trans Count Reset */
657	#define nTFRCNT_RST 0x0
658	#define END_ON_TERM 0x200 /* End/Terminate Select */
659	#define nEND_ON_TERM 0x0
660	#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
661	#define nPIO_USE_DMA 0x0
662	#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
663
664	/* Bit masks for ATAPI_STATUS */
665
666	#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
667	#define nPIO_XFER_ON 0x0
668	#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
669	#define nMULTI_XFER_ON 0x0
670	#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
671	#define nULTRA_XFER_ON 0x0
672	#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
673
674	/* Bit masks for ATAPI_DEV_ADDR */
675
676	#define DEV_ADDR 0x1f /* Device Address */
677
678	/* Bit masks for ATAPI_INT_MASK */
679
680	#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
681	#define nATAPI_DEV_INT_MASK 0x0
682	#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
683	#define nPIO_DONE_MASK 0x0
684	#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
685	#define nMULTI_DONE_MASK 0x0
686	#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
687	#define nUDMAIN_DONE_MASK 0x0
688	#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
689	#define nUDMAOUT_DONE_MASK 0x0
690	#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
691	#define nHOST_TERM_XFER_MASK 0x0
692	#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
693	#define nMULTI_TERM_MASK 0x0
694	#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
695	#define nUDMAIN_TERM_MASK 0x0
696	#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
697	#define nUDMAOUT_TERM_MASK 0x0
698
699	/* Bit masks for ATAPI_INT_STATUS */
700
701	#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
702	#define nATAPI_DEV_INT 0x0
703	#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
704	#define nPIO_DONE_INT 0x0
705	#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
706	#define nMULTI_DONE_INT 0x0
707	#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
708	#define nUDMAIN_DONE_INT 0x0
709	#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
710	#define nUDMAOUT_DONE_INT 0x0
711	#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
712	#define nHOST_TERM_XFER_INT 0x0
713	#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
714	#define nMULTI_TERM_INT 0x0
715	#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
716	#define nUDMAIN_TERM_INT 0x0
717	#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
718	#define nUDMAOUT_TERM_INT 0x0
719
720	/* Bit masks for ATAPI_LINE_STATUS */
721
722	#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
723	#define nATAPI_INTR 0x0
724	#define ATAPI_DASP 0x2 /* Device dasp to host line status */
725	#define nATAPI_DASP 0x0
726	#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
727	#define nATAPI_CS0N 0x0
728	#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
729	#define nATAPI_CS1N 0x0
730	#define ATAPI_ADDR 0x70 /* ATAPI address line status */
731	#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
732	#define nATAPI_DMAREQ 0x0
733	#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
734	#define nATAPI_DMAACKN 0x0
735	#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
736	#define nATAPI_DIOWN 0x0
737	#define ATAPI_DIORN 0x400 /* ATAPI read line status */
738	#define nATAPI_DIORN 0x0
739	#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
740	#define nATAPI_IORDY 0x0
741
742	/* Bit masks for ATAPI_SM_STATE */
743
744	#define PIO_CSTATE 0xf /* PIO mode state machine current state */
745	#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
746	#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
747	#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
748
749	/* Bit masks for ATAPI_TERMINATE */
750
751	#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
752	#define nATAPI_HOST_TERM 0x0
753
754	/* Bit masks for ATAPI_REG_TIM_0 */
755
756	#define T2_REG 0xff /* End of cycle time for register access transfers */
757	#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
758
759	/* Bit masks for ATAPI_PIO_TIM_0 */
760
761	#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
762	#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
763	#define T4_REG 0xf000 /* DIOW data hold */
764
765	/* Bit masks for ATAPI_PIO_TIM_1 */
766
767	#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
768
769	/* Bit masks for ATAPI_MULTI_TIM_0 */
770
771	#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
772	#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
773
774	/* Bit masks for ATAPI_MULTI_TIM_1 */
775
776	#define TKW 0xff /* Selects DIOW negated pulsewidth */
777	#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
778
779	/* Bit masks for ATAPI_MULTI_TIM_2 */
780
781	#define TH 0xff /* Selects DIOW data hold */
782	#define TEOC 0xff00 /* Selects end of cycle for DMA */
783
784	/* Bit masks for ATAPI_ULTRA_TIM_0 */
785
786	#define TACK 0xff /* Selects setup and hold times for TACK */
787	#define TENV 0xff00 /* Selects envelope time */
788
789	/* Bit masks for ATAPI_ULTRA_TIM_1 */
790
791	#define TDVS 0xff /* Selects data valid setup time */
792	#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
793
794	/* Bit masks for ATAPI_ULTRA_TIM_2 */
795
796	#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
797	#define TMLI 0xff00 /* Selects interlock time */
798
799	/* Bit masks for ATAPI_ULTRA_TIM_3 */
800
801	#define TZAH 0xff /* Selects minimum delay required for output */
802	#define READY_PAUSE 0xff00 /* Selects ready to pause */
803
804	/* Bit masks for USB_FADDR */
805
806	#define FUNCTION_ADDRESS 0x7f /* Function address */
807
808	/* Bit masks for USB_POWER */
809
810	#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
811	#define nENABLE_SUSPENDM 0x0
812	#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
813	#define nSUSPEND_MODE 0x0
814	#define RESUME_MODE 0x4 /* DMA Mode */
815	#define nRESUME_MODE 0x0
816	#define RESET 0x8 /* Reset indicator */
817	#define nRESET 0x0
818	#define HS_MODE 0x10 /* High Speed mode indicator */
819	#define nHS_MODE 0x0
820	#define HS_ENABLE 0x20 /* high Speed Enable */
821	#define nHS_ENABLE 0x0
822	#define SOFT_CONN 0x40 /* Soft connect */
823	#define nSOFT_CONN 0x0
824	#define ISO_UPDATE 0x80 /* Isochronous update */
825	#define nISO_UPDATE 0x0
826
827	/* Bit masks for USB_INTRTX */
828
829	#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
830	#define nEP0_TX 0x0
831	#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
832	#define nEP1_TX 0x0
833	#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
834	#define nEP2_TX 0x0
835	#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
836	#define nEP3_TX 0x0
837	#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
838	#define nEP4_TX 0x0
839	#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
840	#define nEP5_TX 0x0
841	#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
842	#define nEP6_TX 0x0
843	#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
844	#define nEP7_TX 0x0
845
846	/* Bit masks for USB_INTRRX */
847
848	#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
849	#define nEP1_RX 0x0
850	#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
851	#define nEP2_RX 0x0
852	#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
853	#define nEP3_RX 0x0
854	#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
855	#define nEP4_RX 0x0
856	#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
857	#define nEP5_RX 0x0
858	#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
859	#define nEP6_RX 0x0
860	#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
861	#define nEP7_RX 0x0
862
863	/* Bit masks for USB_INTRTXE */
864
865	#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
866	#define nEP0_TX_E 0x0
867	#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
868	#define nEP1_TX_E 0x0
869	#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
870	#define nEP2_TX_E 0x0
871	#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
872	#define nEP3_TX_E 0x0
873	#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
874	#define nEP4_TX_E 0x0
875	#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
876	#define nEP5_TX_E 0x0
877	#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
878	#define nEP6_TX_E 0x0
879	#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
880	#define nEP7_TX_E 0x0
881
882	/* Bit masks for USB_INTRRXE */
883
884	#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
885	#define nEP1_RX_E 0x0
886	#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
887	#define nEP2_RX_E 0x0
888	#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
889	#define nEP3_RX_E 0x0
890	#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
891	#define nEP4_RX_E 0x0
892	#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
893	#define nEP5_RX_E 0x0
894	#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
895	#define nEP6_RX_E 0x0
896	#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
897	#define nEP7_RX_E 0x0
898
899	/* Bit masks for USB_INTRUSB */
900
901	#define SUSPEND_B 0x1 /* Suspend indicator */
902	#define nSUSPEND_B 0x0
903	#define RESUME_B 0x2 /* Resume indicator */
904	#define nRESUME_B 0x0
905	#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
906	#define nRESET_OR_BABLE_B 0x0
907	#define SOF_B 0x8 /* Start of frame */
908	#define nSOF_B 0x0
909	#define CONN_B 0x10 /* Connection indicator */
910	#define nCONN_B 0x0
911	#define DISCON_B 0x20 /* Disconnect indicator */
912	#define nDISCON_B 0x0
913	#define SESSION_REQ_B 0x40 /* Session Request */
914	#define nSESSION_REQ_B 0x0
915	#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
916	#define nVBUS_ERROR_B 0x0
917
918	/* Bit masks for USB_INTRUSBE */
919
920	#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
921	#define nSUSPEND_BE 0x0
922	#define RESUME_BE 0x2 /* Resume indicator int enable */
923	#define nRESUME_BE 0x0
924	#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
925	#define nRESET_OR_BABLE_BE 0x0
926	#define SOF_BE 0x8 /* Start of frame int enable */
927	#define nSOF_BE 0x0
928	#define CONN_BE 0x10 /* Connection indicator int enable */
929	#define nCONN_BE 0x0
930	#define DISCON_BE 0x20 /* Disconnect indicator int enable */
931	#define nDISCON_BE 0x0
932	#define SESSION_REQ_BE 0x40 /* Session Request int enable */
933	#define nSESSION_REQ_BE 0x0
934	#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
935	#define nVBUS_ERROR_BE 0x0
936
937	/* Bit masks for USB_FRAME */
938
939	#define FRAME_NUMBER 0x7ff /* Frame number */
940
941	/* Bit masks for USB_INDEX */
942
943	#define SELECTED_ENDPOINT 0xf /* selected endpoint */
944
945	/* Bit masks for USB_GLOBAL_CTL */
946
947	#define GLOBAL_ENA 0x1 /* enables USB module */
948	#define nGLOBAL_ENA 0x0
949	#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
950	#define nEP1_TX_ENA 0x0
951	#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
952	#define nEP2_TX_ENA 0x0
953	#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
954	#define nEP3_TX_ENA 0x0
955	#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
956	#define nEP4_TX_ENA 0x0
957	#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
958	#define nEP5_TX_ENA 0x0
959	#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
960	#define nEP6_TX_ENA 0x0
961	#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
962	#define nEP7_TX_ENA 0x0
963	#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
964	#define nEP1_RX_ENA 0x0
965	#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
966	#define nEP2_RX_ENA 0x0
967	#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
968	#define nEP3_RX_ENA 0x0
969	#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
970	#define nEP4_RX_ENA 0x0
971	#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
972	#define nEP5_RX_ENA 0x0
973	#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
974	#define nEP6_RX_ENA 0x0
975	#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
976	#define nEP7_RX_ENA 0x0
977
978	/* Bit masks for USB_OTG_DEV_CTL */
979
980	#define SESSION 0x1 /* session indicator */
981	#define nSESSION 0x0
982	#define HOST_REQ 0x2 /* Host negotiation request */
983	#define nHOST_REQ 0x0
984	#define HOST_MODE 0x4 /* indicates USBDRC is a host */
985	#define nHOST_MODE 0x0
986	#define VBUS0 0x8 /* Vbus level indicator[0] */
987	#define nVBUS0 0x0
988	#define VBUS1 0x10 /* Vbus level indicator[1] */
989	#define nVBUS1 0x0
990	#define LSDEV 0x20 /* Low-speed indicator */
991	#define nLSDEV 0x0
992	#define FSDEV 0x40 /* Full or High-speed indicator */
993	#define nFSDEV 0x0
994	#define B_DEVICE 0x80 /* A' or 'B' device indicator */
995	#define nB_DEVICE 0x0
996
997	/* Bit masks for USB_OTG_VBUS_IRQ */
998
999	#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
1000	#define nDRIVE_VBUS_ON 0x0
1001	#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
1002	#define nDRIVE_VBUS_OFF 0x0
1003	#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
1004	#define nCHRG_VBUS_START 0x0
1005	#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
1006	#define nCHRG_VBUS_END 0x0
1007	#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
1008	#define nDISCHRG_VBUS_START 0x0
1009	#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
1010	#define nDISCHRG_VBUS_END 0x0
1011
1012	/* Bit masks for USB_OTG_VBUS_MASK */
1013
1014	#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
1015	#define nDRIVE_VBUS_ON_ENA 0x0
1016	#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
1017	#define nDRIVE_VBUS_OFF_ENA 0x0
1018	#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
1019	#define nCHRG_VBUS_START_ENA 0x0
1020	#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
1021	#define nCHRG_VBUS_END_ENA 0x0
1022	#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
1023	#define nDISCHRG_VBUS_START_ENA 0x0
1024	#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
1025	#define nDISCHRG_VBUS_END_ENA 0x0
1026
1027	/* Bit masks for USB_CSR0 */
1028
1029	#define RXPKTRDY 0x1 /* data packet receive indicator */
1030	#define nRXPKTRDY 0x0
1031	#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1032	#define nTXPKTRDY 0x0
1033	#define STALL_SENT 0x4 /* STALL handshake sent */
1034	#define nSTALL_SENT 0x0
1035	#define DATAEND 0x8 /* Data end indicator */
1036	#define nDATAEND 0x0
1037	#define SETUPEND 0x10 /* Setup end */
1038	#define nSETUPEND 0x0
1039	#define SENDSTALL 0x20 /* Send STALL handshake */
1040	#define nSENDSTALL 0x0
1041	#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1042	#define nSERVICED_RXPKTRDY 0x0
1043	#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1044	#define nSERVICED_SETUPEND 0x0
1045	#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1046	#define nFLUSHFIFO 0x0
1047	#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1048	#define nSTALL_RECEIVED_H 0x0
1049	#define SETUPPKT_H 0x8 /* send Setup token host mode */
1050	#define nSETUPPKT_H 0x0
1051	#define ERROR_H 0x10 /* timeout error indicator host mode */
1052	#define nERROR_H 0x0
1053	#define REQPKT_H 0x20 /* Request an IN transaction host mode */
1054	#define nREQPKT_H 0x0
1055	#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1056	#define nSTATUSPKT_H 0x0
1057	#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1058	#define nNAK_TIMEOUT_H 0x0
1059
1060	/* Bit masks for USB_COUNT0 */
1061
1062	#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
1063
1064	/* Bit masks for USB_NAKLIMIT0 */
1065
1066	#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
1067
1068	/* Bit masks for USB_TX_MAX_PACKET */
1069
1070	#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
1071
1072	/* Bit masks for USB_RX_MAX_PACKET */
1073
1074	#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
1075
1076	/* Bit masks for USB_TXCSR */
1077
1078	#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1079	#define nTXPKTRDY_T 0x0
1080	#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1081	#define nFIFO_NOT_EMPTY_T 0x0
1082	#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1083	#define nUNDERRUN_T 0x0
1084	#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1085	#define nFLUSHFIFO_T 0x0
1086	#define STALL_SEND_T 0x10 /* issue a Stall handshake */
1087	#define nSTALL_SEND_T 0x0
1088	#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1089	#define nSTALL_SENT_T 0x0
1090	#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1091	#define nCLEAR_DATATOGGLE_T 0x0
1092	#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1093	#define nINCOMPTX_T 0x0
1094	#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1095	#define nDMAREQMODE_T 0x0
1096	#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1097	#define nFORCE_DATATOGGLE_T 0x0
1098	#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1099	#define nDMAREQ_ENA_T 0x0
1100	#define ISO_T 0x4000 /* enable Isochronous transfers */
1101	#define nISO_T 0x0
1102	#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1103	#define nAUTOSET_T 0x0
1104	#define ERROR_TH 0x4 /* error condition host mode */
1105	#define nERROR_TH 0x0
1106	#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1107	#define nSTALL_RECEIVED_TH 0x0
1108	#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1109	#define nNAK_TIMEOUT_TH 0x0
1110
1111	/* Bit masks for USB_TXCOUNT */
1112
1113	#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
1114
1115	/* Bit masks for USB_RXCSR */
1116
1117	#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1118	#define nRXPKTRDY_R 0x0
1119	#define FIFO_FULL_R 0x2 /* FIFO not empty */
1120	#define nFIFO_FULL_R 0x0
1121	#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1122	#define nOVERRUN_R 0x0
1123	#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1124	#define nDATAERROR_R 0x0
1125	#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1126	#define nFLUSHFIFO_R 0x0
1127	#define STALL_SEND_R 0x20 /* issue a Stall handshake */
1128	#define nSTALL_SEND_R 0x0
1129	#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1130	#define nSTALL_SENT_R 0x0
1131	#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1132	#define nCLEAR_DATATOGGLE_R 0x0
1133	#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1134	#define nINCOMPRX_R 0x0
1135	#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1136	#define nDMAREQMODE_R 0x0
1137	#define DISNYET_R 0x1000 /* disable Nyet handshakes */
1138	#define nDISNYET_R 0x0
1139	#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1140	#define nDMAREQ_ENA_R 0x0
1141	#define ISO_R 0x4000 /* enable Isochronous transfers */
1142	#define nISO_R 0x0
1143	#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1144	#define nAUTOCLEAR_R 0x0
1145	#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1146	#define nERROR_RH 0x0
1147	#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1148	#define nREQPKT_RH 0x0
1149	#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1150	#define nSTALL_RECEIVED_RH 0x0
1151	#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1152	#define nINCOMPRX_RH 0x0
1153	#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1154	#define nDMAREQMODE_RH 0x0
1155	#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1156	#define nAUTOREQ_RH 0x0
1157
1158	/* Bit masks for USB_RXCOUNT */
1159
1160	#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1161
1162	/* Bit masks for USB_TXTYPE */
1163
1164	#define TARGET_EP_NO_T 0xf /* EP number */
1165	#define PROTOCOL_T 0xc /* transfer type */
1166
1167	/* Bit masks for USB_TXINTERVAL */
1168
1169	#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1170
1171	/* Bit masks for USB_RXTYPE */
1172
1173	#define TARGET_EP_NO_R 0xf /* EP number */
1174	#define PROTOCOL_R 0xc /* transfer type */
1175
1176	/* Bit masks for USB_RXINTERVAL */
1177
1178	#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1179
1180	/* Bit masks for USB_DMA_INTERRUPT */
1181
1182	#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1183	#define nDMA0_INT 0x0
1184	#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1185	#define nDMA1_INT 0x0
1186	#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1187	#define nDMA2_INT 0x0
1188	#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1189	#define nDMA3_INT 0x0
1190	#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1191	#define nDMA4_INT 0x0
1192	#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1193	#define nDMA5_INT 0x0
1194	#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1195	#define nDMA6_INT 0x0
1196	#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1197	#define nDMA7_INT 0x0
1198
1199	/* Bit masks for USB_DMAxCONTROL */
1200
1201	#define DMA_ENA 0x1 /* DMA enable */
1202	#define nDMA_ENA 0x0
1203	#define DIRECTION 0x2 /* direction of DMA transfer */
1204	#define nDIRECTION 0x0
1205	#define MODE 0x4 /* DMA Bus error */
1206	#define nMODE 0x0
1207	#define INT_ENA 0x8 /* Interrupt enable */
1208	#define nINT_ENA 0x0
1209	#define EPNUM 0xf0 /* EP number */
1210	#define BUSERROR 0x100 /* DMA Bus error */
1211	#define nBUSERROR 0x0
1212
1213	/* Bit masks for USB_DMAxADDRHIGH */
1214
1215	#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1216
1217	/* Bit masks for USB_DMAxADDRLOW */
1218
1219	#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1220
1221	/* Bit masks for USB_DMAxCOUNTHIGH */
1222
1223	#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1224
1225	/* Bit masks for USB_DMAxCOUNTLOW */
1226
1227	#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1228
1229
1230	/* ******************************************* */
1231	/* MULTI BIT MACRO ENUMERATIONS */
1232	/* ******************************************* */
1233
1234	#ifdef _MISRA_RULES
1235	#pragma diag(pop)
1236	#endif /* _MISRA_RULES */
1237
1238	#endif /* _DEF_BF542_H */

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: trunk/libs/newlib/src/libgloss/bfin/include/defBF542.h @ 615

Download in other formats: