[444] | 1 | /* |
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| 2 | * The authors hereby grant permission to use, copy, modify, distribute, |
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| 3 | * and license this software and its documentation for any purpose, provided |
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| 4 | * that existing copyright notices are retained in all copies and that this |
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| 5 | * notice is included verbatim in any distributions. No written agreement, |
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| 6 | * license, or royalty fee is required for any of the authorized uses. |
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| 7 | * Modifications to this software may be copyrighted by their authors |
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| 8 | * and need not follow the licensing terms described here, provided that |
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| 9 | * the new terms are clearly indicated on the first page of each file where |
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| 10 | * they apply. |
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| 11 | */ |
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| 12 | |
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| 13 | /* |
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| 14 | ** defBF59x_base.h |
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| 15 | ** |
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| 16 | ** Copyright (C) 2009-2010 Analog Devices Inc., All Rights Reserved. |
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| 17 | ** |
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| 18 | ************************************************************************************ |
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| 19 | ** |
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| 20 | ** This include file contains a list of macro "defines" to enable the programmer |
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| 21 | ** to use symbolic names for the registers common to the ADSP-BF59x peripherals. |
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| 22 | ** |
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| 23 | ************************************************************************************ |
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| 24 | ** System MMR Register Map |
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| 25 | ************************************************************************************/ |
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| 26 | |
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| 27 | #ifndef _DEF_BF59x_H |
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| 28 | #define _DEF_BF59x_H |
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| 29 | |
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| 30 | #ifdef _MISRA_RULES |
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| 31 | #pragma diag(push) |
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| 32 | #pragma diag(suppress:misra_rule_19_4) |
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| 33 | #pragma diag(suppress:misra_rule_19_7) |
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| 34 | #include <stdint.h> |
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| 35 | #endif /* _MISRA_RULES */ |
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| 36 | |
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| 37 | |
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| 38 | /* ************************************************************************************************************** */ |
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| 39 | /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF59x */ |
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| 40 | /* ************************************************************************************************************** */ |
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| 41 | |
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| 42 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ |
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| 43 | #define PLL_CTL 0xFFC00000 /* PLL Control Register */ |
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| 44 | #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ |
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| 45 | #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ |
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| 46 | #define PLL_STAT 0xFFC0000C /* PLL Status Register */ |
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| 47 | #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ |
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| 48 | #define CHIPID 0xFFC00014 /* Device ID Register */ |
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| 49 | #define AUX_REVID 0xFFC00108 /* Auxiliary Revision ID Register */ |
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| 50 | |
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| 51 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ |
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| 52 | #define SWRST 0xFFC00100 /* Software Reset Register */ |
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| 53 | #define SYSCR 0xFFC00104 /* System Configuration Register */ |
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| 54 | |
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| 55 | #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ |
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| 56 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 57 | #define SIC_IMASK SIC_IMASK0 |
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| 58 | #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ |
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| 59 | #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ |
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| 60 | #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ |
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| 61 | #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ |
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| 62 | #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ |
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| 63 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 64 | #define SIC_ISR SIC_ISR0 |
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| 65 | #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ |
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| 66 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 67 | #define SIC_IWR SIC_IWR0 |
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| 68 | |
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| 69 | /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ |
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| 70 | #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ |
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| 71 | #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ |
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| 72 | #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ |
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| 73 | |
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| 74 | /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ |
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| 75 | #define UART0_THR 0xFFC00400 /* Transmit Holding register */ |
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| 76 | #define UART0_RBR 0xFFC00400 /* Receive Buffer register */ |
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| 77 | #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ |
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| 78 | #define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ |
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| 79 | #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ |
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| 80 | #define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ |
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| 81 | #define UART0_LCR 0xFFC0040C /* Line Control Register */ |
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| 82 | #define UART0_MCR 0xFFC00410 /* Modem Control Register */ |
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| 83 | #define UART0_LSR 0xFFC00414 /* Line Status Register */ |
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| 84 | #define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ |
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| 85 | #define UART0_GCTL 0xFFC00424 /* Global Control Register */ |
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| 86 | |
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| 87 | |
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| 88 | /* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ |
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| 89 | #define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ |
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| 90 | #define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */ |
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| 91 | #define SPI0_STAT 0xFFC00508 /* SPI0 Status register */ |
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| 92 | #define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ |
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| 93 | #define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ |
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| 94 | #define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */ |
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| 95 | #define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */ |
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| 96 | |
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| 97 | /* SPI1 Controller (0xFFC01300 - 0xFFC013FF) */ |
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| 98 | #define SPI1_CTL 0xFFC01300 /* SPI1 Control Register */ |
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| 99 | #define SPI1_FLG 0xFFC01304 /* SPI1 Flag register */ |
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| 100 | #define SPI1_STAT 0xFFC01308 /* SPI1 Status register */ |
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| 101 | #define SPI1_TDBR 0xFFC0130C /* SPI1 Transmit Data Buffer Register */ |
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| 102 | #define SPI1_RDBR 0xFFC01310 /* SPI1 Receive Data Buffer Register */ |
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| 103 | #define SPI1_BAUD 0xFFC01314 /* SPI1 Baud rate Register */ |
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| 104 | #define SPI1_SHADOW 0xFFC01318 /* SPI1_RDBR Shadow Register */ |
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| 105 | |
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| 106 | |
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| 107 | /* TIMER0-2 Registers (0xFFC00600 - 0xFFC006FF) */ |
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| 108 | #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ |
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| 109 | #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ |
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| 110 | #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ |
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| 111 | #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ |
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| 112 | |
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| 113 | #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ |
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| 114 | #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ |
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| 115 | #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ |
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| 116 | #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ |
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| 117 | |
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| 118 | #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ |
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| 119 | #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ |
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| 120 | #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ |
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| 121 | #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ |
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| 122 | |
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| 123 | #define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ |
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| 124 | #define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ |
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| 125 | #define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ |
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| 126 | |
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| 127 | |
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| 128 | /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ |
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| 129 | #define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ |
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| 130 | #define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ |
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| 131 | #define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ |
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| 132 | #define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ |
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| 133 | #define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ |
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| 134 | #define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ |
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| 135 | #define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ |
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| 136 | #define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ |
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| 137 | #define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ |
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| 138 | #define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ |
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| 139 | #define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ |
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| 140 | #define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ |
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| 141 | #define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ |
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| 142 | #define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ |
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| 143 | #define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ |
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| 144 | #define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ |
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| 145 | #define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ |
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| 146 | |
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| 147 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ |
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| 148 | #define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ |
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| 149 | #define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ |
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| 150 | #define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ |
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| 151 | #define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ |
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| 152 | #define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ |
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| 153 | #define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ |
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| 154 | #define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ |
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| 155 | #define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ |
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| 156 | #define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ |
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| 157 | #define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ |
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| 158 | #define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ |
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| 159 | #define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ |
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| 160 | #define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ |
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| 161 | #define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ |
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| 162 | #define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ |
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| 163 | #define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ |
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| 164 | #define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ |
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| 165 | |
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| 166 | |
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| 167 | /* Pin Control Registers (0xFFC01100 - 0xFFC01208) */ |
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| 168 | #define PORTF_FER 0xFFC01100 /* Port F Function Enable Register (Alternate/Flag*) */ |
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| 169 | #define PORTF_MUX 0xFFC01104 /* Port F mux control */ |
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| 170 | #define PORTF_PADCTL 0xFFC01108 /* Port F pad control */ |
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| 171 | #define PORTG_FER 0xFFC01200 /* Port G Function Enable Register (Alternate/Flag*) */ |
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| 172 | #define PORTG_MUX 0xFFC01204 /* Port G mux control */ |
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| 173 | #define PORTG_PADCTL 0xFFC01208 /* Port G pad control */ |
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| 174 | |
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| 175 | /* SPORT Clock Gating (0xFFC0120C) */ |
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| 176 | #define SPORT_GATECLK 0xFFC0120C /* SPORT Clock Gating Control Register */ |
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| 177 | |
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| 178 | |
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| 179 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ |
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| 180 | #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ |
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| 181 | #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ |
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| 182 | #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ |
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| 183 | #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ |
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| 184 | #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ |
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| 185 | #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ |
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| 186 | #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ |
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| 187 | #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ |
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| 188 | #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ |
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| 189 | #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ |
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| 190 | #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ |
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| 191 | #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ |
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| 192 | #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ |
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| 193 | #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ |
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| 194 | #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ |
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| 195 | #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ |
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| 196 | #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ |
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| 197 | #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ |
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| 198 | #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ |
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| 199 | #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ |
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| 200 | #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ |
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| 201 | #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ |
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| 202 | |
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| 203 | |
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| 204 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ |
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| 205 | #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ |
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| 206 | #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ |
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| 207 | #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ |
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| 208 | #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ |
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| 209 | #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ |
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| 210 | #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ |
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| 211 | #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ |
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| 212 | #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ |
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| 213 | #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ |
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| 214 | #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ |
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| 215 | #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ |
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| 216 | #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ |
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| 217 | #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ |
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| 218 | #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ |
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| 219 | #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ |
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| 220 | #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ |
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| 221 | #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ |
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| 222 | #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ |
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| 223 | #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ |
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| 224 | #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ |
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| 225 | #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ |
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| 226 | #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ |
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| 227 | |
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| 228 | /* DMA Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */ |
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| 229 | #define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ |
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| 230 | #define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ |
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| 231 | |
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| 232 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ |
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| 233 | #define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ |
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| 234 | #define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ |
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| 235 | |
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| 236 | /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ |
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| 237 | #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ |
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| 238 | #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ |
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| 239 | #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ |
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| 240 | #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ |
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| 241 | #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ |
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| 242 | #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ |
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| 243 | #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ |
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| 244 | #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ |
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| 245 | #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ |
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| 246 | #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ |
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| 247 | #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ |
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| 248 | #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ |
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| 249 | #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ |
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| 250 | |
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| 251 | #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ |
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| 252 | #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ |
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| 253 | #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ |
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| 254 | #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ |
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| 255 | #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ |
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| 256 | #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ |
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| 257 | #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ |
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| 258 | #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ |
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| 259 | #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ |
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| 260 | #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ |
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| 261 | #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ |
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| 262 | #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ |
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| 263 | #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ |
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| 264 | |
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| 265 | #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ |
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| 266 | #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ |
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| 267 | #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ |
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| 268 | #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ |
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| 269 | #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ |
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| 270 | #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ |
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| 271 | #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ |
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| 272 | #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ |
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| 273 | #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ |
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| 274 | #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ |
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| 275 | #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ |
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| 276 | #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ |
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| 277 | #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ |
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| 278 | |
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| 279 | #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ |
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| 280 | #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ |
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| 281 | #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ |
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| 282 | #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ |
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| 283 | #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ |
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| 284 | #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ |
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| 285 | #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ |
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| 286 | #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ |
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| 287 | #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ |
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| 288 | #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ |
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| 289 | #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ |
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| 290 | #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ |
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| 291 | #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ |
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| 292 | |
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| 293 | #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ |
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| 294 | #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ |
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| 295 | #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ |
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| 296 | #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ |
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| 297 | #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ |
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| 298 | #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ |
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| 299 | #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ |
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| 300 | #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ |
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| 301 | #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ |
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| 302 | #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ |
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| 303 | #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ |
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| 304 | #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ |
---|
| 305 | #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ |
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| 306 | |
---|
| 307 | #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ |
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| 308 | #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ |
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| 309 | #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ |
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| 310 | #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ |
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| 311 | #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ |
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| 312 | #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ |
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| 313 | #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ |
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| 314 | #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ |
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| 315 | #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ |
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| 316 | #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ |
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| 317 | #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ |
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| 318 | #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ |
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| 319 | #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ |
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| 320 | |
---|
| 321 | #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ |
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| 322 | #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ |
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| 323 | #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ |
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| 324 | #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ |
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| 325 | #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ |
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| 326 | #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ |
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| 327 | #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ |
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| 328 | #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ |
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| 329 | #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ |
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| 330 | #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ |
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| 331 | #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ |
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| 332 | #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ |
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| 333 | #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ |
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| 334 | |
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| 335 | #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ |
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| 336 | #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ |
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| 337 | #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ |
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| 338 | #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ |
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| 339 | #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ |
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| 340 | #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ |
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| 341 | #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ |
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| 342 | #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ |
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| 343 | #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ |
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| 344 | #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ |
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| 345 | #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ |
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| 346 | #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ |
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| 347 | #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ |
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| 348 | |
---|
| 349 | #define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ |
---|
| 350 | #define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ |
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| 351 | #define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ |
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| 352 | #define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ |
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| 353 | #define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ |
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| 354 | #define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ |
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| 355 | #define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ |
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| 356 | #define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ |
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| 357 | #define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ |
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| 358 | #define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ |
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| 359 | #define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ |
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| 360 | #define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ |
---|
| 361 | #define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ |
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| 362 | |
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| 363 | #define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ |
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| 364 | #define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ |
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| 365 | #define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ |
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| 366 | #define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ |
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| 367 | #define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ |
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| 368 | #define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ |
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| 369 | #define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ |
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| 370 | #define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register*/ |
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| 371 | #define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ |
---|
| 372 | #define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ |
---|
| 373 | #define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ |
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| 374 | #define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ |
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| 375 | #define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ |
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| 376 | |
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| 377 | #define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ |
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| 378 | #define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ |
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| 379 | #define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ |
---|
| 380 | #define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ |
---|
| 381 | #define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ |
---|
| 382 | #define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ |
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| 383 | #define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ |
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| 384 | #define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ |
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| 385 | #define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ |
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| 386 | #define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ |
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| 387 | #define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ |
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| 388 | #define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ |
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| 389 | #define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ |
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| 390 | |
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| 391 | #define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ |
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| 392 | #define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ |
---|
| 393 | #define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ |
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| 394 | #define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ |
---|
| 395 | #define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ |
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| 396 | #define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ |
---|
| 397 | #define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ |
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| 398 | #define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register*/ |
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| 399 | #define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ |
---|
| 400 | #define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ |
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| 401 | #define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ |
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| 402 | #define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ |
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| 403 | #define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ |
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| 404 | |
---|
| 405 | #define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ |
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| 406 | #define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ |
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| 407 | #define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ |
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| 408 | #define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ |
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| 409 | #define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ |
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| 410 | #define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ |
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| 411 | #define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ |
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| 412 | #define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ |
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| 413 | #define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ |
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| 414 | #define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ |
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| 415 | #define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ |
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| 416 | #define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ |
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| 417 | #define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ |
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| 418 | |
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| 419 | |
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| 420 | /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ |
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| 421 | #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ |
---|
| 422 | #define PPI_STATUS 0xFFC01004 /* PPI Status Register */ |
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| 423 | #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ |
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| 424 | #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ |
---|
| 425 | #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ |
---|
| 426 | |
---|
| 427 | |
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| 428 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ |
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| 429 | #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ |
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| 430 | #define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ |
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| 431 | #define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ |
---|
| 432 | #define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ |
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| 433 | #define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ |
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| 434 | #define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ |
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| 435 | #define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ |
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| 436 | #define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ |
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| 437 | #define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ |
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| 438 | #define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ |
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| 439 | #define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ |
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| 440 | #define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ |
---|
| 441 | #define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ |
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| 442 | #define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ |
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| 443 | #define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ |
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| 444 | #define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ |
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| 445 | |
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| 446 | |
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| 447 | /****************************************************************************************************************** |
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| 448 | ** System MMR Register Bits And Macros |
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| 449 | ** |
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| 450 | ** Disclaimer: All macros are intended to make C and Assembly code more readable. |
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| 451 | ** Use these macros carefully, as any that do left shifts for field |
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| 452 | ** depositing will result in the lower order bits being destroyed. Any |
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| 453 | ** macro that shifts left to properly position the bit-field should be |
---|
| 454 | ** used as part of an OR to initialize a register and NOT as a dynamic |
---|
| 455 | ** modifier UNLESS the lower order bits are saved and ORed back in when |
---|
| 456 | ** the macro is used. |
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| 457 | *******************************************************************************************************************/ |
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| 458 | |
---|
| 459 | /************************************** PLL AND RESET MASKS *******************************************************/ |
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| 460 | |
---|
| 461 | /* PLL_CTL Masks */ |
---|
| 462 | #define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ |
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| 463 | #define PLL_OFF 0x0002 /* PLL Not Powered */ |
---|
| 464 | #define STOPCK 0x0008 /* Core Clock Off */ |
---|
| 465 | #define PDWN 0x0020 /* Enter Deep Sleep Mode */ |
---|
| 466 | #define BYPASS 0x0100 /* Bypass the PLL */ |
---|
| 467 | #define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ |
---|
| 468 | |
---|
| 469 | /* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ |
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| 470 | #ifdef _MISRA_RULES |
---|
| 471 | #define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ |
---|
| 472 | #else |
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| 473 | #define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ |
---|
| 474 | #endif /* _MISRA_RULES */ |
---|
| 475 | |
---|
| 476 | /* PLL_DIV Masks */ |
---|
| 477 | #define SSEL 0x000F /* System Select */ |
---|
| 478 | #define CSEL 0x0030 /* Core Select */ |
---|
| 479 | #define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ |
---|
| 480 | #define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ |
---|
| 481 | #define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ |
---|
| 482 | #define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ |
---|
| 483 | |
---|
| 484 | /* PLL_DIV Macros */ |
---|
| 485 | #ifdef _MISRA_RULES |
---|
| 486 | #define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ |
---|
| 487 | #else |
---|
| 488 | #define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ |
---|
| 489 | #endif /* _MISRA_RULES */ |
---|
| 490 | |
---|
| 491 | /* VR_CTL Masks */ |
---|
| 492 | #define WAKE_EN0 0x0100 /* Enable Wakeup From Hibernate/Deep Sleep on the WAKEN0 signal */ |
---|
| 493 | #define WAKE_EN1 0x0200 /* Enable Wakeup From Hibernate/Deep Sleep on the WAKEN1 signal */ |
---|
| 494 | #define WAKE_EN2 0x0400 /* Enable Wakeup From Hibernate/Deep Sleep on the WAKEN2 signal */ |
---|
| 495 | #define WAKE_EN3 0x0800 /* Enable Wakeup From Hibernate/Deep Sleep on the WAKEN3 signal */ |
---|
| 496 | #define HIBERNATEB 0x1000 /* Bit mask for HIBERNATEB */ |
---|
| 497 | #define HIBERNATE 0x0000 /* Deasserts EXT_WAKE in order to enter hibernate mode */ |
---|
| 498 | #define EXTCLK_SEL 0x2000 /* Selects SCLK for the EXTCLK signal */ |
---|
| 499 | #define EXTCLK_OE 0x4000 /* Output enable for the EXTCLK signal */ |
---|
| 500 | #define WAKE_POLARITY 0x8000 /* Make wakeups active-high */ |
---|
| 501 | |
---|
| 502 | /* PLL_STAT Masks */ |
---|
| 503 | #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ |
---|
| 504 | #define FULL_ON 0x0002 /* Processor In Full On Mode */ |
---|
| 505 | #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ |
---|
| 506 | #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ |
---|
| 507 | |
---|
| 508 | /* SWRST Masks */ |
---|
| 509 | #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ |
---|
| 510 | #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ |
---|
| 511 | #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ |
---|
| 512 | #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ |
---|
| 513 | #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ |
---|
| 514 | |
---|
| 515 | /* SYSCR Masks */ |
---|
| 516 | #define BMODE_IDLE 0x0000 /* Bypass boot ROM, go to idle */ |
---|
| 517 | #define BMODE_SPI1MEM 0x0002 /* Boot from serial SPI1 memory */ |
---|
| 518 | #define BMODE_SPI1HOST 0x0003 /* Boot from SPI1 host (slave mode) */ |
---|
| 519 | #define BMODE_SPI0MEM 0x0004 /* Boot from serial SPI0 memory */ |
---|
| 520 | #define BMODE_PPI 0x0005 /* Boot from PPI Port */ |
---|
| 521 | #define BMODE_L1ROM 0x0006 /* Boot from internal L1 ROM */ |
---|
| 522 | #define BMODE_UART0HOST 0x0007 /* Boot from UART0 host */ |
---|
| 523 | #define BMODE 0x0007 /* Boot Mode. Mirror of BMODE Mode Pins */ |
---|
| 524 | |
---|
| 525 | #define BCODE 0x00F0 |
---|
| 526 | #define BCODE_NORMAL 0x0000 /* normal boot, update PLL/VR, quickboot as by WURESET */ |
---|
| 527 | #define BCODE_NOBOOT 0x0010 /* bypass boot, don't update PLL/VR */ |
---|
| 528 | #define BCODE_QUICKBOOT 0x0020 /* quick boot, overrule WURESET, don't update PLL/VR */ |
---|
| 529 | #define BCODE_ALLBOOT 0x0040 /* no quick boot, overrule WURESET, don't update PLL/VR */ |
---|
| 530 | #define BCODE_FULLBOOT 0x0060 /* no quick boot, overrule WURESET, update PLL/VR */ |
---|
| 531 | |
---|
| 532 | #define WURESET 0x1000 /* wakeup event since last hardware reset */ |
---|
| 533 | #define DFRESET 0x2000 /* recent reset was due to a double fault event */ |
---|
| 534 | #define WDRESET 0x4000 /* recent reset was due to a watchdog event */ |
---|
| 535 | #define SWRESET 0x8000 /* recent reset was issued by software */ |
---|
| 536 | |
---|
| 537 | /********************************* SYSTEM INTERRUPT CONTROLLER MASKS *********************************************/ |
---|
| 538 | /* Peripheral Masks For SIC_ISR0, SIC_IWR0, SIC_IMASK0 */ |
---|
| 539 | #define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ |
---|
| 540 | #define IRQ_DMA_ERR0 0x00000002 /* Error Interrupt (DMA error 0 interrupt (generic)) */ |
---|
| 541 | #define IRQ_PPI_ERR 0x00000004 /* Error Interrupt (PPI error interrupt) */ |
---|
| 542 | #define IRQ_SPORT0_ERR 0x00000008 /* Error Interrupt (SPORT0 status interrupt) */ |
---|
| 543 | #define IRQ_SPORT1_ERR 0x00000010 /* Error Interrupt (SPORT1 status interrupt) */ |
---|
| 544 | #define IRQ_SPI0_ERR 0x00000020 /* Error Interrupt (SPI0 status interrupt) */ |
---|
| 545 | #define IRQ_SPI1_ERR 0x00000040 /* Error Interrupt (SPI1 status interrupt) */ |
---|
| 546 | #define IRQ_UART0_ERR 0x00000080 /* Error Interrupt (UART0 status interrupt) */ |
---|
| 547 | #define IRQ_DMA0 0x00000100 /* DMA channel 0 (PPI) Interrupt */ |
---|
| 548 | #define IRQ_DMA1 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt */ |
---|
| 549 | #define IRQ_DMA2 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt */ |
---|
| 550 | #define IRQ_DMA3 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt */ |
---|
| 551 | #define IRQ_DMA4 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt */ |
---|
| 552 | #define IRQ_DMA5 0x00002000 /* DMA Channel 5 (SPI0) Interrupt */ |
---|
| 553 | #define IRQ_DMA6 0x00004000 /* DMA Channel 6 (SPI1) Interrupt */ |
---|
| 554 | #define IRQ_DMA7 0x00008000 /* DMA Channel 7 (UART0 RX) Interrupt */ |
---|
| 555 | #define IRQ_DMA8 0x00010000 /* DMA Channel 8 (UART0 TX) Interrupt */ |
---|
| 556 | #define IRQ_PFA_PORTF 0x00020000 /* PF Port F Interrupt A */ |
---|
| 557 | #define IRQ_PFB_PORTF 0x00040000 /* PF Port F Interrupt B */ |
---|
| 558 | #define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */ |
---|
| 559 | #define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */ |
---|
| 560 | #define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */ |
---|
| 561 | #define IRQ_PFA_PORTG 0x00400000 /* PF Port G Interrupt A */ |
---|
| 562 | #define IRQ_PFB_PORTG 0x00800000 /* PF Port G Interrupt B */ |
---|
| 563 | #define IRQ_TWI 0x01000000 /* TWI Interrupt */ |
---|
| 564 | #define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA0 Destination) TX Interrupt */ |
---|
| 565 | #define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA0 Source) RX Interrupt */ |
---|
| 566 | #define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA1 Destination) TX Interrupt */ |
---|
| 567 | #define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA1 Source) RX Interrupt */ |
---|
| 568 | #define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ |
---|
| 569 | |
---|
| 570 | /* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ |
---|
| 571 | #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ |
---|
| 572 | #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ |
---|
| 573 | /* x = pos 0 to 31, for 32-63 use value-32 */ |
---|
| 574 | #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ |
---|
| 575 | #define IWR_DISABLE(x) (0xFFFFFFFF^(1<<(x))) /* Wakeup Disable Peripheral #x */ |
---|
| 576 | |
---|
| 577 | |
---|
| 578 | #ifdef _MISRA_RULES |
---|
| 579 | #define _MF15 0xFu |
---|
| 580 | #define _MF7 7u |
---|
| 581 | #else |
---|
| 582 | #define _MF15 0xF |
---|
| 583 | #define _MF7 7 |
---|
| 584 | #endif /* _MISRA_RULES */ |
---|
| 585 | |
---|
| 586 | |
---|
| 587 | /* SIC_IAR0 Macros*/ |
---|
| 588 | #define P0_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #0 assigned IVG #x */ |
---|
| 589 | #define P1_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #1 assigned IVG #x */ |
---|
| 590 | #define P2_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #2 assigned IVG #x */ |
---|
| 591 | #define P3_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #3 assigned IVG #x */ |
---|
| 592 | #define P4_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #4 assigned IVG #x */ |
---|
| 593 | #define P5_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #5 assigned IVG #x */ |
---|
| 594 | #define P6_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #6 assigned IVG #x */ |
---|
| 595 | #define P7_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #7 assigned IVG #x */ |
---|
| 596 | |
---|
| 597 | /* SIC_IAR1 Macros*/ |
---|
| 598 | #define P8_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #8 assigned IVG #x */ |
---|
| 599 | #define P9_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #9 assigned IVG #x */ |
---|
| 600 | #define P10_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #10 assigned IVG #x */ |
---|
| 601 | #define P11_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #11 assigned IVG #x */ |
---|
| 602 | #define P12_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #12 assigned IVG #x */ |
---|
| 603 | #define P13_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #13 assigned IVG #x */ |
---|
| 604 | #define P14_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #14 assigned IVG #x */ |
---|
| 605 | #define P15_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #15 assigned IVG #x */ |
---|
| 606 | |
---|
| 607 | /* SIC_IAR2 Macros*/ |
---|
| 608 | #define P16_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #16 assigned IVG #x */ |
---|
| 609 | #define P17_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #17 assigned IVG #x */ |
---|
| 610 | #define P18_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #18 assigned IVG #x */ |
---|
| 611 | #define P19_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #19 assigned IVG #x */ |
---|
| 612 | #define P20_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #20 assigned IVG #x */ |
---|
| 613 | #define P21_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #21 assigned IVG #x */ |
---|
| 614 | #define P22_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #22 assigned IVG #x */ |
---|
| 615 | #define P23_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #23 assigned IVG #x */ |
---|
| 616 | |
---|
| 617 | /* SIC_IAR3 Macros*/ |
---|
| 618 | #define P24_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #24 assigned IVG #x */ |
---|
| 619 | #define P29_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #29 assigned IVG #x */ |
---|
| 620 | #define P30_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #30 assigned IVG #x */ |
---|
| 621 | #define P31_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #31 assigned IVG #x */ |
---|
| 622 | |
---|
| 623 | |
---|
| 624 | /* SIC_IMASK0 Masks*/ |
---|
| 625 | #define SIC_UNMASK0_ALL 0x00000000 /* Unmask all peripheral interrupts */ |
---|
| 626 | #define SIC_MASK0_ALL 0xE1FFFFFF /* Mask all peripheral interrupts */ |
---|
| 627 | |
---|
| 628 | /* SIC_IWR0 Masks*/ |
---|
| 629 | #define IWR0_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ |
---|
| 630 | #define IWR0_ENABLE_ALL 0xE1FFFFFF /* Wakeup Enable all peripherals */ |
---|
| 631 | |
---|
| 632 | |
---|
| 633 | /* ************************************** WATCHDOG TIMER MASKS ****************************************************/ |
---|
| 634 | |
---|
| 635 | /* Watchdog Timer WDOG_CTL Register Masks */ |
---|
| 636 | #ifdef _MISRA_RULES |
---|
| 637 | #define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */ |
---|
| 638 | #else |
---|
| 639 | #define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */ |
---|
| 640 | #endif /* _MISRA_RULES */ |
---|
| 641 | |
---|
| 642 | #define WDEV_RESET 0x0000 /* generate reset event on roll over */ |
---|
| 643 | #define WDEV_NMI 0x0002 /* generate NMI event on roll over */ |
---|
| 644 | #define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */ |
---|
| 645 | #define WDEV_NONE 0x0006 /* no event on roll over */ |
---|
| 646 | #define WDEN 0x0FF0 /* enable watchdog */ |
---|
| 647 | #define WDDIS 0x0AD0 /* disable watchdog */ |
---|
| 648 | #define WDRO 0x8000 /* watchdog rolled over latch */ |
---|
| 649 | |
---|
| 650 | /* depreciated WDOG_CTL Register Masks for legacy code */ |
---|
| 651 | #define ICTL WDEV |
---|
| 652 | #define ENABLE_RESET WDEV_RESET |
---|
| 653 | #define WDOG_RESET WDEV_RESET |
---|
| 654 | #define ENABLE_NMI WDEV_NMI |
---|
| 655 | #define WDOG_NMI WDEV_NMI |
---|
| 656 | #define ENABLE_GPI WDEV_GPI |
---|
| 657 | #define WDOG_GPI WDEV_GPI |
---|
| 658 | #define DISABLE_EVT WDEV_NONE |
---|
| 659 | #define WDOG_NONE WDEV_NONE |
---|
| 660 | |
---|
| 661 | #define TMR_EN WDEN |
---|
| 662 | #define TMR_DIS WDDIS |
---|
| 663 | #define TRO WDRO |
---|
| 664 | #define ICTL_P0 0x01 |
---|
| 665 | #define ICTL_P1 0x02 |
---|
| 666 | #define TRO_P 0x0F |
---|
| 667 | |
---|
| 668 | |
---|
| 669 | /* ************************************ UART CONTROLLER MASKS *****************************************************/ |
---|
| 670 | |
---|
| 671 | /* UARTx_LCR Masks*/ |
---|
| 672 | #ifdef _MISRA_RULES |
---|
| 673 | #define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */ |
---|
| 674 | #else |
---|
| 675 | #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ |
---|
| 676 | #endif /* _MISRA_RULES */ |
---|
| 677 | |
---|
| 678 | #define STB 0x04 /* Stop Bits */ |
---|
| 679 | #define PEN 0x08 /* Parity Enable */ |
---|
| 680 | #define EPS 0x10 /* Even Parity Select */ |
---|
| 681 | #define STP 0x20 /* Stick Parity */ |
---|
| 682 | #define SB 0x40 /* Set Break */ |
---|
| 683 | #define DLAB 0x80 /* Divisor Latch Access */ |
---|
| 684 | |
---|
| 685 | /* UARTx_MCR Mask */ |
---|
| 686 | #define LOOP_ENA 0x10 /* Loopback Mode Enable */ |
---|
| 687 | |
---|
| 688 | /* UARTx_LSR Masks */ |
---|
| 689 | #define DR 0x01 /* Data Ready */ |
---|
| 690 | #define OE 0x02 /* Overrun Error */ |
---|
| 691 | #define PE 0x04 /* Parity Error */ |
---|
| 692 | #define FE 0x08 /* Framing Error */ |
---|
| 693 | #define BI 0x10 /* Break Interrupt */ |
---|
| 694 | #define THRE 0x20 /* THR Empty */ |
---|
| 695 | #define TEMT 0x40 /* TSR and UART_THR Empty */ |
---|
| 696 | |
---|
| 697 | /* UARTx_IER Masks*/ |
---|
| 698 | #define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ |
---|
| 699 | #define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ |
---|
| 700 | #define ELSI 0x04 /* Enable RX Status Interrupt */ |
---|
| 701 | |
---|
| 702 | /* UARTx_IIR Masks*/ |
---|
| 703 | #define NINT 0x01 /* Pending Interrupt */ |
---|
| 704 | #define STATUS 0x06 /* Highest Priority Pending Interrupt */ |
---|
| 705 | |
---|
| 706 | /* UARTx_GCTL Masks*/ |
---|
| 707 | #define UCEN 0x01 /* Enable UARTx Clocks */ |
---|
| 708 | #define IREN 0x02 /* Enable IrDA Mode */ |
---|
| 709 | #define TPOLC 0x04 /* IrDA TX Polarity Change */ |
---|
| 710 | #define RPOLC 0x08 /* IrDA RX Polarity Change */ |
---|
| 711 | #define FPE 0x10 /* Force Parity Error On Transmit */ |
---|
| 712 | #define FFE 0x20 /* Force Framing Error On Transmit */ |
---|
| 713 | |
---|
| 714 | /* Bit masks for UART Divisor Latch Registers: UARTx_DLL & UARTx_DLH */ |
---|
| 715 | #define UARTDLL 0x00FF /* Divisor Latch Low Byte */ |
---|
| 716 | #define UARTDLH 0xFF00 /* Divisor Latch High Byte */ |
---|
| 717 | |
---|
| 718 | |
---|
| 719 | /******************************** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ***************************************/ |
---|
| 720 | |
---|
| 721 | /* SPIx_CTL Masks*/ |
---|
| 722 | #define TIMOD 0x0003 /* Transfer Initiate Mode */ |
---|
| 723 | #define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ |
---|
| 724 | #define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ |
---|
| 725 | #define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ |
---|
| 726 | #define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ |
---|
| 727 | #define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ |
---|
| 728 | #define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ |
---|
| 729 | #define PSSE 0x0010 /* Slave-Select Input Enable */ |
---|
| 730 | #define EMISO 0x0020 /* Enable MISO As Output */ |
---|
| 731 | #define SIZE 0x0100 /* Size of Words (16/8* Bits) */ |
---|
| 732 | #define LSBF 0x0200 /* LSB First */ |
---|
| 733 | #define CPHA 0x0400 /* Clock Phase */ |
---|
| 734 | #define CPOL 0x0800 /* Clock Polarity */ |
---|
| 735 | #define MSTR 0x1000 /* Master/Slave* */ |
---|
| 736 | #define WOM 0x2000 /* Write Open Drain Master */ |
---|
| 737 | #define SPE 0x4000 /* SPI Enable */ |
---|
| 738 | |
---|
| 739 | /* SPIx_FLG Masks*/ |
---|
| 740 | #define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */ |
---|
| 741 | #define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */ |
---|
| 742 | #define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */ |
---|
| 743 | #define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */ |
---|
| 744 | #define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */ |
---|
| 745 | #define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */ |
---|
| 746 | #define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */ |
---|
| 747 | #define FLG1 0xFDFF /* Activates SPI_FLOUT1 */ |
---|
| 748 | #define FLG2 0xFBFF /* Activates SPI_FLOUT2 */ |
---|
| 749 | #define FLG3 0xF7FF /* Activates SPI_FLOUT3 */ |
---|
| 750 | #define FLG4 0xEFFF /* Activates SPI_FLOUT4 */ |
---|
| 751 | #define FLG5 0xDFFF /* Activates SPI_FLOUT5 */ |
---|
| 752 | #define FLG6 0xBFFF /* Activates SPI_FLOUT6 */ |
---|
| 753 | #define FLG7 0x7FFF /* Activates SPI_FLOUT7 */ |
---|
| 754 | |
---|
| 755 | /* SPIx_STAT Masks*/ |
---|
| 756 | #define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */ |
---|
| 757 | #define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */ |
---|
| 758 | #define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */ |
---|
| 759 | #define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */ |
---|
| 760 | #define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */ |
---|
| 761 | #define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ |
---|
| 762 | #define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ |
---|
| 763 | |
---|
| 764 | |
---|
| 765 | /*********************************** GENERAL PURPOSE TIMER MASKS ************************************************/ |
---|
| 766 | /* TIMER_ENABLE Masks*/ |
---|
| 767 | #define TIMEN0 0x0001 /* Enable Timer 0 */ |
---|
| 768 | #define TIMEN1 0x0002 /* Enable Timer 1 */ |
---|
| 769 | #define TIMEN2 0x0004 /* Enable Timer 2 */ |
---|
| 770 | |
---|
| 771 | /* TIMER_DISABLE Masks*/ |
---|
| 772 | #define TIMDIS0 TIMEN0 /* Disable Timer 0 */ |
---|
| 773 | #define TIMDIS1 TIMEN1 /* Disable Timer 1 */ |
---|
| 774 | #define TIMDIS2 TIMEN2 /* Disable Timer 2 */ |
---|
| 775 | |
---|
| 776 | /* TIMER_STATUS Masks*/ |
---|
| 777 | #define TIMIL0 0x00000001 /* Timer 0 Interrupt */ |
---|
| 778 | #define TIMIL1 0x00000002 /* Timer 1 Interrupt */ |
---|
| 779 | #define TIMIL2 0x00000004 /* Timer 2 Interrupt */ |
---|
| 780 | #define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ |
---|
| 781 | #define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ |
---|
| 782 | #define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ |
---|
| 783 | #define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ |
---|
| 784 | #define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ |
---|
| 785 | #define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ |
---|
| 786 | |
---|
| 787 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ |
---|
| 788 | #define TOVL_ERR0 TOVF_ERR0 |
---|
| 789 | #define TOVL_ERR1 TOVF_ERR1 |
---|
| 790 | #define TOVL_ERR2 TOVF_ERR2 |
---|
| 791 | |
---|
| 792 | /* TIMERx_CONFIG Masks */ |
---|
| 793 | #define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ |
---|
| 794 | #define WDTH_CAP 0x0002 /* Width Capture Input Mode */ |
---|
| 795 | #define EXT_CLK 0x0003 /* External Clock Mode */ |
---|
| 796 | #define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ |
---|
| 797 | #define PERIOD_CNT 0x0008 /* Period Count */ |
---|
| 798 | #define IRQ_ENA 0x0010 /* Interrupt Request Enable */ |
---|
| 799 | #define TIN_SEL 0x0020 /* Timer Input Select */ |
---|
| 800 | #define OUT_DIS 0x0040 /* Output Pad Disable */ |
---|
| 801 | #define CLK_SEL 0x0080 /* Timer Clock Select */ |
---|
| 802 | #define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ |
---|
| 803 | #define EMU_RUN 0x0200 /* Emulation Behavior Select */ |
---|
| 804 | #define ERR_TYP 0xC000 /* Error Type */ |
---|
| 805 | |
---|
| 806 | |
---|
| 807 | /* ************************************* GPIO PORTS F, G MASKS **********************************************/ |
---|
| 808 | |
---|
| 809 | /* General Purpose IO Masks */ |
---|
| 810 | /* Port F Masks */ |
---|
| 811 | #define PF0 0x0001 |
---|
| 812 | #define PF1 0x0002 |
---|
| 813 | #define PF2 0x0004 |
---|
| 814 | #define PF3 0x0008 |
---|
| 815 | #define PF4 0x0010 |
---|
| 816 | #define PF5 0x0020 |
---|
| 817 | #define PF6 0x0040 |
---|
| 818 | #define PF7 0x0080 |
---|
| 819 | #define PF8 0x0100 |
---|
| 820 | #define PF9 0x0200 |
---|
| 821 | #define PF10 0x0400 |
---|
| 822 | #define PF11 0x0800 |
---|
| 823 | #define PF12 0x1000 |
---|
| 824 | #define PF13 0x2000 |
---|
| 825 | #define PF14 0x4000 |
---|
| 826 | #define PF15 0x8000 |
---|
| 827 | |
---|
| 828 | /* Port G Masks */ |
---|
| 829 | #define PG0 0x0001 |
---|
| 830 | #define PG1 0x0002 |
---|
| 831 | #define PG2 0x0004 |
---|
| 832 | #define PG3 0x0008 |
---|
| 833 | #define PG4 0x0010 |
---|
| 834 | #define PG5 0x0020 |
---|
| 835 | #define PG6 0x0040 |
---|
| 836 | #define PG7 0x0080 |
---|
| 837 | #define PG8 0x0100 |
---|
| 838 | #define PG9 0x0200 |
---|
| 839 | #define PG10 0x0400 |
---|
| 840 | #define PG11 0x0800 |
---|
| 841 | #define PG12 0x1000 |
---|
| 842 | #define PG13 0x2000 |
---|
| 843 | #define PG14 0x4000 |
---|
| 844 | #define PG15 0x8000 |
---|
| 845 | |
---|
| 846 | /* ************************************** SERIAL PORT MASKS *****************************************************/ |
---|
| 847 | /* SPORT_GATECLK Masks */ |
---|
| 848 | #define SPORT0_GATECLK_EN 0x0001 /* SPORT0 Clock Gating Enable */ |
---|
| 849 | #define SPORT0_GATECLK_MODE 0x0002 /* SPORT0 Clock Gating Mode */ |
---|
| 850 | #define SPORT0_GATECLK_STATE 0x0004 /* SPORT0 Clock Gating State */ |
---|
| 851 | #define SPORT1_GATECLK_EN 0x0010 /* SPORT1 Clock Gating Enable */ |
---|
| 852 | #define SPORT1_GATECLK_MODE 0x0020 /* SPORT1 Clock Gating Mode */ |
---|
| 853 | #define SPORT1_GATECLK_STATE 0x0040 /* SPORT1 Clock Gating State */ |
---|
| 854 | |
---|
| 855 | /* SPORTx_TCR1 Masks */ |
---|
| 856 | #define TSPEN 0x0001 /* Transmit Enable */ |
---|
| 857 | #define ITCLK 0x0002 /* Internal Transmit Clock Select */ |
---|
| 858 | #define DTYPE_NORM 0x0004 /* Data Format Normal */ |
---|
| 859 | #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ |
---|
| 860 | #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ |
---|
| 861 | #define TLSBIT 0x0010 /* Transmit Bit Order */ |
---|
| 862 | #define ITFS 0x0200 /* Internal Transmit Frame Sync Select */ |
---|
| 863 | #define TFSR 0x0400 /* Transmit Frame Sync Required Select */ |
---|
| 864 | #define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */ |
---|
| 865 | #define LTFS 0x1000 /* Low Transmit Frame Sync Select */ |
---|
| 866 | #define LATFS 0x2000 /* Late Transmit Frame Sync Select */ |
---|
| 867 | #define TCKFE 0x4000 /* Clock Falling Edge Select */ |
---|
| 868 | |
---|
| 869 | /* SPORTx_TCR2 Masks and Macro */ |
---|
| 870 | #ifdef _MISRA_RULES |
---|
| 871 | #define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */ |
---|
| 872 | #else |
---|
| 873 | #define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */ |
---|
| 874 | #endif /* _MISRA_RULES */ |
---|
| 875 | |
---|
| 876 | #define TXSE 0x0100 /* TX Secondary Enable */ |
---|
| 877 | #define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */ |
---|
| 878 | #define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */ |
---|
| 879 | |
---|
| 880 | /* SPORTx_RCR1 Masks */ |
---|
| 881 | #define RSPEN 0x0001 /* Receive Enable */ |
---|
| 882 | #define IRCLK 0x0002 /* Internal Receive Clock Select */ |
---|
| 883 | #define DTYPE_NORM 0x0004 /* Data Format Normal */ |
---|
| 884 | #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ |
---|
| 885 | #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ |
---|
| 886 | #define RLSBIT 0x0010 /* Receive Bit Order */ |
---|
| 887 | #define IRFS 0x0200 /* Internal Receive Frame Sync Select */ |
---|
| 888 | #define RFSR 0x0400 /* Receive Frame Sync Required Select */ |
---|
| 889 | #define LRFS 0x1000 /* Low Receive Frame Sync Select */ |
---|
| 890 | #define LARFS 0x2000 /* Late Receive Frame Sync Select */ |
---|
| 891 | #define RCKFE 0x4000 /* Clock Falling Edge Select */ |
---|
| 892 | |
---|
| 893 | /* SPORTx_RCR2 Masks */ |
---|
| 894 | #ifdef _MISRA_RULES |
---|
| 895 | #define SLEN(x) ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31) */ |
---|
| 896 | #else |
---|
| 897 | #define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */ |
---|
| 898 | #endif /* _MISRA_RULES */ |
---|
| 899 | |
---|
| 900 | #define RXSE 0x0100 /* RX Secondary Enable */ |
---|
| 901 | #define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ |
---|
| 902 | #define RRFST 0x0400 /* Right-First Data Order */ |
---|
| 903 | |
---|
| 904 | /* SPORTx_STAT Masks */ |
---|
| 905 | #define RXNE 0x0001 /* Receive FIFO Not Empty Status */ |
---|
| 906 | #define RUVF 0x0002 /* Sticky Receive Underflow Status */ |
---|
| 907 | #define ROVF 0x0004 /* Sticky Receive Overflow Status */ |
---|
| 908 | #define TXF 0x0008 /* Transmit FIFO Full Status */ |
---|
| 909 | #define TUVF 0x0010 /* Sticky Transmit Underflow Status */ |
---|
| 910 | #define TOVF 0x0020 /* Sticky Transmit Overflow Status */ |
---|
| 911 | #define TXHRE 0x0040 /* Transmit Hold Register Empty */ |
---|
| 912 | |
---|
| 913 | /* SPORTx_MCMC1 Macros */ |
---|
| 914 | #ifdef _MISRA_RULES |
---|
| 915 | #define WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */ |
---|
| 916 | /* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits*/ |
---|
| 917 | #define WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */ |
---|
| 918 | #else |
---|
| 919 | #define WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */ |
---|
| 920 | /* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */ |
---|
| 921 | #define WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */ |
---|
| 922 | #endif /* _MISRA_RULES */ |
---|
| 923 | |
---|
| 924 | /* SPORTx_MCMC2 Masks */ |
---|
| 925 | #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ |
---|
| 926 | #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ |
---|
| 927 | #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ |
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| 928 | #define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ |
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| 929 | #define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ |
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| 930 | #define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ |
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| 931 | #define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ |
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| 932 | #define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ |
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| 933 | #define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ |
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| 934 | #define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ |
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| 935 | #define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ |
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| 936 | #define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ |
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| 937 | #define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ |
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| 938 | #define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ |
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| 939 | #define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ |
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| 940 | #define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ |
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| 941 | #define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ |
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| 942 | #define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ |
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| 943 | #define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ |
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| 944 | #define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ |
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| 945 | #define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ |
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| 946 | #define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ |
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| 947 | #define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ |
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| 948 | |
---|
| 949 | |
---|
| 950 | /**************************************** DMA CONTROLLER MASKS **************************************************/ |
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| 951 | |
---|
| 952 | /* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ |
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| 953 | #define DMAEN 0x0001 /* DMA Channel Enable */ |
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| 954 | #define WNR 0x0002 /* Channel Direction (W/R*) */ |
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| 955 | #define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ |
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| 956 | #define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ |
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| 957 | #define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ |
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| 958 | #define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ |
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| 959 | #define SYNC 0x0020 /* DMA Buffer Clear */ |
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| 960 | #define DI_SEL 0x0040 /* Data Interrupt Timing Select */ |
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| 961 | #define DI_EN 0x0080 /* Data Interrupt Enable */ |
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| 962 | #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ |
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| 963 | #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ |
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| 964 | #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ |
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| 965 | #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ |
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| 966 | #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ |
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| 967 | #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ |
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| 968 | #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ |
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| 969 | #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ |
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| 970 | #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ |
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| 971 | #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ |
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| 972 | #define FLOW_STOP 0x0000 /* Stop Mode */ |
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| 973 | #define FLOW_AUTO 0x1000 /* Autobuffer Mode */ |
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| 974 | #define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */ |
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| 975 | #define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ |
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| 976 | #define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ |
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| 977 | |
---|
| 978 | /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ |
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| 979 | #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ |
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| 980 | #define PMAP 0xF000 /* Peripheral Mapped To This Channel */ |
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| 981 | #define PMAP_PPI 0x0000 /* PPI Port DMA */ |
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| 982 | #define PMAP_SPORT0RX 0x1000 /* SPORT0 Receive DMA */ |
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| 983 | #define PMAP_SPORT0TX 0x2000 /* SPORT0 Transmit DMA */ |
---|
| 984 | #define PMAP_SPORT1RX 0x3000 /* SPORT1 Receive DMA */ |
---|
| 985 | #define PMAP_SPORT1TX 0x4000 /* SPORT1 Transmit DMA */ |
---|
| 986 | #define PMAP_SPI0 0x5000 /* SPI0 Transmit/Receive DMA */ |
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| 987 | #define PMAP_SPI1 0x6000 /* SPI1 Transmit/Receive DMA */ |
---|
| 988 | #define PMAP_UART0RX 0x7000 /* UART0 Port Receive DMA */ |
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| 989 | #define PMAP_UART0TX 0x8000 /* UART0 Port Transmit DMA */ |
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| 990 | |
---|
| 991 | /* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ |
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| 992 | #define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ |
---|
| 993 | #define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ |
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| 994 | #define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ |
---|
| 995 | #define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ |
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| 996 | |
---|
| 997 | |
---|
| 998 | /********************************* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************************************/ |
---|
| 999 | |
---|
| 1000 | /* PPI_CONTROL Masks */ |
---|
| 1001 | #define PORT_EN 0x0001 /* PPI Port Enable */ |
---|
| 1002 | #define PORT_DIR 0x0002 /* PPI Port Direction */ |
---|
| 1003 | #define XFR_TYPE 0x000C /* PPI Transfer Type */ |
---|
| 1004 | #define PORT_CFG 0x0030 /* PPI Port Configuration */ |
---|
| 1005 | #define FLD_SEL 0x0040 /* PPI Active Field Select */ |
---|
| 1006 | #define PACK_EN 0x0080 /* PPI Packing Mode */ /* previous versions of defBF532.h erroneously included DMA32 (PPI 32-bit DMA Enable) */ |
---|
| 1007 | #define SKIP_EN 0x0200 /* PPI Skip Element Enable */ |
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| 1008 | #define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ |
---|
| 1009 | #define DLEN_8 0x0000 /* Data Length = 8 Bits */ |
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| 1010 | #define DLEN_10 0x0800 /* Data Length = 10 Bits */ |
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| 1011 | #define DLEN_11 0x1000 /* Data Length = 11 Bits */ |
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| 1012 | #define DLEN_12 0x1800 /* Data Length = 12 Bits */ |
---|
| 1013 | #define DLEN_13 0x2000 /* Data Length = 13 Bits */ |
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| 1014 | #define DLEN_14 0x2800 /* Data Length = 14 Bits */ |
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| 1015 | #define DLEN_15 0x3000 /* Data Length = 15 Bits */ |
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| 1016 | #define DLEN_16 0x3800 /* Data Length = 16 Bits */ |
---|
| 1017 | #define POLC 0x4000 /* PPI Clock Polarity */ |
---|
| 1018 | #define POLS 0x8000 /* PPI Frame Sync Polarity */ |
---|
| 1019 | |
---|
| 1020 | /* PPI_STATUS Masks */ |
---|
| 1021 | #define LT_ERR_OVR 0x0100 /* Line Track Overflow Error */ |
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| 1022 | #define LT_ERR_UNDR 0x0200 /* Line Track Underflow Error */ |
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| 1023 | #define FLD 0x0400 /* Field Indicator */ |
---|
| 1024 | #define FT_ERR 0x0800 /* Frame Track Error */ |
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| 1025 | #define OVR 0x1000 /* FIFO Overflow Error */ |
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| 1026 | #define UNDR 0x2000 /* FIFO Underrun Error */ |
---|
| 1027 | #define ERR_DET 0x4000 /* Error Detected Indicator */ |
---|
| 1028 | #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ |
---|
| 1029 | |
---|
| 1030 | |
---|
| 1031 | /*************************************** TWO-WIRE INTERFACE (TWI) MASKS *****************************************/ |
---|
| 1032 | |
---|
| 1033 | /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ |
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| 1034 | #ifdef _MISRA_RULES |
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| 1035 | #define CLKLOW(x) ((x) & 0xFFu)/* Periods Clock Is Held Low */ |
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| 1036 | #define CLKHI(y) (((y)&0xFFu)<<0x8)/* Periods Before New Clock Low */ |
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| 1037 | #else |
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| 1038 | #define CLKLOW(x) ((x) & 0xFF)/* Periods Clock Is Held Low */ |
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| 1039 | #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ |
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| 1040 | #endif /* _MISRA_RULES */ |
---|
| 1041 | |
---|
| 1042 | /* TWI_PRESCALE Masks */ |
---|
| 1043 | #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ |
---|
| 1044 | #define TWI_ENA 0x0080 /* TWI Enable */ |
---|
| 1045 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ |
---|
| 1046 | |
---|
| 1047 | /* TWI_SLAVE_CTRL Masks */ |
---|
| 1048 | #define SEN 0x0001 /* Slave Enable */ |
---|
| 1049 | #define SADD_LEN 0x0002 /* Slave Address Length */ |
---|
| 1050 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ |
---|
| 1051 | #define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ |
---|
| 1052 | #define GEN 0x0010 /* General Call Adrress Matching Enabled */ |
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| 1053 | |
---|
| 1054 | /* TWI_SLAVE_STAT Masks */ |
---|
| 1055 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ |
---|
| 1056 | #define GCALL 0x0002 /* General Call Indicator */ |
---|
| 1057 | |
---|
| 1058 | /* TWI_MASTER_CTRL Masks */ |
---|
| 1059 | #define MEN 0x0001 /* Master Mode Enable */ |
---|
| 1060 | #define MADD_LEN 0x0002 /* Master Address Length */ |
---|
| 1061 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ |
---|
| 1062 | #define FAST 0x0008 /* Use Fast Mode Timing Specs */ |
---|
| 1063 | #define STOP 0x0010 /* Issue Stop Condition */ |
---|
| 1064 | #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ |
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| 1065 | #define DCNT 0x3FC0 /* Data Bytes To Transfer */ |
---|
| 1066 | #define SDAOVR 0x4000 /* Serial Data Override */ |
---|
| 1067 | #define SCLOVR 0x8000 /* Serial Clock Override */ |
---|
| 1068 | |
---|
| 1069 | /* TWI_MASTER_STAT Masks */ |
---|
| 1070 | #define MPROG 0x0001 /* Master Transfer In Progress */ |
---|
| 1071 | #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ |
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| 1072 | #define ANAK 0x0004 /* Address Not Acknowledged */ |
---|
| 1073 | #define DNAK 0x0008 /* Data Not Acknowledged */ |
---|
| 1074 | #define BUFRDERR 0x0010 /* Buffer Read Error */ |
---|
| 1075 | #define BUFWRERR 0x0020 /* Buffer Write Error */ |
---|
| 1076 | #define SDASEN 0x0040 /* Serial Data Sense */ |
---|
| 1077 | #define SCLSEN 0x0080 /* Serial Clock Sense */ |
---|
| 1078 | #define BUSBUSY 0x0100 /* Bus Busy Indicator */ |
---|
| 1079 | |
---|
| 1080 | /* TWI_INT_SRC and TWI_INT_ENABLE Masks */ |
---|
| 1081 | #define SINIT 0x0001 /* Slave Transfer Initiated */ |
---|
| 1082 | #define SCOMP 0x0002 /* Slave Transfer Complete */ |
---|
| 1083 | #define SERR 0x0004 /* Slave Transfer Error */ |
---|
| 1084 | #define SOVF 0x0008 /* Slave Overflow */ |
---|
| 1085 | #define MCOMP 0x0010 /* Master Transfer Complete */ |
---|
| 1086 | #define MERR 0x0020 /* Master Transfer Error */ |
---|
| 1087 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ |
---|
| 1088 | #define RCVSERV 0x0080 /* Receive FIFO Service */ |
---|
| 1089 | |
---|
| 1090 | /* TWI_FIFO_CTRL Masks */ |
---|
| 1091 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ |
---|
| 1092 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ |
---|
| 1093 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ |
---|
| 1094 | #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ |
---|
| 1095 | |
---|
| 1096 | /* TWI_FIFO_STAT Masks */ |
---|
| 1097 | #define XMTSTAT 0x0003 /* Transmit FIFO Status */ |
---|
| 1098 | #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ |
---|
| 1099 | #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ |
---|
| 1100 | #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ |
---|
| 1101 | |
---|
| 1102 | #define RCVSTAT 0x000C /* Receive FIFO Status */ |
---|
| 1103 | #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ |
---|
| 1104 | #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ |
---|
| 1105 | #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ |
---|
| 1106 | |
---|
| 1107 | #ifdef _MISRA_RULES |
---|
| 1108 | #pragma diag(pop) |
---|
| 1109 | #endif /* _MISRA_RULES */ |
---|
| 1110 | |
---|
| 1111 | #endif /* _DEF_BF59x_H */ |
---|