[444] | 1 | /* |
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| 2 | * The authors hereby grant permission to use, copy, modify, distribute, |
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| 3 | * and license this software and its documentation for any purpose, provided |
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| 4 | * that existing copyright notices are retained in all copies and that this |
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| 5 | * notice is included verbatim in any distributions. No written agreement, |
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| 6 | * license, or royalty fee is required for any of the authorized uses. |
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| 7 | * Modifications to this software may be copyrighted by their authors |
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| 8 | * and need not follow the licensing terms described here, provided that |
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| 9 | * the new terms are clearly indicated on the first page of each file where |
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| 10 | * they apply. |
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| 11 | */ |
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| 12 | |
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| 13 | /************************************************************************ |
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| 14 | * |
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| 15 | * def_LPBlackfin.h |
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| 16 | * |
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| 17 | * (c) Copyright 2001-2009 Analog Devices, Inc. All rights reserved. |
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| 18 | * |
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| 19 | ************************************************************************/ |
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| 20 | |
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| 21 | /* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */ |
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| 22 | |
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| 23 | #ifndef _DEF_LPBLACKFIN_H |
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| 24 | #define _DEF_LPBLACKFIN_H |
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| 25 | |
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| 26 | #ifdef _MISRA_RULES |
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| 27 | #pragma diag(push) |
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| 28 | #pragma diag(suppress:misra_rule_19_4) |
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| 29 | #pragma diag(suppress:misra_rule_19_7) |
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| 30 | #endif /* _MISRA_RULES */ |
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| 31 | |
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| 32 | |
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| 33 | #if !defined(__ADSPLPBLACKFIN__) |
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| 34 | #warning def_LPBlackfin.h should only be included for 532 compatible chips. |
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| 35 | #endif |
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| 36 | /* ensure macro params bracketed to avoid unexpected evaluations. (GA), MISRA Rule 19.10 */ |
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| 37 | #ifdef _MISRA_RULES |
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| 38 | #define MK_BMSK_( x ) (1ul<<(x)) /* Make a bit mask from a bit position */ |
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| 39 | #else |
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| 40 | #define MK_BMSK_( x ) (1<<(x)) /* Make a bit mask from a bit position */ |
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| 41 | #endif /* _MISRA_RULES */ |
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| 42 | |
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| 43 | /*********************************************************************************** */ |
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| 44 | /* System Register Bits */ |
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| 45 | /*********************************************************************************** */ |
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| 46 | |
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| 47 | /*************************************************** */ |
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| 48 | /* ASTAT register */ |
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| 49 | /*************************************************** */ |
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| 50 | |
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| 51 | /* definitions of ASTAT bit positions */ |
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| 52 | #define ASTAT_AZ_P 0x00000000 /* Result of last ALU0 or shifter operation is zero */ |
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| 53 | #define ASTAT_AN_P 0x00000001 /* Result of last ALU0 or shifter operation is negative */ |
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| 54 | #define ASTAT_CC_P 0x00000005 /* Condition Code, used for holding comparison results */ |
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| 55 | #define ASTAT_AQ_P 0x00000006 /* Quotient Bit */ |
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| 56 | #define ASTAT_RND_MOD_P 0x00000008 /* Rounding mode, set for biased, clear for unbiased */ |
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| 57 | #define ASTAT_AC0_P 0x0000000C /* Result of last ALU0 operation generated a carry */ |
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| 58 | #define ASTAT_AC0_COPY_P 0x00000002 /* Result of last ALU0 operation generated a carry */ |
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| 59 | #define ASTAT_AC1_P 0x0000000D /* Result of last ALU1 operation generated a carry */ |
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| 60 | #define ASTAT_AV0_P 0x00000010 /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */ |
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| 61 | #define ASTAT_AV0S_P 0x00000011 /* Sticky version of ASTAT_AV0 */ |
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| 62 | #define ASTAT_AV1_P 0x00000012 /* Result of last MAC1 operation overflowed, sticky for MAC */ |
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| 63 | #define ASTAT_AV1S_P 0x00000013 /* Sticky version of ASTAT_AV1 */ |
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| 64 | #define ASTAT_V_P 0x00000018 /* Result of last ALU0 or MAC0 operation overflowed */ |
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| 65 | #define ASTAT_V_COPY_P 0x00000003 /* Result of last ALU0 or MAC0 operation overflowed */ |
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| 66 | #define ASTAT_VS_P 0x00000019 /* Sticky version of ASTAT_V */ |
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| 67 | |
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| 68 | /* ** Masks */ |
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| 69 | #define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P) /* Result of last ALU0 or shifter operation is zero */ |
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| 70 | #define ASTAT_AN MK_BMSK_(ASTAT_AN_P) /* Result of last ALU0 or shifter operation is negative */ |
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| 71 | #define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P) /* Result of last ALU0 operation generated a carry */ |
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| 72 | #define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P) /* Result of last ALU0 operation generated a carry */ |
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| 73 | #define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P) /* Result of last ALU0 operation generated a carry */ |
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| 74 | #define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P) /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */ |
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| 75 | #define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P) /* Result of last MAC1 operation overflowed, sticky for MAC */ |
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| 76 | #define ASTAT_CC MK_BMSK_(ASTAT_CC_P) /* Condition Code, used for holding comparison results */ |
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| 77 | #define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P) /* Quotient Bit */ |
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| 78 | #define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P) /* Rounding mode, set for biased, clear for unbiased */ |
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| 79 | #define ASTAT_V MK_BMSK_(ASTAT_V_P) /* Overflow Bit */ |
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| 80 | #define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P) /* Overflow Bit */ |
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| 81 | |
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| 82 | /*************************************************** */ |
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| 83 | /* SEQSTAT register */ |
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| 84 | /*************************************************** */ |
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| 85 | |
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| 86 | /* ** Bit Positions */ |
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| 87 | #define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */ |
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| 88 | #define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */ |
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| 89 | #define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */ |
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| 90 | #define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */ |
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| 91 | #define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */ |
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| 92 | #define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */ |
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| 93 | #define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request, set by IDLE instruction */ |
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| 94 | #define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last reset was a software reset (=1) */ |
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| 95 | #define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */ |
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| 96 | #define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */ |
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| 97 | #define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */ |
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| 98 | #define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */ |
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| 99 | #define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */ |
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| 100 | #define SEQSTAT_HWERRCAUSE5_P 0x00000013 /* Last hw error cause bit 5 */ |
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| 101 | #define SEQSTAT_HWERRCAUSE6_P 0x00000014 /* Last hw error cause bit 6 */ |
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| 102 | #define SEQSTAT_HWERRCAUSE7_P 0x00000015 /* Last hw error cause bit 7 */ |
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| 103 | /* ** Masks */ |
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| 104 | /* Exception cause */ |
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| 105 | #define SEQSTAT_EXCAUSE ( MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \ |
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| 106 | MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \ |
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| 107 | MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \ |
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| 108 | MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \ |
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| 109 | MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \ |
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| 110 | MK_BMSK_(SEQSTAT_EXCAUSE5_P ) ) |
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| 111 | |
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| 112 | /* Indicates whether the last reset was a software reset (=1) */ |
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| 113 | #define SEQSTAT_SFTRESET MK_BMSK_(SEQSTAT_SFTRESET_P ) |
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| 114 | |
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| 115 | /* Last hw error cause */ |
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| 116 | #define SEQSTAT_HWERRCAUSE ( MK_BMSK_(SEQSTAT_HWERRCAUSE0_P ) | \ |
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| 117 | MK_BMSK_(SEQSTAT_HWERRCAUSE1_P ) | \ |
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| 118 | MK_BMSK_(SEQSTAT_HWERRCAUSE2_P ) | \ |
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| 119 | MK_BMSK_(SEQSTAT_HWERRCAUSE3_P ) | \ |
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| 120 | MK_BMSK_(SEQSTAT_HWERRCAUSE4_P ) ) |
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| 121 | |
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| 122 | /*************************************************** */ |
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| 123 | /* SYSCFG register */ |
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| 124 | /*************************************************** */ |
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| 125 | |
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| 126 | /* ** Bit Positions */ |
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| 127 | #define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when set it forces an exception for each instruction executed */ |
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| 128 | #define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */ |
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| 129 | #define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */ |
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| 130 | |
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| 131 | /* ** Masks */ |
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| 132 | #define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P ) /* Supervisor single step, when set it forces an exception for each instruction executed */ |
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| 133 | #define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P ) /* Enable cycle counter (=1) */ |
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| 134 | #define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P) /* Self Nesting Interrupt Enable */ |
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| 135 | /* Backward-compatibility for typos in prior releases */ |
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| 136 | #define SYSCFG_SSSSTEP SYSCFG_SSSTEP |
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| 137 | #define SYSCFG_CCCEN SYSCFG_CCEN |
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| 138 | |
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| 139 | /*********************************************************************************** */ |
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| 140 | /* Core MMR Register Map */ |
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| 141 | /*********************************************************************************** */ |
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| 142 | |
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| 143 | /* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */ |
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| 144 | |
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| 145 | |
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| 146 | #define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */ |
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| 147 | #define DMEM_CONTROL 0xFFE00004 /* Data memory control */ |
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| 148 | #define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ |
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| 149 | #define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */ |
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| 150 | #define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ |
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| 151 | #define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ |
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| 152 | #define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ |
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| 153 | #define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ |
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| 154 | #define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection Lookaside Buffer 3 */ |
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| 155 | #define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection Lookaside Buffer 4 */ |
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| 156 | #define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection Lookaside Buffer 5 */ |
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| 157 | #define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection Lookaside Buffer 6 */ |
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| 158 | #define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection Lookaside Buffer 7 */ |
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| 159 | #define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection Lookaside Buffer 8 */ |
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| 160 | #define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection Lookaside Buffer 9 */ |
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| 161 | #define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection Lookaside Buffer 10 */ |
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| 162 | #define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection Lookaside Buffer 11 */ |
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| 163 | #define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection Lookaside Buffer 12 */ |
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| 164 | #define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection Lookaside Buffer 13 */ |
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| 165 | #define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection Lookaside Buffer 14 */ |
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| 166 | #define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection Lookaside Buffer 15 */ |
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| 167 | #define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ |
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| 168 | #define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ |
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| 169 | #define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ |
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| 170 | #define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ |
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| 171 | #define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ |
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| 172 | #define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ |
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| 173 | #define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ |
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| 174 | #define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ |
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| 175 | #define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ |
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| 176 | #define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ |
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| 177 | #define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ |
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| 178 | #define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ |
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| 179 | #define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ |
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| 180 | #define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ |
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| 181 | #define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ |
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| 182 | #define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ |
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| 183 | #define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ |
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| 184 | #define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ |
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| 185 | #define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ |
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| 186 | |
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| 187 | /* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */ |
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| 188 | |
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| 189 | #define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ |
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| 190 | #define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */ |
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| 191 | #define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */ |
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| 192 | #define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */ |
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| 193 | #define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */ |
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| 194 | #define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ |
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| 195 | #define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ |
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| 196 | #define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ |
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| 197 | #define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ |
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| 198 | #define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ |
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| 199 | #define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ |
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| 200 | #define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ |
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| 201 | #define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ |
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| 202 | #define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ |
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| 203 | #define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ |
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| 204 | #define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ |
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| 205 | #define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ |
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| 206 | #define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ |
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| 207 | #define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ |
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| 208 | #define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ |
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| 209 | #define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ |
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| 210 | #define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ |
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| 211 | #define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ |
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| 212 | #define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ |
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| 213 | #define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ |
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| 214 | #define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ |
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| 215 | #define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ |
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| 216 | #define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ |
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| 217 | #define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ |
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| 218 | #define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ |
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| 219 | #define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ |
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| 220 | #define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ |
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| 221 | #define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ |
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| 222 | #define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ |
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| 223 | #define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ |
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| 224 | #define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ |
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| 225 | #define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ |
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| 226 | #define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ |
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| 227 | #define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ |
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| 228 | #define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ |
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| 229 | |
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| 230 | /* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */ |
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| 231 | |
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| 232 | #define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ |
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| 233 | #define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ |
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| 234 | #define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ |
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| 235 | #define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ |
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| 236 | #define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ |
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| 237 | #define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ |
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| 238 | #define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ |
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| 239 | #define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ |
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| 240 | #define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ |
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| 241 | #define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ |
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| 242 | #define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ |
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| 243 | #define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ |
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| 244 | #define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ |
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| 245 | #define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ |
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| 246 | #define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ |
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| 247 | #define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ |
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| 248 | #define IMASK 0xFFE02104 /* Interrupt Mask Register */ |
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| 249 | #define IPEND 0xFFE02108 /* Interrupt Pending Register */ |
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| 250 | #define ILAT 0xFFE0210C /* Interrupt Latch Register */ |
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| 251 | #define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */ |
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| 252 | |
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| 253 | /* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */ |
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| 254 | |
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| 255 | #define TCNTL 0xFFE03000 /* Core Timer Control Register */ |
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| 256 | #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ |
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| 257 | #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ |
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| 258 | #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ |
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| 259 | |
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| 260 | /* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */ |
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| 261 | #define DSPID 0xFFE05000 /* DSP Processor ID Register for MP implementations */ |
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| 262 | |
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| 263 | #define DBGSTAT 0xFFE05008 /* Debug Status Register */ |
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| 264 | |
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| 265 | |
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| 266 | /* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */ |
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| 267 | |
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| 268 | #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ |
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| 269 | #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ |
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| 270 | #define TBUF 0xFFE06100 /* Trace Buffer */ |
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| 271 | |
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| 272 | /* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */ |
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| 273 | |
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| 274 | #define WPIACTL 0xFFE07000 /* Watchpoint Instruction Address Control Register */ |
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| 275 | #define WPIA0 0xFFE07040 /* Watchpoint Instruction Address Register 0 */ |
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| 276 | #define WPIA1 0xFFE07044 /* Watchpoint Instruction Address Register 1 */ |
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| 277 | #define WPIA2 0xFFE07048 /* Watchpoint Instruction Address Register 2 */ |
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| 278 | #define WPIA3 0xFFE0704C /* Watchpoint Instruction Address Register 3 */ |
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| 279 | #define WPIA4 0xFFE07050 /* Watchpoint Instruction Address Register 4 */ |
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| 280 | #define WPIA5 0xFFE07054 /* Watchpoint Instruction Address Register 5 */ |
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| 281 | #define WPIACNT0 0xFFE07080 /* Watchpoint Instruction Address Count Register 0 */ |
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| 282 | #define WPIACNT1 0xFFE07084 /* Watchpoint Instruction Address Count Register 1 */ |
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| 283 | #define WPIACNT2 0xFFE07088 /* Watchpoint Instruction Address Count Register 2 */ |
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| 284 | #define WPIACNT3 0xFFE0708C /* Watchpoint Instruction Address Count Register 3 */ |
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| 285 | #define WPIACNT4 0xFFE07090 /* Watchpoint Instruction Address Count Register 4 */ |
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| 286 | #define WPIACNT5 0xFFE07094 /* Watchpoint Instruction Address Count Register 5 */ |
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| 287 | #define WPDACTL 0xFFE07100 /* Watchpoint Data Address Control Register */ |
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| 288 | #define WPDA0 0xFFE07140 /* Watchpoint Data Address Register 0 */ |
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| 289 | #define WPDA1 0xFFE07144 /* Watchpoint Data Address Register 1 */ |
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| 290 | #define WPDACNT0 0xFFE07180 /* Watchpoint Data Address Count Value Register 0 */ |
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| 291 | #define WPDACNT1 0xFFE07184 /* Watchpoint Data Address Count Value Register 1 */ |
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| 292 | #define WPSTAT 0xFFE07200 /* Watchpoint Status Register */ |
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| 293 | |
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| 294 | /* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */ |
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| 295 | |
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| 296 | #define PFCTL 0xFFE08000 /* Performance Monitor Control Register */ |
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| 297 | #define PFCNTR0 0xFFE08100 /* Performance Monitor Counter Register 0 */ |
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| 298 | #define PFCNTR1 0xFFE08104 /* Performance Monitor Counter Register 1 */ |
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| 299 | |
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| 300 | |
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| 301 | /*********************************************************************************** */ |
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| 302 | /* Core MMR Register Bits */ |
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| 303 | /*********************************************************************************** */ |
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| 304 | |
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| 305 | /*************************************************** */ |
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| 306 | /* EVT registers (ILAT, IMASK, and IPEND). */ |
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| 307 | /*************************************************** */ |
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| 308 | |
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| 309 | /* ** Bit Positions */ |
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| 310 | #define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */ |
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| 311 | #define EVT_RST_P 0x00000001 /* Reset interrupt bit position */ |
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| 312 | #define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */ |
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| 313 | #define EVT_EVX_P 0x00000003 /* Exception bit position */ |
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| 314 | #define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */ |
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| 315 | #define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */ |
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| 316 | #define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */ |
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| 317 | #define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */ |
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| 318 | #define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */ |
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| 319 | #define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */ |
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| 320 | #define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */ |
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| 321 | #define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */ |
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| 322 | #define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */ |
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| 323 | #define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */ |
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| 324 | #define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */ |
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| 325 | #define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */ |
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| 326 | |
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| 327 | /* ** Masks */ |
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| 328 | #define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */ |
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| 329 | #define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */ |
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| 330 | #define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */ |
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| 331 | #define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */ |
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| 332 | #define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */ |
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| 333 | #define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */ |
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| 334 | #define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */ |
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| 335 | #define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */ |
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| 336 | #define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */ |
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| 337 | #define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */ |
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| 338 | #define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */ |
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| 339 | #define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */ |
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| 340 | #define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */ |
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| 341 | #define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */ |
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| 342 | #define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */ |
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| 343 | #define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */ |
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| 344 | |
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| 345 | /*************************************************** */ |
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| 346 | /* DMEM_CONTROL Register */ |
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| 347 | /*************************************************** */ |
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| 348 | /* ** Bit Positions */ |
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| 349 | #define ENDM_P 0x00 /* (doesn't really exist) Enable Data Memory L1 */ |
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| 350 | #define DMCTL_ENDM_P ENDM_P /* "" (older define) */ |
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| 351 | |
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| 352 | #define ENDCPLB_P 0x01 /* Enable DCPLBS */ |
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| 353 | #define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */ |
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| 354 | #if defined(__ADSPBF50x__) |
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| 355 | #define DMC_P 0x03 /* L1 Data Memory Configure bit */ |
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| 356 | #else |
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| 357 | #define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */ |
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| 358 | #define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */ |
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| 359 | #define DMCTL_DMC0_P DMC0_P /* "" (older define) */ |
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| 360 | #define DMCTL_DMC1_P DMC1_P /* "" (older define) */ |
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| 361 | #endif |
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| 362 | #define DCBS_P 0x04 /* L1 Data Cache Bank Select */ |
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| 363 | #define PORT_PREF0_P 0x12 /* DAG0 Port Preference */ |
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| 364 | #define PORT_PREF1_P 0x13 /* DAG1 Port Preference */ |
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| 365 | |
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| 366 | /* ** Masks */ |
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| 367 | #define ENDM 0x00000001 /* (doesn't really exist) Enable Data Memory L1 */ |
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| 368 | #define ENDCPLB 0x00000002 /* Enable DCPLB */ |
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| 369 | #define ASRAM_BSRAM 0x00000000 |
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| 370 | #define ACACHE_BSRAM 0x00000008 |
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| 371 | #define ACACHE_BCACHE 0x0000000C |
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| 372 | #define DCBS 0x00000010 /* L1 Data Cache Bank Select */ |
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| 373 | #define PORT_PREF0 0x00001000 /* DAG0 Port Preference */ |
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| 374 | #define PORT_PREF1 0x00002000 /* DAG1 Port Preference */ |
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| 375 | |
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| 376 | /* IMEM_CONTROL Register */ |
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| 377 | /* ** Bit Positions */ |
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| 378 | #define ENICPLB_P 0x01 /* Enable ICPLB */ |
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| 379 | #define IMCTL_ENICPLB_P 0x01 /* "" (older define) */ |
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| 380 | #define IMC_P 0x02 /* Enable */ |
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| 381 | #define IMCTL_IMC_P 0x02 /* Configure L1 code memory as cache (0=SRAM) */ |
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| 382 | #define ILOC0_P 0x03 /* Lock Way 0 */ |
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| 383 | #define ILOC1_P 0x04 /* Lock Way 1 */ |
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| 384 | #define ILOC2_P 0x05 /* Lock Way 2 */ |
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| 385 | #define ILOC3_P 0x06 /* Lock Way 3 */ |
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| 386 | #define LRUPRIORST_P 0x0D /* Least Recently Used Replacement Priority */ |
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| 387 | /* ** Masks */ |
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| 388 | #define ENICPLB 0x00000002 /* Enable ICPLB */ |
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| 389 | #define IMC 0x00000004 /* Configure L1 code memory as cache (0=SRAM) */ |
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| 390 | #define ILOC0 0x00000008 /* Lock Way 0 */ |
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| 391 | #define ILOC1 0x00000010 /* Lock Way 1 */ |
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| 392 | #define ILOC2 0x00000020 /* Lock Way 2 */ |
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| 393 | #define ILOC3 0x00000040 /* Lock Way 3 */ |
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| 394 | #define LRUPRIORST 0x00002000 /* Least Recently Used Replacement Priority */ |
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| 395 | |
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| 396 | /* TCNTL Masks */ |
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| 397 | #define TMPWR 0x00000001 /* Timer Low Power Control, 0=low power mode, 1=active state */ |
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| 398 | #define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */ |
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| 399 | #define TAUTORLD 0x00000004 /* Timer auto reload */ |
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| 400 | #define TINT 0x00000008 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */ |
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| 401 | |
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| 402 | /* TCNTL Bit Positions */ |
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| 403 | #define TMPWR_P 0x00000000 /* Timer Low Power Control, 0=low power mode, 1=active state */ |
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| 404 | #define TMREN_P 0x00000001 /* Timer enable, 0=disable, 1=enable */ |
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| 405 | #define TAUTORLD_P 0x00000002 /* Timer auto reload */ |
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| 406 | #define TINT_P 0x00000003 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */ |
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| 407 | |
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| 408 | /* DCPLB_DATA and ICPLB_DATA Registers - bit positions */ |
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| 409 | #define CPLB_VALID_P 0 /* 0=invalid entry, 1=valid entry */ |
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| 410 | #define CPLB_LOCK_P 1 /* 0=entry may be replaced, 1=entry locked */ |
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| 411 | #define CPLB_USER_RD_P 2 /* 0=no read access, 1=read access allowed (user mode) */ |
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| 412 | #define CPLB_PORTPRIO_P 9 /* 0=low priority port, 1= high priority port */ |
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| 413 | /*** ICPLB_DATA only */ |
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| 414 | #define CPLB_LRUPRIO_P 8 /* 0=can be replaced by any line, 1=priority for non-replacement */ |
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| 415 | /*** DCPLB_DATA only */ |
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| 416 | #define CPLB_USER_WR_P 3 /* 0=no write access, 0=write access allowed (user mode) */ |
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| 417 | #define CPLB_SUPV_WR_P 4 /* 0=no write access, 0=write access allowed (supervisor mode) */ |
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| 418 | #define CPLB_DIRTY_P 7 /* 1=dirty, 0=clean */ |
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| 419 | #define CPLB_L1_CHBL_P 12 /* 0=non-cacheable in L1, 1=cacheable in L1 */ |
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| 420 | #define CPLB_WT_P 14 /* 0=write-back, 1=write-through */ |
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| 421 | #define CPLB_L1_AOW_P 15 /* 0=do not allocate cache lines on write-through writes, */ |
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| 422 | /* 1= allocate cache lines on write-through writes. */ |
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| 423 | |
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| 424 | /* DCPLB_DATA and ICPLB_DATA Registers - Masks */ |
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| 425 | #define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ |
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| 426 | #define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */ |
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| 427 | #define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */ |
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| 428 | #define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ |
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| 429 | #define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ |
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| 430 | #define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ |
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| 431 | #define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ |
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| 432 | #define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ |
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| 433 | #define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */ |
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| 434 | /*** ICPLB_DATA only */ |
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| 435 | #define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */ |
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| 436 | /*** DCPLB_DATA only */ |
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| 437 | #define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */ |
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| 438 | #define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */ |
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| 439 | #define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ |
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| 440 | #define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */ |
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| 441 | /* 1= allocate cache lines on write-through writes. */ |
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| 442 | #define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ |
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| 443 | |
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| 444 | |
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| 445 | |
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| 446 | /* ITEST_COMMAND and DTEST_COMMAND Registers */ |
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| 447 | /*** Masks */ |
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| 448 | #define TEST_READ 0x00000000 /* Read Access */ |
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| 449 | #define TEST_WRITE 0x00000002 /* Write Access */ |
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| 450 | #define TEST_TAG 0x00000000 /* Access TAG */ |
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| 451 | #define TEST_DATA 0x00000004 /* Access DATA */ |
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| 452 | #define TEST_DW0 0x00000000 /* Select Double Word 0 */ |
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| 453 | #define TEST_DW1 0x00000008 /* Select Double Word 1 */ |
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| 454 | #define TEST_DW2 0x00000010 /* Select Double Word 2 */ |
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| 455 | #define TEST_DW3 0x00000018 /* Select Double Word 3 */ |
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| 456 | #define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */ |
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| 457 | #define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */ |
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| 458 | #define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */ |
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| 459 | #define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */ |
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| 460 | /* ensure macro params bracketed to avoid unexpected evaluations. (GA) MISRA Rule 19.10 */ |
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| 461 | #ifdef _MISRA_RULES |
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| 462 | #define TEST_SET(x) (((x) << 5) & 0x03E0u) /* Set Index 0->31 */ |
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| 463 | #else |
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| 464 | #define TEST_SET(x) (((x) << 5) & 0x03E0) /* Set Index 0->31 */ |
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| 465 | #endif /* _MISRA_RULES */ |
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| 466 | #define TEST_WAY0 0x00000000 /* Access Way0 */ |
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| 467 | #define TEST_WAY1 0x04000000 /* Access Way1 */ |
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| 468 | /*** ITEST_COMMAND only */ |
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| 469 | #define TEST_WAY2 0x08000000 /* Access Way2 */ |
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| 470 | #define TEST_WAY3 0x0C000000 /* Access Way3 */ |
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| 471 | /*** DTEST_COMMAND only */ |
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| 472 | #define TEST_BNKSELA 0x00000000 /* Access SuperBank A */ |
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| 473 | #define TEST_BNKSELB 0x00800000 /* Access SuperBank B */ |
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| 474 | |
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| 475 | #ifdef _MISRA_RULES |
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| 476 | #pragma diag(pop) |
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| 477 | #endif /* _MISRA_RULES */ |
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| 478 | |
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| 479 | #endif /* _DEF_LPBLACKFIN_H */ |
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