1 | /* |
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2 | * The authors hereby grant permission to use, copy, modify, distribute, |
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3 | * and license this software and its documentation for any purpose, provided |
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4 | * that existing copyright notices are retained in all copies and that this |
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5 | * notice is included verbatim in any distributions. No written agreement, |
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6 | * license, or royalty fee is required for any of the authorized uses. |
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7 | * Modifications to this software may be copyrighted by their authors |
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8 | * and need not follow the licensing terms described here, provided that |
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9 | * the new terms are clearly indicated on the first page of each file where |
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10 | * they apply. |
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11 | */ |
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12 | |
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13 | /************************************************************************ |
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14 | * |
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15 | * anomaly_macros_rtl.h : $Revision$ |
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16 | * |
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17 | * (c) Copyright 2005-2011 Analog Devices, Inc. All rights reserved. |
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18 | * |
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19 | * This file defines macros used within the run-time libraries to enable |
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20 | * certain anomaly workarounds for the appropriate chips and silicon |
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21 | * revisions. Certain macros are defined for silicon-revision none - this |
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22 | * is to ensure behaviour is unchanged from libraries supplied with |
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23 | * earlier tools versions, where a small number of anomaly workarounds |
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24 | * were applied in all library flavours. __FORCE_LEGACY_WORKAROUNDS__ |
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25 | * is defined in this case. |
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26 | * |
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27 | * This file defines macros for a subset of all anomalies that may impact |
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28 | * the run-time libraries. |
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29 | * |
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30 | ************************************************************************/ |
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31 | |
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32 | |
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33 | #ifdef _MISRA_RULES |
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34 | #pragma diag(push) |
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35 | #pragma diag(suppress:misra_rule_2_4:"Assembly code in comment used to illustrate anomalous behaviour") |
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36 | #endif /* _MISRA_RULES */ |
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37 | |
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38 | #if !defined(__SILICON_REVISION__) |
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39 | #define __FORCE_LEGACY_WORKAROUNDS__ |
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40 | #endif |
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41 | |
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42 | |
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43 | /* 050000245 - "False Hardware Error from an Access in the Shadow of a |
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44 | ** Conditional Branch" |
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45 | ** |
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46 | ** If a load accesses reserved or illegal memory on the opposite control |
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47 | ** flow of a conditional jump to the taken path, a false hardware error |
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48 | ** will occur. |
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49 | ** |
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50 | ** This macro is used by System Services/Device Drivers. |
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51 | ** |
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52 | ** This is for all Blackfin LP parts. |
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53 | */ |
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54 | #define WA_05000245 \ |
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55 | (defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)) |
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56 | |
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57 | |
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58 | /* 05-00-0229 - "SPI Slave Boot Mode Modifies Registers". |
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59 | * When the SPI slave boot completes, the final DMA IRQ is cleared |
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60 | * but the DMA5_CONFIG and SPI_CTL registers are not reset to their |
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61 | * default states. |
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62 | * |
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63 | * We work around this by resetting the registers to their default |
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64 | * values at the beginning of the CRT. The only issue would be when |
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65 | * users boot from flash and make use of the DMA or serial port. |
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66 | * In this case, users would need to modify the CRT. |
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67 | * |
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68 | * This problem impacts all revisions of ADSP-BF531/2/3/8/9 |
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69 | */ |
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70 | #define WA_05000229 \ |
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71 | (defined(__ADSPBLACKFIN__) && defined (__SILICON_REVISION__) && \ |
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72 | (defined(__ADSPBF531__) || defined(__ADSPBF532__) || \ |
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73 | defined(__ADSPBF533__) || defined(__ADSPBF538__) || \ |
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74 | defined(__ADSPBF539__))) |
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75 | |
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76 | |
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77 | /* 05-00-0283 - "A system MMR write is stalled indefinitely when killed in a |
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78 | * particular stage". |
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79 | * |
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80 | * Where an interrupt occurs killing a stalled system MMR write, and the ISR |
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81 | * executes an SSYNC, execution execution may stall indefinitely". |
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82 | * |
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83 | * The workaround is to execute a mispredicted jump over a dummy MMR read, |
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84 | * thus killing the read. Also to avoid a system MMR write in two slots |
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85 | * after a not predicted conditional jump. |
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86 | * |
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87 | * This problem impacts: |
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88 | * BF531/2/3 - < 0.6 |
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89 | * BF534/6/7 - < 0.3 |
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90 | * BF538/9 - < 0.4 |
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91 | * BF561/6 - < 0.5 |
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92 | * |
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93 | * Since this impacts 538/9 0.3 but not 534 0.3 (the libraries that they use) |
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94 | * we have to enable this workaround for the 534 0.3 libraries (see bottom |
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95 | * two lines). |
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96 | */ |
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97 | #define WA_05000283 \ |
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98 | (defined (__SILICON_REVISION__) && \ |
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99 | (((defined(__ADSPBF531__) || \ |
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100 | defined(__ADSPBF532__) || \ |
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101 | defined(__ADSPBF533__)) && \ |
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102 | (__SILICON_REVISION__ == 0xffff || \ |
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103 | __SILICON_REVISION__ < 0x6)) || \ |
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104 | ((defined(__ADSPBF534__) || \ |
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105 | defined(__ADSPBF536__) || \ |
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106 | defined(__ADSPBF537__)) && \ |
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107 | (__SILICON_REVISION__ == 0xffff || \ |
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108 | __SILICON_REVISION__ < 0x3)) || \ |
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109 | ((defined(__ADSPBF538__) || \ |
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110 | defined(__ADSPBF539__)) && \ |
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111 | (__SILICON_REVISION__ == 0xffff || \ |
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112 | __SILICON_REVISION__ < 0x4)) || \ |
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113 | (defined(__ADSPBF561__)) || \ |
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114 | (defined(__ADSPBF534__) && __SILICON_REVISION__ == 0x3 && \ |
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115 | defined(__ADI_LIB_BUILD__)))) |
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116 | |
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117 | |
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118 | /* 05-00-0311 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences |
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119 | ** |
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120 | ** Impacted: |
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121 | ** ADSP-BF53[123] - 0.0-0.5 (fixed in 0.6) |
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122 | ** |
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123 | ** Use by System Services/Device Drivers. |
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124 | */ |
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125 | #define WA_05000311 \ |
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126 | (defined(__ADSPBF533_FAMILY__) && \ |
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127 | (defined(__SILICON_REVISION__) && \ |
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128 | (__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff))) |
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129 | |
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130 | |
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131 | /* 05-00-0312 - Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers |
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132 | ** Are Interrupted |
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133 | ** |
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134 | ** Impacted: |
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135 | ** ADSP-BF53[123] - 0.0-0.5 (fixed in 0.6) |
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136 | ** ADSP-BF53[467] - all supported revisions |
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137 | ** ADSP-BF53[89] - 0.0-0.4 (fixed in 0.5) |
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138 | ** ADSP-BF561 - all supported revisions |
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139 | ** ADSP-BF54[24789] - 0.0 (fixed in 0.1) |
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140 | ** |
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141 | ** Used by VDK |
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142 | */ |
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143 | #define WA_05000312 \ |
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144 | (defined(__SILICON_REVISION__) && \ |
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145 | ((defined(__ADSPBF533_FAMILY__) && \ |
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146 | (__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)) || \ |
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147 | (defined(__ADSPBF537_FAMILY__)) || \ |
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148 | (defined(__ADSPBF538_FAMILY__) && \ |
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149 | (__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \ |
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150 | (defined(__ADSPBF548_FAMILY__) && \ |
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151 | (__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)) || \ |
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152 | (defined(__ADSPBF561_FAMILY__)))) |
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153 | |
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154 | |
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155 | /* 05-00-0323 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences |
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156 | ** |
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157 | ** Impacted: |
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158 | ** ADSP-BF561 - all supported revisions |
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159 | ** |
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160 | ** Use by System Services/Device Drivers. |
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161 | */ |
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162 | #define WA_05000323 \ |
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163 | (defined(__ADSPBF561__) && defined(__SILICON_REVISION__)) |
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164 | |
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165 | |
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166 | /* 05-00-0365 - DMAs that Go Urgent during Tight Core Writes to External |
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167 | ** Memory Are Blocked |
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168 | ** |
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169 | ** Impacted: |
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170 | ** ADSP-BF54[24789] - all supported revisions |
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171 | ** ADSP-BF54[24789]M - all supported revisions |
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172 | ** |
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173 | ** Use by System Services/Device Drivers. |
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174 | */ |
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175 | #define WA_05000365 \ |
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176 | ((defined(__ADSPBF548_FAMILY__) || defined(__ADSPBF548M_FAMILY__)) && \ |
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177 | defined(__SILICON_REVISION__)) |
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178 | |
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179 | |
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180 | /* 05-00-0371 - Possible RETS Register Corruption when Subroutine Is under |
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181 | ** 5 Cycles in Duration |
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182 | ** |
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183 | ** This problem impacts: |
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184 | ** BF531/2/3 - 0.0-0.5 (fixed in 0.6) |
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185 | ** BF534/6/7 - 0.0-0.3 |
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186 | ** BF538/9 - 0.0-0.4 (fixed in 0.5) |
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187 | ** BF561 - 0.0-0.5 |
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188 | ** BF542/4/7/8/9 - 0.0-0.1 (fixed in 0.2) |
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189 | ** BF523/5/7 - 0.0-0.1 (fixed in 0.2) |
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190 | ** |
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191 | */ |
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192 | #define WA_05000371 \ |
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193 | (defined(__SILICON_REVISION__) && \ |
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194 | ((defined(__ADSPBF533_FAMILY__) && \ |
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195 | (__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)) || \ |
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196 | (defined(__ADSPBF537_FAMILY__) && \ |
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197 | (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)) || \ |
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198 | (defined(__ADSPBF538_FAMILY__) && \ |
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199 | (__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \ |
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200 | (defined(__ADSPBF548_FAMILY__) && \ |
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201 | (__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \ |
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202 | (defined(__ADSPBF527_FAMILY__) && \ |
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203 | (__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \ |
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204 | (defined(__ADSPBF561__) || defined(__ADSPBF566__)))) |
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205 | |
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206 | |
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207 | /* 05-00-0412 - "TESTSET Instruction Causes Data Corruption with Writeback Data |
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208 | * Cache Enabled" |
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209 | * |
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210 | * If you use the testset instruction to operate on L2 memory and you have data |
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211 | * in external memory that is cached using WB mode, data in external memory |
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212 | * and/or L2 memory can be corrupted. |
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213 | * |
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214 | * Workaround: Either do not use writeback cache or precede the TESTSET |
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215 | * instruction with an SSYNC instruction. If preceding the TESTSET instruction |
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216 | * by an SSYNC instruction, do the following: |
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217 | * |
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218 | * CLI R0 |
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219 | * R1 = [P0] // perform a dummy read to make sure CPLB is installed |
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220 | * NOP |
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221 | * NOP |
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222 | * SSYNC |
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223 | * TESTSET (P0) |
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224 | * STI R0 |
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225 | * |
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226 | * This problem impacts: |
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227 | * BF561/6 - rev 0.0-0.5 |
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228 | * |
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229 | */ |
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230 | #define WA_05000412 \ |
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231 | (defined (__SILICON_REVISION__) && defined(__ADSPBF561__)) |
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232 | |
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233 | |
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234 | /* 05-00-0426 - Speculative Fetches of Indirect-Pointer Instructions Can |
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235 | ** Cause False Hardware Errors |
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236 | ** |
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237 | ** |
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238 | ** A false hardware error is generated if there is an indirect jump or |
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239 | ** call through a pointer which may point to reserved or illegal memory |
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240 | ** on the opposite control flow of a conditional jump to the taken path. |
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241 | ** This commonly occurs when using function pointers, which can be |
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242 | ** invalid (e.g., set to -1). |
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243 | ** |
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244 | ** Workaround: If instruction cache is on or the ICPLBs are enabled, |
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245 | ** this anomaly does not apply. If instruction cache is off and ICPLBs |
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246 | ** are disabled, the indirect pointer instructions must be 2 instructions |
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247 | ** away from the branch instruction, which can be implemented using NOPs: |
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248 | ** |
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249 | ** |
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250 | ** Impacted: |
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251 | ** All parts and revisions other than BF535 based parts. |
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252 | ** |
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253 | ** Used by System Services/Device Drivers. |
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254 | */ |
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255 | #define WA_05000426 \ |
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256 | (defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)) |
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257 | |
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258 | |
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259 | /* 05-00-0428 - "Lost/Corrupted Write to L2 Memory Following Speculative Read |
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260 | * by Core B from L2 Memory" |
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261 | * |
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262 | * This issue occurs only when the accesses are performed by core B of a BF561. |
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263 | * |
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264 | * When a write to internal L2 memory follows a speculative read from internal |
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265 | * L2 memory, the L2 write may be lost or corrupted. For this anomaly to occur, |
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266 | * the speculative read must be caused by a read in the shadow of a branch. The |
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267 | * accesses do not have to be consecutive accesses. In other words, the problem |
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268 | * can occur even if there are multiple instructions between the speculative |
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269 | * read and the write, as shown in the following example: |
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270 | * |
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271 | * R1 = 1; R2 = 1; |
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272 | * CC = R1 == R2; |
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273 | * IF CC JUMP X; // Always true... |
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274 | * R0 = [P0]; // If any of these three loads accesses L2 memory from Core |
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275 | * R1 = [P1]; // B, speculative execution in the pipeline causes the |
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276 | * R2 = [P2]; // anomaly trigger condition. |
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277 | * X: |
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278 | * ... // Any number of instructions... |
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279 | * [P0] = R0; // This write can be corrupted or lost. |
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280 | * |
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281 | * The issue does not occur if the speculative read access is caused by an |
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282 | * interrupt or exception. |
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283 | * |
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284 | * The workaround required depends upon the conditional branch instruction. |
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285 | * If the evaluated condition is true and the branch is predicted, then the |
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286 | * workaround is to ensure that the target instruction is not be a load |
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287 | * instruction, for example: |
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288 | * |
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289 | * IF CC JUMP X (BP); |
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290 | * ... |
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291 | * X: <load that might be from L2 memory> |
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292 | * |
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293 | * If the evaluated condition is false and the branch is not predicted, then |
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294 | * the workaround is to make sure that none of the three instructions that |
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295 | * are executed after the conditional JUMP are load instructions, for example: |
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296 | * |
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297 | * IF CC JUMP ...; |
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298 | * <load that might be from L2 memory> |
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299 | * <load that might be from L2 memory> |
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300 | * <load that might be from L2 memory> |
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301 | * |
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302 | * This problem impacts: |
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303 | * BF561 - rev 0.4,0.5 |
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304 | * |
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305 | */ |
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306 | #define WA_05000428 \ |
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307 | (defined(__SILICON_REVISION__) && \ |
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308 | defined(__ADSPBF561__) && \ |
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309 | ((__SILICON_REVISION__ == 0xffff) || \ |
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310 | (__SILICON_REVISION__ == 0x4) || \ |
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311 | (__SILICON_REVISION__ == 0x5))) |
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312 | |
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313 | |
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314 | /* 05-00-0443 - IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall |
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315 | ** |
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316 | ** Impacted: |
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317 | ** All parts and revisions other than BF535 based parts. |
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318 | ** |
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319 | ** Used by System Services/Device Drivers. |
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320 | */ |
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321 | #define WA_05000443 \ |
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322 | (defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)) |
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323 | |
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324 | |
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325 | /* 16-00-0005 - "Using L1 Instruction Cache with Parity Enabled is Unreliable." |
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326 | ** |
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327 | ** Using L1 instruction cache with parity enabled is unreliable and may cause |
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328 | ** unpredictable results. |
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329 | ** |
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330 | ** Impacted: |
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331 | ** BF6xx. |
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332 | */ |
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333 | #define WA_16000005 \ |
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334 | (defined(__ADSPBF60x__) && defined(__SILICON_REVISION__)) |
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335 | |
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336 | #ifdef _MISRA_RULES |
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337 | #pragma diag(pop) |
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338 | #endif /* _MISRA_RULES */ |
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339 | |
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