[444] | 1 | /* |
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| 2 | * The authors hereby grant permission to use, copy, modify, distribute, |
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| 3 | * and license this software and its documentation for any purpose, provided |
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| 4 | * that existing copyright notices are retained in all copies and that this |
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| 5 | * notice is included verbatim in any distributions. No written agreement, |
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| 6 | * license, or royalty fee is required for any of the authorized uses. |
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| 7 | * Modifications to this software may be copyrighted by their authors |
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| 8 | * and need not follow the licensing terms described here, provided that |
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| 9 | * the new terms are clearly indicated on the first page of each file where |
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| 10 | * they apply. |
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| 11 | */ |
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| 12 | |
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| 13 | #pragma once |
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| 14 | #ifndef __NO_BUILTIN |
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| 15 | #pragma system_header /* exception.h */ |
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| 16 | #endif |
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| 17 | /************************************************************************ |
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| 18 | * |
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| 19 | * exception.h |
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| 20 | * |
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| 21 | * (c) Copyright 2001-2008 Analog Devices, Inc. All rights reserved. |
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| 22 | * |
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| 23 | ************************************************************************/ |
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| 24 | |
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| 25 | #ifndef _EXCEPTION_H |
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| 26 | #define _EXCEPTION_H |
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| 27 | |
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| 28 | #ifdef _MISRA_RULES |
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| 29 | #pragma diag(push) |
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| 30 | #pragma diag(suppress:misra_rule_5_6) |
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| 31 | #pragma diag(suppress:misra_rule_5_7) |
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| 32 | #pragma diag(suppress:misra_rule_6_3) |
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| 33 | #pragma diag(suppress:misra_rule_19_4) |
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| 34 | #pragma diag(suppress:misra_rule_19_7) |
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| 35 | #pragma diag(suppress:misra_rule_19_10) |
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| 36 | #pragma diag(suppress:misra_rule_19_13) |
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| 37 | #endif /* _MISRA_RULES */ |
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| 38 | |
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| 39 | |
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| 40 | |
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| 41 | /* |
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| 42 | ** Definitions for user-friendly interrupt handling. |
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| 43 | */ |
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| 44 | |
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| 45 | /* |
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| 46 | ** Memory-Mapped Registers (MMRs) - these record what causes address |
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| 47 | ** exceptions. |
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| 48 | */ |
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| 49 | |
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| 50 | #define EX_DATA_FAULT_STATUS 0xFFE00008 |
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| 51 | #define EX_DATA_FAULT_ADDR 0xFFE0000C |
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| 52 | #define EX_CODE_FAULT_STATUS 0xFFE01008 |
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| 53 | #define EX_CODE_FAULT_ADDR 0xFFE0100C |
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| 54 | |
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| 55 | /* |
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| 56 | ** Event Vector Table |
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| 57 | */ |
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| 58 | |
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| 59 | #define EX_EVENT_VECTOR_TABLE 0xFFE02000 |
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| 60 | |
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| 61 | /* |
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| 62 | ** Meaning of the various bits in EXCAUSE field in SEQSTAT register. |
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| 63 | */ |
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| 64 | |
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| 65 | #define EX_BITS 0x3F /* All EXCAUSE bits */ |
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| 66 | #define EX_TYPE 0x30 /* The bits which define the type */ |
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| 67 | #define EX_DEBUG 0x10 /* If set, is a debug exception type */ |
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| 68 | #define EX_SYS 0x20 /* If set, is a system exception type */ |
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| 69 | /* If neither set, is from EXCPT instr */ |
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| 70 | |
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| 71 | #define EX_IS_DEBUG_EXCEPTION(E) (((E)&EX_TYPE)==EX_DEBUG) |
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| 72 | #define EX_IS_SYSTEM_EXCEPTION(E) (((E)&EX_TYPE)==EX_SYS) |
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| 73 | #define EX_IS_USER_EXCEPTION(E) (((E)&EX_TYPE)==0) |
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| 74 | |
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| 75 | /* |
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| 76 | ** Service exceptions continue from the instruction after the one |
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| 77 | ** that raised the exception. |
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| 78 | ** Error exceptions restart the instruction that raised the exception. |
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| 79 | */ |
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| 80 | |
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| 81 | #define EX_IS_SERVICE_EXCEPTION(E) (!EX_IS_SYSTEM_EXCEPTION(E)) |
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| 82 | #define EX_IS_ERROR_EXCEPTION(E) (EX_IS_SYSTEM_EXCEPTION(E)) |
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| 83 | |
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| 84 | #define EX_DB_SINGLE_STEP 0x10 /* Processor is single-stepping */ |
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| 85 | #define EX_DB_EMTRCOVRFLW 0x11 /* Emulation Trace buffer overflowed */ |
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| 86 | |
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| 87 | #define EX_SYS_UNDEFINSTR 0x21 /* Undefined instruction */ |
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| 88 | #define EX_SYS_ILLINSTRC 0x22 /* Illegal instruction combination */ |
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| 89 | #define EX_SYS_DCPLBPROT 0x23 /* Data CPLB Protection violation */ |
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| 90 | #define EX_SYS_DALIGN 0x24 /* Data access misaligned address violation */ |
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| 91 | #define EX_SYS_UNRECEVT 0x25 /* Unrecoverable event */ |
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| 92 | #define EX_SYS_DCPLBMISS 0x26 /* Data access CPLB Miss */ |
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| 93 | #define EX_SYS_DCPLBMHIT 0x27 /* Data access CPLB Multiple Hits */ |
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| 94 | #define EX_SYS_EMWATCHPT 0x28 /* Emulation watch point match */ |
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| 95 | #define EX_SYS_CACCESSEX 0x29 /* Code fetch access exception */ |
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| 96 | #define EX_SYS_CALIGN 0x2A /* Attempted misaligned instr cache fetch */ |
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| 97 | #define EX_SYS_CCPLBPROT 0x2B /* Code fetch CPLB Protection */ |
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| 98 | #define EX_SYS_CCPLBMISS 0x2C /* CPLB miss on an instruction fetch */ |
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| 99 | #define EX_SYS_CCPLBMHIT 0x2D /* Code fetch CPLB Multiple Hits */ |
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| 100 | #define EX_SYS_ILLUSESUP 0x2E /* Illegal use of Supervisor Resource */ |
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| 101 | |
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| 102 | /* |
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| 103 | ** Meaning of the various bits in HWERRCAUSE in SEQSTAT |
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| 104 | */ |
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| 105 | |
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| 106 | #define EX_HWBITS (0x1F<<14) /* bits 18:14 */ |
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| 107 | |
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| 108 | #if !defined(__ADSPLPBLACKFIN__) |
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| 109 | #define EX_HW_NOMEM1 (0x16<<14) |
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| 110 | #define EX_HW_NOMEM2 (0x17<<14) |
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| 111 | #else |
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| 112 | #define EX_HW_SYSMMR (0x02<<14) |
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| 113 | #define EX_HW_EXTMEM (0x03<<14) |
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| 114 | #endif |
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| 115 | #define EX_HW_DMAHIT (0x01<<14) |
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| 116 | #define EX_HW_PERFMON (0x12<<14) |
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| 117 | #define EX_HW_RAISE (0x18<<14) |
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| 118 | |
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| 119 | /* |
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| 120 | ** Meaning of the bits in DATA_FAULT_STATUS and CODE_FAULT_STATUS |
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| 121 | */ |
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| 122 | |
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| 123 | #define EX_DATA_FAULT_ILLADDR (1<<19) /* non-existent memory */ |
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| 124 | #define EX_DATA_FAULT_DAG (1<<18) /* 0=>DAG0, 1=>DAG1 */ |
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| 125 | #define EX_DATA_FAULT_USERSUPV (1<<17) /* 0=>user mode, 1=> supervisor */ |
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| 126 | #define EX_DATA_FAULT_READWRITE (1<<16) /* 0=>read, 1=>write */ |
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| 127 | #define EX_DATA_FAULT_CPLB 0xFFFF /* 0=>CPLB0, 1=>CPLB1, etc */ |
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| 128 | |
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| 129 | #define EX_CODE_FAULT_ILLADDR (1<<19) /* non-existent memory */ |
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| 130 | #define EX_CODE_FAULT_USERSUPV (1<<17) /* 0=>user mode, 1=> supervisor */ |
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| 131 | #define EX_CODE_FAULT_CPLB 0xFFFF /* 0=>CPLB0, 1=>CPLB1, etc */ |
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| 132 | |
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| 133 | /* |
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| 134 | ** The kinds of interrupt that can occur. These are also the |
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| 135 | ** indices into the Event Vector Table. |
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| 136 | */ |
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| 137 | |
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| 138 | #ifdef __cplusplus |
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| 139 | extern "C" { |
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| 140 | #endif |
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| 141 | |
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| 142 | typedef enum { |
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| 143 | ik_err=-1, |
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| 144 | ik_emulation, |
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| 145 | ik_reset, |
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| 146 | ik_nmi, |
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| 147 | ik_exception, |
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| 148 | ik_global_int_enable, |
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| 149 | ik_hardware_err, |
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| 150 | ik_timer, |
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| 151 | ik_ivg7, |
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| 152 | ik_ivg8, |
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| 153 | ik_ivg9, |
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| 154 | ik_ivg10, |
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| 155 | ik_ivg11, |
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| 156 | ik_ivg12, |
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| 157 | ik_ivg13, |
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| 158 | ik_ivg14, |
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| 159 | ik_ivg15, |
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| 160 | num_interrupt_kind |
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| 161 | } interrupt_kind; |
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| 162 | |
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| 163 | /* |
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| 164 | ** Structure for recording details of an exception or interrupt |
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| 165 | ** that has occurred. |
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| 166 | */ |
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| 167 | |
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| 168 | typedef struct { |
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| 169 | interrupt_kind kind; /* whether interrupt, exception, etc. */ |
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| 170 | int value; /* interrupt number, exception type, etc. */ |
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| 171 | void *pc; /* PC at point where exception occurred */ |
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| 172 | void *addr; /* if an address faulted, which one. */ |
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| 173 | unsigned status; /* if an address faulted, why. */ |
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| 174 | } interrupt_info; |
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| 175 | |
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| 176 | /* |
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| 177 | ** Macro for defining an interrupt routine |
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| 178 | */ |
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| 179 | |
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| 180 | typedef void (*ex_handler_fn)(); |
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| 181 | |
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| 182 | #define EX_HANDLER(KIND,NAME) \ |
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| 183 | _Pragma(#KIND) \ |
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| 184 | void NAME (void) |
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| 185 | |
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| 186 | #define EX_HANDLER_PROTO(KIND, NAME) EX_HANDLER(KIND, NAME) |
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| 187 | |
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| 188 | #define EX_INTERRUPT_HANDLER(NAME) EX_HANDLER(interrupt,NAME) |
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| 189 | #define EX_EXCEPTION_HANDLER(NAME) EX_HANDLER(exception,NAME) |
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| 190 | #define EX_NMI_HANDLER(NAME) EX_HANDLER(nmi,NAME) |
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| 191 | #define EX_REENTRANT_HANDLER(NAME) \ |
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| 192 | _Pragma("interrupt_reentrant") \ |
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| 193 | EX_HANDLER(interrupt,NAME) |
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| 194 | |
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| 195 | /* |
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| 196 | ** A convenience function for setting up the interrupt_info contents. |
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| 197 | ** Must be called from immediately with the interrupt handler. |
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| 198 | */ |
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| 199 | |
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| 200 | void get_interrupt_info(interrupt_kind int_kind, interrupt_info *int_info); |
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| 201 | |
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| 202 | /* |
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| 203 | ** Diagnostics function for reporting unexpected events. |
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| 204 | */ |
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| 205 | |
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| 206 | void _ex_report_event(interrupt_info *int_info); |
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| 207 | |
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| 208 | /* |
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| 209 | ** Register an interrupt handler within the EVT. |
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| 210 | ** Return previous value if there was one. |
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| 211 | */ |
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| 212 | ex_handler_fn register_handler(interrupt_kind int_kind, ex_handler_fn handler); |
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| 213 | |
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| 214 | /* |
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| 215 | ** Some magic values for registering default and null handlers. |
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| 216 | */ |
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| 217 | |
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| 218 | #define EX_INT_DEFAULT ((ex_handler_fn)-1) |
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| 219 | #define EX_INT_IGNORE ((ex_handler_fn)0) |
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| 220 | |
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| 221 | /* |
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| 222 | ** Extended function to register an interrupt handler within the EVT. |
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| 223 | ** Returns the old handler. |
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| 224 | ** |
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| 225 | ** If enabled == EX_INT_ALWAYS_ENABLE, install fn (if fn != EX_INT_IGNORE |
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| 226 | ** and fn != EX_INT_DISABLE), and then enable the interrupt in IMASK then |
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| 227 | ** return |
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| 228 | ** |
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| 229 | ** If fn == EX_INT_IGNORE, disable the interrupt |
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| 230 | ** If fn == EX_INT_DEFAULT, delete the handler entry in the EVT and disable |
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| 231 | ** the interrupt in IMASK |
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| 232 | ** Otherwise, install the new interrupt handler. Then, |
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| 233 | ** If enabled == EX_INT_DISABLE, disable the interrupt in IMASK |
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| 234 | ** If enabled == EX_INT_ENABLE, enable the interrupt in IMASK |
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| 235 | ** otherwise leave the interrupt status alone. |
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| 236 | */ |
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| 237 | ex_handler_fn register_handler_ex(interrupt_kind kind, ex_handler_fn fn, |
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| 238 | int enable); |
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| 239 | |
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| 240 | /* Constants for the enabled parameter of register_handler_ex */ |
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| 241 | #define EX_INT_DISABLE 0 |
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| 242 | #define EX_INT_ENABLE 1 |
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| 243 | #define EX_INT_KEEP_IMASK -1 |
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| 244 | #define EX_INT_ALWAYS_ENABLE 2 |
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| 245 | |
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| 246 | /* |
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| 247 | ** Allow the user to raise exceptions from C. |
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| 248 | */ |
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| 249 | |
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| 250 | int raise_interrupt(interrupt_kind kind, int which, |
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| 251 | int cmd, int arg1, int arg2); |
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| 252 | |
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| 253 | #ifdef __cplusplus |
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| 254 | } /* extern "C" */ |
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| 255 | #endif |
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| 256 | |
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| 257 | #ifdef _MISRA_RULES |
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| 258 | #pragma diag(pop) |
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| 259 | #endif /* _MISRA_RULES */ |
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| 260 | |
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| 261 | #endif /* _EXCEPTION_H */ |
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