1 | /* |
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2 | * The authors hereby grant permission to use, copy, modify, distribute, |
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3 | * and license this software and its documentation for any purpose, provided |
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4 | * that existing copyright notices are retained in all copies and that this |
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5 | * notice is included verbatim in any distributions. No written agreement, |
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6 | * license, or royalty fee is required for any of the authorized uses. |
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7 | * Modifications to this software may be copyrighted by their authors |
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8 | * and need not follow the licensing terms described here, provided that |
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9 | * the new terms are clearly indicated on the first page of each file where |
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10 | * they apply. |
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11 | */ |
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12 | |
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13 | /************************************************************************ |
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14 | * |
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15 | * pll.h |
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16 | * |
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17 | * (c) Copyright 2003-2004 Analog Devices, Inc. All rights reserved. |
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18 | * |
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19 | ************************************************************************/ |
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20 | |
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21 | #ifndef __ASSEMBLER__ |
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22 | #pragma once |
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23 | #pragma system_header |
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24 | #endif |
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25 | |
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26 | #ifndef _PLL_H |
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27 | #define _PLL_H |
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28 | |
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29 | #ifdef _MISRA_RULES |
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30 | #pragma diag(push) |
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31 | #pragma diag(suppress:misra_rule_6_3) |
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32 | #endif /* _MISRA_RULES */ |
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33 | |
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34 | #define NO_STARTUP_SET 0 |
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35 | #define MAX_IN_STARTUP 1 |
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36 | |
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37 | #ifndef __ASSEMBLER__ |
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38 | |
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39 | enum clkctrl_t { |
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40 | /* no modification of PLL rates in CRT startup - default */ |
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41 | no_startup_set=NO_STARTUP_SET, |
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42 | |
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43 | /* CRT startup sets PLL rates to suitable maximum values */ |
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44 | max_in_startup=MAX_IN_STARTUP |
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45 | }; |
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46 | |
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47 | /* |
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48 | ** Define __clk_ctrl to 1 to cause startup to set PLL rates for maximum |
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49 | ** speed performance rates. The default version defined in the runtime- |
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50 | ** libraries defines __clk_ctrl to 0 which disables the feature. |
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51 | */ |
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52 | extern enum clkctrl_t __clk_ctrl; |
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53 | |
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54 | #ifdef __cplusplus |
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55 | extern "C" { |
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56 | #endif |
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57 | |
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58 | #if defined(__ADSPLPBLACKFIN__) |
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59 | |
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60 | /* Sets SSEL and CSEL bits in PLL_DIV to passed values. |
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61 | ** Returns -1 on failure. |
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62 | */ |
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63 | int pll_set_system_clocks(int _csel, int _ssel); |
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64 | |
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65 | /* |
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66 | ** Sets MSEL and DF bits in PLL_CTL and LOCKCNT in PLL_LOCKCNT. |
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67 | ** Returns -1 on failure. |
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68 | */ |
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69 | int pll_set_system_vco(int _msel, int _df, int _lockcnt); |
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70 | |
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71 | #endif /* __ADSPLPBLACKFIN__ */ |
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72 | |
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73 | #ifdef __cplusplus |
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74 | } |
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75 | #endif |
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76 | |
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77 | #endif /* __ASSEMBLER__ */ |
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78 | |
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79 | #ifdef _MISRA_RULES |
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80 | #pragma diag(pop) |
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81 | #endif /* _MISRA_RULES */ |
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82 | |
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83 | #endif /* _PLL_H */ |
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84 | |
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