1 | /* The interrupt table. |
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2 | * |
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3 | * Copyright (c) 2006 CodeSourcery Inc |
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4 | * |
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5 | * The authors hereby grant permission to use, copy, modify, distribute, |
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6 | * and license this software and its documentation for any purpose, provided |
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7 | * that existing copyright notices are retained in all copies and that this |
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8 | * notice is included verbatim in any distributions. No written agreement, |
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9 | * license, or royalty fee is required for any of the authorized uses. |
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10 | * Modifications to this software may be copyrighted by their authors |
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11 | * and need not follow the licensing terms described here, provided that |
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12 | * the new terms are clearly indicated on the first page of each file where |
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13 | * they apply. |
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14 | */ |
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15 | |
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16 | .macro SLOT,n,prefix=,suffix= |
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17 | .long __\prefix\n\suffix |
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18 | .endm |
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19 | |
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20 | .macro ISR n |
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21 | SLOT \n,interrupt, |
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22 | .endm |
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23 | |
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24 | .macro TRAP n |
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25 | SLOT \n,trap, |
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26 | .endm |
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27 | |
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28 | .macro FP n |
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29 | SLOT \n,fp_, |
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30 | .endm |
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31 | |
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32 | .macro UNIMP_OPCODE n |
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33 | SLOT \n,unimplemented_,_opcode |
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34 | .endm |
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35 | |
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36 | .macro BREAKPOINT_DEBUG n |
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37 | SLOT \n,,_breakpoint_debug_interrupt |
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38 | .endm |
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39 | |
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40 | .section .interrupt_vector,"a" |
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41 | |
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42 | .globl __interrupt_vector |
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43 | __interrupt_vector: |
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44 | |
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45 | .long __stack /* 0 */ |
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46 | .long __reset /* 1 */ |
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47 | .long __access_error /* 2 */ |
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48 | .long __address_error /* 3 */ |
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49 | .long __illegal_instruction /* 4 */ |
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50 | .long __divide_by_zero /* 5 */ |
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51 | ISR 6 |
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52 | ISR 7 |
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53 | .long __privilege_violation /* 8 */ |
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54 | .long __trace /* 9 */ |
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55 | UNIMP_OPCODE line_a /* 10 */ |
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56 | UNIMP_OPCODE line_f /* 11 */ |
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57 | BREAKPOINT_DEBUG non_pc /* 12 */ |
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58 | BREAKPOINT_DEBUG pc /* 13 */ |
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59 | .long __format_error /* 14 */ |
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60 | .irp N,15,16,17,18,19,20,21,22,23 |
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61 | ISR \N /* [15,24) */ |
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62 | .endr |
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63 | .long __spurious_interrupt /* 24 */ |
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64 | .irp N,25,26,27,28,29,30,31 |
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65 | ISR \N /* [25,32) */ |
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66 | .endr |
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67 | .irp N,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
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68 | TRAP \N /* [32,48) */ |
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69 | .endr |
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70 | FP branch_unordered /* 48 */ |
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71 | FP inexact_result /* 49 */ |
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72 | FP divide_by_zero /* 50 */ |
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73 | FP underflow /* 51 */ |
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74 | FP operand_error /* 52 */ |
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75 | FP overflow /* 53 */ |
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76 | FP input_not_a_number /* 54 */ |
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77 | FP input_denormalized_number /* 55 */ |
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78 | .irp N,56,57,58,59,60 |
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79 | ISR \N /* [56,61) */ |
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80 | .endr |
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81 | .long __unsupported_instruction /* 61 */ |
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82 | .irp N,62,63 |
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83 | ISR \N /* [62,64) */ |
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84 | .endr |
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85 | .irp N,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79 |
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86 | ISR \N /* [64,80) */ |
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87 | .endr |
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88 | .irp N,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95 |
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89 | ISR \N /* [80,96) */ |
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90 | .endr |
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91 | .irp N,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111 |
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92 | ISR \N /* [96,112) */ |
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93 | .endr |
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94 | .irp N,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127 |
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95 | ISR \N /* [112,128) */ |
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96 | .endr |
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97 | .irp N,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143 |
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98 | ISR \N /* [128,144) */ |
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99 | .endr |
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100 | .irp N,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159 |
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101 | ISR \N /* [144,160) */ |
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102 | .endr |
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103 | .irp N,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 |
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104 | ISR \N /* [160,176) */ |
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105 | .endr |
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106 | .irp N,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191 |
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107 | ISR \N /* [176,192) */ |
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108 | .endr |
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109 | .irp N,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207 |
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110 | ISR \N /* [192,208) */ |
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111 | .endr |
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112 | .irp N,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223 |
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113 | ISR \N /* [208,224) */ |
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114 | .endr |
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115 | .irp N,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239 |
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116 | ISR \N /* [224,240) */ |
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117 | .endr |
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118 | .irp N,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255 |
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119 | ISR \N /* [240,256) */ |
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120 | .endr |
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