[444] | 1 | /* caches-asm.S -- cache manipulation for OpenRISC 1000. |
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| 2 | * |
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| 3 | * Copyright (c) 2011, 2014 Authors |
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| 4 | * |
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| 5 | * Contributor Julius Baxter <juliusbaxter@gmail.com> |
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| 6 | * Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de> |
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| 7 | * |
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| 8 | * The authors hereby grant permission to use, copy, modify, distribute, |
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| 9 | * and license this software and its documentation for any purpose, provided |
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| 10 | * that existing copyright notices are retained in all copies and that this |
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| 11 | * notice is included verbatim in any distributions. No written agreement, |
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| 12 | * license, or royalty fee is required for any of the authorized uses. |
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| 13 | * Modifications to this software may be copyrighted by their authors |
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| 14 | * and need not follow the licensing terms described here, provided that |
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| 15 | * the new terms are clearly indicated on the first page of each file where |
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| 16 | * they apply. |
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| 17 | */ |
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| 18 | |
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| 19 | #include "include/or1k-asm.h" |
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| 20 | #include "include/or1k-sprs.h" |
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| 21 | |
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| 22 | /* -------------------------------------------------------------------------- */ |
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| 23 | /*!Function used at reset to clear and enable all caches |
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| 24 | */ |
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| 25 | /* -------------------------------------------------------------------------- */ |
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| 26 | .global _or1k_cache_init |
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| 27 | .type _or1k_cache_init,@function |
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| 28 | |
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| 29 | _or1k_cache_init: |
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| 30 | /* Instruction cache enable */ |
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| 31 | /* Check if IC present and skip enabling otherwise */ |
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| 32 | l.mfspr r3,r0,OR1K_SPR_SYS_UPR_ADDR |
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| 33 | l.andi r4,r3,OR1K_SPR_SYS_UPR_ICP_MASK |
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| 34 | l.sfeq r4,r0 |
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| 35 | OR1K_DELAYED_NOP(OR1K_INST(l.bf .Lnoic)) |
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| 36 | |
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| 37 | /* Disable IC */ |
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| 38 | l.mfspr r6,r0,OR1K_SPR_SYS_SR_ADDR |
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| 39 | l.addi r5,r0,-1 |
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| 40 | l.xori r5,r5,OR1K_SPR_SYS_SR_ICE_MASK |
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| 41 | l.and r5,r6,r5 |
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| 42 | l.mtspr r0,r5,OR1K_SPR_SYS_SR_ADDR |
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| 43 | |
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| 44 | /* Establish cache block size |
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| 45 | If BS=0, 16; |
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| 46 | If BS=1, 32; |
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| 47 | r14 contain block size |
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| 48 | */ |
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| 49 | l.mfspr r3,r0,OR1K_SPR_SYS_ICCFGR_ADDR |
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| 50 | l.andi r4,r3,OR1K_SPR_SYS_ICCFGR_CBS_MASK |
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| 51 | l.srli r7,r4,7 |
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| 52 | l.ori r8,r0,16 |
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| 53 | l.sll r14,r8,r7 |
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| 54 | |
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| 55 | /* Establish number of cache sets |
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| 56 | r13 contains number of cache sets |
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| 57 | r7 contains log(# of cache sets) |
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| 58 | */ |
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| 59 | l.andi r4,r3,OR1K_SPR_SYS_ICCFGR_NCS_MASK |
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| 60 | l.srli r7,r4,3 |
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| 61 | l.ori r8,r0,1 |
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| 62 | l.sll r13,r8,r7 |
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| 63 | |
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| 64 | /* Invalidate IC */ |
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| 65 | l.addi r6,r0,0 |
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| 66 | l.sll r5,r14,r7 |
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| 67 | |
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| 68 | .Linvi: l.mtspr r0,r6,OR1K_SPR_ICACHE_ICBIR_ADDR |
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| 69 | l.sfne r6,r5 |
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| 70 | OR1K_DELAYED( |
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| 71 | OR1K_INST(l.add r6,r6,r14), |
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| 72 | OR1K_INST(l.bf .Linvi) |
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| 73 | ) |
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| 74 | |
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| 75 | /* Enable IC */ |
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| 76 | l.mfspr r6,r0,OR1K_SPR_SYS_SR_ADDR |
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| 77 | l.ori r6,r6,OR1K_SPR_SYS_SR_ICE_MASK |
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| 78 | l.mtspr r0,r6,OR1K_SPR_SYS_SR_ADDR |
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| 79 | l.nop |
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| 80 | l.nop |
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| 81 | l.nop |
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| 82 | l.nop |
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| 83 | l.nop |
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| 84 | l.nop |
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| 85 | l.nop |
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| 86 | l.nop |
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| 87 | |
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| 88 | /* Data cache enable */ |
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| 89 | /* Check if DC present and skip enabling otherwise */ |
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| 90 | .Lnoic: l.mfspr r3,r0,OR1K_SPR_SYS_UPR_ADDR |
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| 91 | l.andi r4,r3,OR1K_SPR_SYS_UPR_DCP_MASK |
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| 92 | l.sfeq r4,r0 |
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| 93 | OR1K_DELAYED_NOP(OR1K_INST(l.bf .Lnodc)) |
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| 94 | /* Disable DC */ |
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| 95 | l.mfspr r6,r0,OR1K_SPR_SYS_SR_ADDR |
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| 96 | l.addi r5,r0,-1 |
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| 97 | l.xori r5,r5,OR1K_SPR_SYS_SR_DCE_MASK |
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| 98 | l.and r5,r6,r5 |
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| 99 | l.mtspr r0,r5,OR1K_SPR_SYS_SR_ADDR |
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| 100 | /* Establish cache block size |
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| 101 | If BS=0, 16; |
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| 102 | If BS=1, 32; |
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| 103 | r14 contain block size */ |
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| 104 | l.mfspr r3,r0,OR1K_SPR_SYS_DCCFGR_ADDR |
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| 105 | l.andi r4,r3,OR1K_SPR_SYS_DCCFGR_CBS_MASK |
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| 106 | l.srli r7,r4,7 |
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| 107 | l.ori r8,r0,16 |
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| 108 | l.sll r14,r8,r7 |
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| 109 | /* Establish number of cache sets |
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| 110 | r13 contains number of cache sets |
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| 111 | r7 contains log(# of cache sets) */ |
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| 112 | l.andi r4,r3,OR1K_SPR_SYS_ICCFGR_NCS_MASK |
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| 113 | l.srli r7,r4,3 |
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| 114 | l.ori r8,r0,1 |
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| 115 | l.sll r13,r8,r7 |
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| 116 | /* Invalidate DC */ |
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| 117 | l.addi r6,r0,0 |
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| 118 | l.sll r5,r14,r7 |
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| 119 | |
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| 120 | .Linvd: l.mtspr r0,r6,OR1K_SPR_DCACHE_DCBIR_ADDR |
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| 121 | l.sfne r6,r5 |
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| 122 | OR1K_DELAYED( |
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| 123 | OR1K_INST(l.add r6,r6,r14), |
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| 124 | OR1K_INST(l.bf .Linvd) |
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| 125 | ) |
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| 126 | /* Enable DC */ |
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| 127 | l.mfspr r6,r0,OR1K_SPR_SYS_SR_ADDR |
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| 128 | l.ori r6,r6,OR1K_SPR_SYS_SR_DCE_MASK |
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| 129 | l.mtspr r0,r6,OR1K_SPR_SYS_SR_ADDR |
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| 130 | |
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| 131 | .Lnodc: |
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| 132 | /* Return */ |
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| 133 | OR1K_DELAYED_NOP(OR1K_INST(l.jr r9)) |
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| 134 | |
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| 135 | /* -------------------------------------------------------------------------- */ |
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| 136 | /*!Function to enable instruction cache |
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| 137 | */ |
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| 138 | /* -------------------------------------------------------------------------- */ |
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| 139 | |
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| 140 | .global or1k_icache_enable |
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| 141 | .type or1k_icache_enable,@function |
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| 142 | |
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| 143 | or1k_icache_enable: |
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| 144 | /* Enable IC */ |
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| 145 | l.mfspr r13,r0,OR1K_SPR_SYS_SR_ADDR |
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| 146 | l.ori r13,r13,OR1K_SPR_SYS_SR_ICE_MASK |
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| 147 | l.mtspr r0,r13,OR1K_SPR_SYS_SR_ADDR |
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| 148 | l.nop |
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| 149 | l.nop |
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| 150 | l.nop |
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| 151 | l.nop |
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| 152 | l.nop |
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| 153 | OR1K_DELAYED_NOP(OR1K_INST(l.jr r9)) |
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| 154 | |
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| 155 | /* -------------------------------------------------------------------------- */ |
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| 156 | /*!Function to disable instruction cache |
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| 157 | */ |
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| 158 | /* -------------------------------------------------------------------------- */ |
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| 159 | .global or1k_icache_disable |
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| 160 | .type or1k_icache_disable,@function |
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| 161 | |
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| 162 | or1k_icache_disable: |
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| 163 | /* Disable IC */ |
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| 164 | l.mfspr r13,r0,OR1K_SPR_SYS_SR_ADDR |
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| 165 | l.addi r12,r0,-1 |
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| 166 | l.xori r12,r12,OR1K_SPR_SYS_SR_ICE_MASK |
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| 167 | l.and r12,r13,r12 |
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| 168 | l.mtspr r0,r12,OR1K_SPR_SYS_SR_ADDR |
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| 169 | OR1K_DELAYED_NOP(OR1K_INST(l.jr r9)) |
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| 170 | |
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| 171 | /* -------------------------------------------------------------------------- */ |
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| 172 | /*!Function to flush address of instruction cache |
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| 173 | */ |
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| 174 | /* -------------------------------------------------------------------------- */ |
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| 175 | .global or1k_icache_flush |
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| 176 | .type or1k_icache_flush,@function |
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| 177 | |
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| 178 | or1k_icache_flush: |
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| 179 | OR1K_DELAYED( |
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| 180 | OR1K_INST(l.mtspr r0,r3,OR1K_SPR_ICACHE_ICBIR_ADDR), |
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| 181 | /* Push r3 into IC invalidate reg */ |
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| 182 | OR1K_INST(l.jr r9) |
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| 183 | ) |
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| 184 | |
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| 185 | |
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| 186 | /* -------------------------------------------------------------------------- */ |
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| 187 | /*!Function to enable data cache |
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| 188 | */ |
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| 189 | /* -------------------------------------------------------------------------- */ |
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| 190 | .global or1k_dcache_enable |
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| 191 | .type or1k_dcache_enable,@function |
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| 192 | |
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| 193 | or1k_dcache_enable: |
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| 194 | /* Enable DC */ |
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| 195 | l.mfspr r13,r0,OR1K_SPR_SYS_SR_ADDR |
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| 196 | l.ori r13,r13,OR1K_SPR_SYS_SR_DCE_MASK |
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| 197 | l.mtspr r0,r13,OR1K_SPR_SYS_SR_ADDR |
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| 198 | l.nop |
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| 199 | l.nop |
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| 200 | l.nop |
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| 201 | l.nop |
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| 202 | l.nop |
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| 203 | OR1K_DELAYED_NOP(OR1K_INST(l.jr r9)) |
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| 204 | |
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| 205 | /* -------------------------------------------------------------------------- */ |
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| 206 | /*!Function to disable data cache |
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| 207 | */ |
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| 208 | /* -------------------------------------------------------------------------- */ |
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| 209 | .global or1k_dcache_disable |
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| 210 | .type or1k_dcache_disable,@function |
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| 211 | |
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| 212 | or1k_dcache_disable: |
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| 213 | /* Disable DC */ |
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| 214 | l.mfspr r13,r0,OR1K_SPR_SYS_SR_ADDR |
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| 215 | l.addi r12,r0,-1 |
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| 216 | l.xori r12,r12,OR1K_SPR_SYS_SR_DCE_MASK |
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| 217 | l.and r12,r13,r12 |
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| 218 | l.mtspr r0,r12,OR1K_SPR_SYS_SR_ADDR |
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| 219 | OR1K_DELAYED_NOP(OR1K_INST(l.jr r9)) |
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| 220 | |
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| 221 | /* -------------------------------------------------------------------------- */ |
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| 222 | /*!Function to flush address of data cache |
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| 223 | */ |
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| 224 | /* -------------------------------------------------------------------------- */ |
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| 225 | .global or1k_dcache_flush |
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| 226 | .type or1k_dcache_flush,@function |
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| 227 | |
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| 228 | or1k_dcache_flush: |
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| 229 | OR1K_DELAYED( |
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| 230 | OR1K_INST(l.mtspr r0,r3,OR1K_SPR_DCACHE_DCBIR_ADDR), |
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| 231 | /* Push r3 into DC invalidate reg */ |
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| 232 | OR1K_INST(l.jr r9) |
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| 233 | ) |
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