[444] | 1 | /* or1k-sprs.h -- OR1K SPR definitions |
---|
| 2 | Copyright (c) 2014 OpenRISC Project Maintainers |
---|
| 3 | All rights reserved. |
---|
| 4 | |
---|
| 5 | Redistribution and use in source and binary forms, with or without |
---|
| 6 | modification, are permitted provided that the following condition |
---|
| 7 | is met: |
---|
| 8 | |
---|
| 9 | 1. Redistributions of source code must retain the above copyright |
---|
| 10 | notice, this list of conditions and the following disclaimer. |
---|
| 11 | |
---|
| 12 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
---|
| 13 | "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
---|
| 14 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
---|
| 15 | FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
---|
| 16 | COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
---|
| 17 | INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
---|
| 18 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
---|
| 19 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
---|
| 20 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
---|
| 21 | STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
---|
| 22 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED |
---|
| 23 | OF THE POSSIBILITY OF SUCH DAMAGE. |
---|
| 24 | */ |
---|
| 25 | |
---|
| 26 | /* |
---|
| 27 | * Generated from revision 4cab27375dd07cd890d5493e11446cc06ca8265e |
---|
| 28 | * on Tue Nov 18 14:35:33 2014 |
---|
| 29 | */ |
---|
| 30 | |
---|
| 31 | #ifndef _OR1K_SPRS_H_ |
---|
| 32 | #define _OR1K_SPRS_H_ |
---|
| 33 | |
---|
| 34 | #define OR1K_SPR_GROUP_BITS 5 |
---|
| 35 | #define OR1K_SPR_GROUP_LSB 11 |
---|
| 36 | #define OR1K_SPR_GROUP_MSB 15 |
---|
| 37 | #define OR1K_SPR_INDEX_BITS 11 |
---|
| 38 | #define OR1K_SPR_INDEX_LSB 0 |
---|
| 39 | #define OR1K_SPR_INDEX_MSB 10 |
---|
| 40 | |
---|
| 41 | #ifdef __ASSEMBLER__ |
---|
| 42 | #define OR1K_UNSIGNED(x) x |
---|
| 43 | #else |
---|
| 44 | #define OR1K_UNSIGNED(x) x##U |
---|
| 45 | #endif |
---|
| 46 | |
---|
| 47 | |
---|
| 48 | /****************/ |
---|
| 49 | /* System Group */ |
---|
| 50 | /****************/ |
---|
| 51 | #define OR1K_SPR_SYS_GROUP 0x00 |
---|
| 52 | |
---|
| 53 | /* Version Register */ |
---|
| 54 | #define OR1K_SPR_SYS_VR_INDEX OR1K_UNSIGNED(0x000) |
---|
| 55 | #define OR1K_SPR_SYS_VR_ADDR OR1K_UNSIGNED(0x0000) |
---|
| 56 | |
---|
| 57 | /* Revision */ |
---|
| 58 | #define OR1K_SPR_SYS_VR_REV_LSB 0 |
---|
| 59 | #define OR1K_SPR_SYS_VR_REV_MSB 5 |
---|
| 60 | #define OR1K_SPR_SYS_VR_REV_BITS 6 |
---|
| 61 | #define OR1K_SPR_SYS_VR_REV_MASK OR1K_UNSIGNED(0x0000003f) |
---|
| 62 | #define OR1K_SPR_SYS_VR_REV_GET(X) (((X) >> 0) & OR1K_UNSIGNED(0x0000003f)) |
---|
| 63 | #define OR1K_SPR_SYS_VR_REV_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffc0)) | ((Y) << 0)) |
---|
| 64 | |
---|
| 65 | /* Updated Version Registers Present */ |
---|
| 66 | #define OR1K_SPR_SYS_VR_UVRP_OFFSET 6 |
---|
| 67 | #define OR1K_SPR_SYS_VR_UVRP_MASK 0x00000040 |
---|
| 68 | #define OR1K_SPR_SYS_VR_UVRP_GET(X) (((X) >> 6) & 0x1) |
---|
| 69 | #define OR1K_SPR_SYS_VR_UVRP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6)) |
---|
| 70 | |
---|
| 71 | /* Configuration Template */ |
---|
| 72 | #define OR1K_SPR_SYS_VR_CFG_LSB 16 |
---|
| 73 | #define OR1K_SPR_SYS_VR_CFG_MSB 23 |
---|
| 74 | #define OR1K_SPR_SYS_VR_CFG_BITS 8 |
---|
| 75 | #define OR1K_SPR_SYS_VR_CFG_MASK OR1K_UNSIGNED(0x00ff0000) |
---|
| 76 | #define OR1K_SPR_SYS_VR_CFG_GET(X) (((X) >> 16) & OR1K_UNSIGNED(0x000000ff)) |
---|
| 77 | #define OR1K_SPR_SYS_VR_CFG_SET(X, Y) (((X) & OR1K_UNSIGNED(0xff00ffff)) | ((Y) << 16)) |
---|
| 78 | |
---|
| 79 | /* Version */ |
---|
| 80 | #define OR1K_SPR_SYS_VR_VER_LSB 24 |
---|
| 81 | #define OR1K_SPR_SYS_VR_VER_MSB 31 |
---|
| 82 | #define OR1K_SPR_SYS_VR_VER_BITS 8 |
---|
| 83 | #define OR1K_SPR_SYS_VR_VER_MASK OR1K_UNSIGNED(0xff000000) |
---|
| 84 | #define OR1K_SPR_SYS_VR_VER_GET(X) (((X) >> 24) & OR1K_UNSIGNED(0x000000ff)) |
---|
| 85 | #define OR1K_SPR_SYS_VR_VER_SET(X, Y) (((X) & OR1K_UNSIGNED(0x00ffffff)) | ((Y) << 24)) |
---|
| 86 | |
---|
| 87 | |
---|
| 88 | /* Unit Present Register */ |
---|
| 89 | #define OR1K_SPR_SYS_UPR_INDEX OR1K_UNSIGNED(0x001) |
---|
| 90 | #define OR1K_SPR_SYS_UPR_ADDR OR1K_UNSIGNED(0x0001) |
---|
| 91 | |
---|
| 92 | /* UPR Present */ |
---|
| 93 | #define OR1K_SPR_SYS_UPR_UP_OFFSET 0 |
---|
| 94 | #define OR1K_SPR_SYS_UPR_UP_MASK 0x00000001 |
---|
| 95 | #define OR1K_SPR_SYS_UPR_UP_GET(X) (((X) >> 0) & 0x1) |
---|
| 96 | #define OR1K_SPR_SYS_UPR_UP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 97 | |
---|
| 98 | /* Data Cache Present */ |
---|
| 99 | #define OR1K_SPR_SYS_UPR_DCP_OFFSET 1 |
---|
| 100 | #define OR1K_SPR_SYS_UPR_DCP_MASK 0x00000002 |
---|
| 101 | #define OR1K_SPR_SYS_UPR_DCP_GET(X) (((X) >> 1) & 0x1) |
---|
| 102 | #define OR1K_SPR_SYS_UPR_DCP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffd)) | ((!!(Y)) << 1)) |
---|
| 103 | |
---|
| 104 | /* Instruction Cache Present */ |
---|
| 105 | #define OR1K_SPR_SYS_UPR_ICP_OFFSET 2 |
---|
| 106 | #define OR1K_SPR_SYS_UPR_ICP_MASK 0x00000004 |
---|
| 107 | #define OR1K_SPR_SYS_UPR_ICP_GET(X) (((X) >> 2) & 0x1) |
---|
| 108 | #define OR1K_SPR_SYS_UPR_ICP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffb)) | ((!!(Y)) << 2)) |
---|
| 109 | |
---|
| 110 | /* Data MMU Present */ |
---|
| 111 | #define OR1K_SPR_SYS_UPR_DMP_OFFSET 3 |
---|
| 112 | #define OR1K_SPR_SYS_UPR_DMP_MASK 0x00000008 |
---|
| 113 | #define OR1K_SPR_SYS_UPR_DMP_GET(X) (((X) >> 3) & 0x1) |
---|
| 114 | #define OR1K_SPR_SYS_UPR_DMP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff7)) | ((!!(Y)) << 3)) |
---|
| 115 | |
---|
| 116 | /* Instruction MMU Present */ |
---|
| 117 | #define OR1K_SPR_SYS_UPR_IMP_OFFSET 4 |
---|
| 118 | #define OR1K_SPR_SYS_UPR_IMP_MASK 0x00000010 |
---|
| 119 | #define OR1K_SPR_SYS_UPR_IMP_GET(X) (((X) >> 4) & 0x1) |
---|
| 120 | #define OR1K_SPR_SYS_UPR_IMP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffef)) | ((!!(Y)) << 4)) |
---|
| 121 | |
---|
| 122 | /* MAC Present */ |
---|
| 123 | #define OR1K_SPR_SYS_UPR_MP_OFFSET 5 |
---|
| 124 | #define OR1K_SPR_SYS_UPR_MP_MASK 0x00000020 |
---|
| 125 | #define OR1K_SPR_SYS_UPR_MP_GET(X) (((X) >> 5) & 0x1) |
---|
| 126 | #define OR1K_SPR_SYS_UPR_MP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 127 | |
---|
| 128 | /* Debug Unit Present */ |
---|
| 129 | #define OR1K_SPR_SYS_UPR_DUP_OFFSET 6 |
---|
| 130 | #define OR1K_SPR_SYS_UPR_DUP_MASK 0x00000040 |
---|
| 131 | #define OR1K_SPR_SYS_UPR_DUP_GET(X) (((X) >> 6) & 0x1) |
---|
| 132 | #define OR1K_SPR_SYS_UPR_DUP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6)) |
---|
| 133 | |
---|
| 134 | /* Performance Counters Unit Present */ |
---|
| 135 | #define OR1K_SPR_SYS_UPR_PCUP_OFFSET 7 |
---|
| 136 | #define OR1K_SPR_SYS_UPR_PCUP_MASK 0x00000080 |
---|
| 137 | #define OR1K_SPR_SYS_UPR_PCUP_GET(X) (((X) >> 7) & 0x1) |
---|
| 138 | #define OR1K_SPR_SYS_UPR_PCUP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7)) |
---|
| 139 | |
---|
| 140 | /* Power Management Present */ |
---|
| 141 | #define OR1K_SPR_SYS_UPR_PICP_OFFSET 8 |
---|
| 142 | #define OR1K_SPR_SYS_UPR_PICP_MASK 0x00000100 |
---|
| 143 | #define OR1K_SPR_SYS_UPR_PICP_GET(X) (((X) >> 8) & 0x1) |
---|
| 144 | #define OR1K_SPR_SYS_UPR_PICP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffeff)) | ((!!(Y)) << 8)) |
---|
| 145 | |
---|
| 146 | /* Programmable Interrupt Controller Present */ |
---|
| 147 | #define OR1K_SPR_SYS_UPR_PMP_OFFSET 9 |
---|
| 148 | #define OR1K_SPR_SYS_UPR_PMP_MASK 0x00000200 |
---|
| 149 | #define OR1K_SPR_SYS_UPR_PMP_GET(X) (((X) >> 9) & 0x1) |
---|
| 150 | #define OR1K_SPR_SYS_UPR_PMP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffdff)) | ((!!(Y)) << 9)) |
---|
| 151 | |
---|
| 152 | /* Tick Timer Present */ |
---|
| 153 | #define OR1K_SPR_SYS_UPR_TTP_OFFSET 10 |
---|
| 154 | #define OR1K_SPR_SYS_UPR_TTP_MASK 0x00000400 |
---|
| 155 | #define OR1K_SPR_SYS_UPR_TTP_GET(X) (((X) >> 10) & 0x1) |
---|
| 156 | #define OR1K_SPR_SYS_UPR_TTP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffbff)) | ((!!(Y)) << 10)) |
---|
| 157 | |
---|
| 158 | /* Custom Units Present */ |
---|
| 159 | #define OR1K_SPR_SYS_UPR_CUP_LSB 24 |
---|
| 160 | #define OR1K_SPR_SYS_UPR_CUP_MSB 31 |
---|
| 161 | #define OR1K_SPR_SYS_UPR_CUP_BITS 8 |
---|
| 162 | #define OR1K_SPR_SYS_UPR_CUP_MASK OR1K_UNSIGNED(0xff000000) |
---|
| 163 | #define OR1K_SPR_SYS_UPR_CUP_GET(X) (((X) >> 24) & OR1K_UNSIGNED(0x000000ff)) |
---|
| 164 | #define OR1K_SPR_SYS_UPR_CUP_SET(X, Y) (((X) & OR1K_UNSIGNED(0x00ffffff)) | ((Y) << 24)) |
---|
| 165 | |
---|
| 166 | |
---|
| 167 | /* CPU Configuration Register */ |
---|
| 168 | #define OR1K_SPR_SYS_CPUCFGR_INDEX OR1K_UNSIGNED(0x002) |
---|
| 169 | #define OR1K_SPR_SYS_CPUCFGR_ADDR OR1K_UNSIGNED(0x0002) |
---|
| 170 | |
---|
| 171 | /* Number of Shadow GPR Files */ |
---|
| 172 | #define OR1K_SPR_SYS_CPUCFGR_NSGF_LSB 0 |
---|
| 173 | #define OR1K_SPR_SYS_CPUCFGR_NSGF_MSB 3 |
---|
| 174 | #define OR1K_SPR_SYS_CPUCFGR_NSGF_BITS 4 |
---|
| 175 | #define OR1K_SPR_SYS_CPUCFGR_NSGF_MASK OR1K_UNSIGNED(0x0000000f) |
---|
| 176 | #define OR1K_SPR_SYS_CPUCFGR_NSGF_GET(X) (((X) >> 0) & OR1K_UNSIGNED(0x0000000f)) |
---|
| 177 | #define OR1K_SPR_SYS_CPUCFGR_NSGF_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff0)) | ((Y) << 0)) |
---|
| 178 | |
---|
| 179 | /* Custom GPR File */ |
---|
| 180 | #define OR1K_SPR_SYS_CPUCFGR_CGF_OFFSET 4 |
---|
| 181 | #define OR1K_SPR_SYS_CPUCFGR_CGF_MASK 0x00000010 |
---|
| 182 | #define OR1K_SPR_SYS_CPUCFGR_CGF_GET(X) (((X) >> 4) & 0x1) |
---|
| 183 | #define OR1K_SPR_SYS_CPUCFGR_CGF_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffef)) | ((!!(Y)) << 4)) |
---|
| 184 | |
---|
| 185 | /* ORBIS32 Supported */ |
---|
| 186 | #define OR1K_SPR_SYS_CPUCFGR_OB32S_OFFSET 5 |
---|
| 187 | #define OR1K_SPR_SYS_CPUCFGR_OB32S_MASK 0x00000020 |
---|
| 188 | #define OR1K_SPR_SYS_CPUCFGR_OB32S_GET(X) (((X) >> 5) & 0x1) |
---|
| 189 | #define OR1K_SPR_SYS_CPUCFGR_OB32S_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 190 | |
---|
| 191 | /* ORBIS64 Supported */ |
---|
| 192 | #define OR1K_SPR_SYS_CPUCFGR_OB64S_OFFSET 6 |
---|
| 193 | #define OR1K_SPR_SYS_CPUCFGR_OB64S_MASK 0x00000040 |
---|
| 194 | #define OR1K_SPR_SYS_CPUCFGR_OB64S_GET(X) (((X) >> 6) & 0x1) |
---|
| 195 | #define OR1K_SPR_SYS_CPUCFGR_OB64S_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6)) |
---|
| 196 | |
---|
| 197 | /* ORFPX32 Supported */ |
---|
| 198 | #define OR1K_SPR_SYS_CPUCFGR_OF32S_OFFSET 7 |
---|
| 199 | #define OR1K_SPR_SYS_CPUCFGR_OF32S_MASK 0x00000080 |
---|
| 200 | #define OR1K_SPR_SYS_CPUCFGR_OF32S_GET(X) (((X) >> 7) & 0x1) |
---|
| 201 | #define OR1K_SPR_SYS_CPUCFGR_OF32S_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7)) |
---|
| 202 | |
---|
| 203 | /* ORFPX64 Supported */ |
---|
| 204 | #define OR1K_SPR_SYS_CPUCFGR_OF64S_OFFSET 8 |
---|
| 205 | #define OR1K_SPR_SYS_CPUCFGR_OF64S_MASK 0x00000100 |
---|
| 206 | #define OR1K_SPR_SYS_CPUCFGR_OF64S_GET(X) (((X) >> 8) & 0x1) |
---|
| 207 | #define OR1K_SPR_SYS_CPUCFGR_OF64S_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffeff)) | ((!!(Y)) << 8)) |
---|
| 208 | |
---|
| 209 | /* ORVDX64 Supported */ |
---|
| 210 | #define OR1K_SPR_SYS_CPUCFGR_OV64S_OFFSET 9 |
---|
| 211 | #define OR1K_SPR_SYS_CPUCFGR_OV64S_MASK 0x00000200 |
---|
| 212 | #define OR1K_SPR_SYS_CPUCFGR_OV64S_GET(X) (((X) >> 9) & 0x1) |
---|
| 213 | #define OR1K_SPR_SYS_CPUCFGR_OV64S_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffdff)) | ((!!(Y)) << 9)) |
---|
| 214 | |
---|
| 215 | /* No Delay-Slot */ |
---|
| 216 | #define OR1K_SPR_SYS_CPUCFGR_ND_OFFSET 10 |
---|
| 217 | #define OR1K_SPR_SYS_CPUCFGR_ND_MASK 0x00000400 |
---|
| 218 | #define OR1K_SPR_SYS_CPUCFGR_ND_GET(X) (((X) >> 10) & 0x1) |
---|
| 219 | #define OR1K_SPR_SYS_CPUCFGR_ND_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffbff)) | ((!!(Y)) << 10)) |
---|
| 220 | |
---|
| 221 | /* Architecture Version Register Present */ |
---|
| 222 | #define OR1K_SPR_SYS_CPUCFGR_AVRP_OFFSET 11 |
---|
| 223 | #define OR1K_SPR_SYS_CPUCFGR_AVRP_MASK 0x00000800 |
---|
| 224 | #define OR1K_SPR_SYS_CPUCFGR_AVRP_GET(X) (((X) >> 11) & 0x1) |
---|
| 225 | #define OR1K_SPR_SYS_CPUCFGR_AVRP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffff7ff)) | ((!!(Y)) << 11)) |
---|
| 226 | |
---|
| 227 | /* Exception Vector Base Address Register Present */ |
---|
| 228 | #define OR1K_SPR_SYS_CPUCFGR_EVBARP_OFFSET 12 |
---|
| 229 | #define OR1K_SPR_SYS_CPUCFGR_EVBARP_MASK 0x00001000 |
---|
| 230 | #define OR1K_SPR_SYS_CPUCFGR_EVBARP_GET(X) (((X) >> 12) & 0x1) |
---|
| 231 | #define OR1K_SPR_SYS_CPUCFGR_EVBARP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffefff)) | ((!!(Y)) << 12)) |
---|
| 232 | |
---|
| 233 | /* Implementation-Specific Registers (ISR0-7) Present */ |
---|
| 234 | #define OR1K_SPR_SYS_CPUCFGR_ISRP_OFFSET 13 |
---|
| 235 | #define OR1K_SPR_SYS_CPUCFGR_ISRP_MASK 0x00002000 |
---|
| 236 | #define OR1K_SPR_SYS_CPUCFGR_ISRP_GET(X) (((X) >> 13) & 0x1) |
---|
| 237 | #define OR1K_SPR_SYS_CPUCFGR_ISRP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffdfff)) | ((!!(Y)) << 13)) |
---|
| 238 | |
---|
| 239 | /* Arithmetic Exception Control/Status Registers Present */ |
---|
| 240 | #define OR1K_SPR_SYS_CPUCFGR_AECSRP_OFFSET 14 |
---|
| 241 | #define OR1K_SPR_SYS_CPUCFGR_AECSRP_MASK 0x00004000 |
---|
| 242 | #define OR1K_SPR_SYS_CPUCFGR_AECSRP_GET(X) (((X) >> 14) & 0x1) |
---|
| 243 | #define OR1K_SPR_SYS_CPUCFGR_AECSRP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffbfff)) | ((!!(Y)) << 14)) |
---|
| 244 | |
---|
| 245 | |
---|
| 246 | /* Data MMU Configuration Register */ |
---|
| 247 | #define OR1K_SPR_SYS_DMMUCFGR_INDEX OR1K_UNSIGNED(0x003) |
---|
| 248 | #define OR1K_SPR_SYS_DMMUCFGR_ADDR OR1K_UNSIGNED(0x0003) |
---|
| 249 | |
---|
| 250 | /* Number of TLB Ways */ |
---|
| 251 | #define OR1K_SPR_SYS_DMMUCFGR_NTW_LSB 0 |
---|
| 252 | #define OR1K_SPR_SYS_DMMUCFGR_NTW_MSB 1 |
---|
| 253 | #define OR1K_SPR_SYS_DMMUCFGR_NTW_BITS 2 |
---|
| 254 | #define OR1K_SPR_SYS_DMMUCFGR_NTW_MASK OR1K_UNSIGNED(0x00000003) |
---|
| 255 | #define OR1K_SPR_SYS_DMMUCFGR_NTW_GET(X) (((X) >> 0) & OR1K_UNSIGNED(0x00000003)) |
---|
| 256 | #define OR1K_SPR_SYS_DMMUCFGR_NTW_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffc)) | ((Y) << 0)) |
---|
| 257 | |
---|
| 258 | /* Number of TLB Sets */ |
---|
| 259 | #define OR1K_SPR_SYS_DMMUCFGR_NTS_LSB 2 |
---|
| 260 | #define OR1K_SPR_SYS_DMMUCFGR_NTS_MSB 4 |
---|
| 261 | #define OR1K_SPR_SYS_DMMUCFGR_NTS_BITS 3 |
---|
| 262 | #define OR1K_SPR_SYS_DMMUCFGR_NTS_MASK OR1K_UNSIGNED(0x0000001c) |
---|
| 263 | #define OR1K_SPR_SYS_DMMUCFGR_NTS_GET(X) (((X) >> 2) & OR1K_UNSIGNED(0x00000007)) |
---|
| 264 | #define OR1K_SPR_SYS_DMMUCFGR_NTS_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffe3)) | ((Y) << 2)) |
---|
| 265 | |
---|
| 266 | /* Number of ATB Entries */ |
---|
| 267 | #define OR1K_SPR_SYS_DMMUCFGR_NAE_LSB 5 |
---|
| 268 | #define OR1K_SPR_SYS_DMMUCFGR_NAE_MSB 7 |
---|
| 269 | #define OR1K_SPR_SYS_DMMUCFGR_NAE_BITS 3 |
---|
| 270 | #define OR1K_SPR_SYS_DMMUCFGR_NAE_MASK OR1K_UNSIGNED(0x000000e0) |
---|
| 271 | #define OR1K_SPR_SYS_DMMUCFGR_NAE_GET(X) (((X) >> 5) & OR1K_UNSIGNED(0x00000007)) |
---|
| 272 | #define OR1K_SPR_SYS_DMMUCFGR_NAE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff1f)) | ((Y) << 5)) |
---|
| 273 | |
---|
| 274 | /* Control Register Implemented */ |
---|
| 275 | #define OR1K_SPR_SYS_DMMUCFGR_CRI_OFFSET 8 |
---|
| 276 | #define OR1K_SPR_SYS_DMMUCFGR_CRI_MASK 0x00000100 |
---|
| 277 | #define OR1K_SPR_SYS_DMMUCFGR_CRI_GET(X) (((X) >> 8) & 0x1) |
---|
| 278 | #define OR1K_SPR_SYS_DMMUCFGR_CRI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffeff)) | ((!!(Y)) << 8)) |
---|
| 279 | |
---|
| 280 | /* Protection Register Implemented */ |
---|
| 281 | #define OR1K_SPR_SYS_DMMUCFGR_PRI_OFFSET 9 |
---|
| 282 | #define OR1K_SPR_SYS_DMMUCFGR_PRI_MASK 0x00000200 |
---|
| 283 | #define OR1K_SPR_SYS_DMMUCFGR_PRI_GET(X) (((X) >> 9) & 0x1) |
---|
| 284 | #define OR1K_SPR_SYS_DMMUCFGR_PRI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffdff)) | ((!!(Y)) << 9)) |
---|
| 285 | |
---|
| 286 | /* TLB Entry Invalidate Register Implemented */ |
---|
| 287 | #define OR1K_SPR_SYS_DMMUCFGR_TEIRI_OFFSET 10 |
---|
| 288 | #define OR1K_SPR_SYS_DMMUCFGR_TEIRI_MASK 0x00000400 |
---|
| 289 | #define OR1K_SPR_SYS_DMMUCFGR_TEIRI_GET(X) (((X) >> 10) & 0x1) |
---|
| 290 | #define OR1K_SPR_SYS_DMMUCFGR_TEIRI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffbff)) | ((!!(Y)) << 10)) |
---|
| 291 | |
---|
| 292 | /* Hardware TLB Reload */ |
---|
| 293 | #define OR1K_SPR_SYS_DMMUCFGR_HTR_OFFSET 11 |
---|
| 294 | #define OR1K_SPR_SYS_DMMUCFGR_HTR_MASK 0x00000800 |
---|
| 295 | #define OR1K_SPR_SYS_DMMUCFGR_HTR_GET(X) (((X) >> 11) & 0x1) |
---|
| 296 | #define OR1K_SPR_SYS_DMMUCFGR_HTR_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffff7ff)) | ((!!(Y)) << 11)) |
---|
| 297 | |
---|
| 298 | /* DTLB reloaded in software */ |
---|
| 299 | #define OR1K_SPR_SYS_DMMUCFGR_HTR_SW 0 |
---|
| 300 | /* DTLB reloaded in hardware */ |
---|
| 301 | #define OR1K_SPR_SYS_DMMUCFGR_HTR_HW 1 |
---|
| 302 | |
---|
| 303 | /* Instruction MMU Configuration Register */ |
---|
| 304 | #define OR1K_SPR_SYS_IMMUCFGR_INDEX OR1K_UNSIGNED(0x004) |
---|
| 305 | #define OR1K_SPR_SYS_IMMUCFGR_ADDR OR1K_UNSIGNED(0x0004) |
---|
| 306 | |
---|
| 307 | /* Number of TLB Ways */ |
---|
| 308 | #define OR1K_SPR_SYS_IMMUCFGR_NTW_LSB 0 |
---|
| 309 | #define OR1K_SPR_SYS_IMMUCFGR_NTW_MSB 1 |
---|
| 310 | #define OR1K_SPR_SYS_IMMUCFGR_NTW_BITS 2 |
---|
| 311 | #define OR1K_SPR_SYS_IMMUCFGR_NTW_MASK OR1K_UNSIGNED(0x00000003) |
---|
| 312 | #define OR1K_SPR_SYS_IMMUCFGR_NTW_GET(X) (((X) >> 0) & OR1K_UNSIGNED(0x00000003)) |
---|
| 313 | #define OR1K_SPR_SYS_IMMUCFGR_NTW_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffc)) | ((Y) << 0)) |
---|
| 314 | |
---|
| 315 | /* Number of TLB Sets */ |
---|
| 316 | #define OR1K_SPR_SYS_IMMUCFGR_NTS_LSB 2 |
---|
| 317 | #define OR1K_SPR_SYS_IMMUCFGR_NTS_MSB 4 |
---|
| 318 | #define OR1K_SPR_SYS_IMMUCFGR_NTS_BITS 3 |
---|
| 319 | #define OR1K_SPR_SYS_IMMUCFGR_NTS_MASK OR1K_UNSIGNED(0x0000001c) |
---|
| 320 | #define OR1K_SPR_SYS_IMMUCFGR_NTS_GET(X) (((X) >> 2) & OR1K_UNSIGNED(0x00000007)) |
---|
| 321 | #define OR1K_SPR_SYS_IMMUCFGR_NTS_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffe3)) | ((Y) << 2)) |
---|
| 322 | |
---|
| 323 | /* Number of ATB Entries */ |
---|
| 324 | #define OR1K_SPR_SYS_IMMUCFGR_NAE_LSB 5 |
---|
| 325 | #define OR1K_SPR_SYS_IMMUCFGR_NAE_MSB 7 |
---|
| 326 | #define OR1K_SPR_SYS_IMMUCFGR_NAE_BITS 3 |
---|
| 327 | #define OR1K_SPR_SYS_IMMUCFGR_NAE_MASK OR1K_UNSIGNED(0x000000e0) |
---|
| 328 | #define OR1K_SPR_SYS_IMMUCFGR_NAE_GET(X) (((X) >> 5) & OR1K_UNSIGNED(0x00000007)) |
---|
| 329 | #define OR1K_SPR_SYS_IMMUCFGR_NAE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff1f)) | ((Y) << 5)) |
---|
| 330 | |
---|
| 331 | /* Control Register Implemented */ |
---|
| 332 | #define OR1K_SPR_SYS_IMMUCFGR_CRI_OFFSET 8 |
---|
| 333 | #define OR1K_SPR_SYS_IMMUCFGR_CRI_MASK 0x00000100 |
---|
| 334 | #define OR1K_SPR_SYS_IMMUCFGR_CRI_GET(X) (((X) >> 8) & 0x1) |
---|
| 335 | #define OR1K_SPR_SYS_IMMUCFGR_CRI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffeff)) | ((!!(Y)) << 8)) |
---|
| 336 | |
---|
| 337 | /* Protection Register Implemented */ |
---|
| 338 | #define OR1K_SPR_SYS_IMMUCFGR_PRI_OFFSET 9 |
---|
| 339 | #define OR1K_SPR_SYS_IMMUCFGR_PRI_MASK 0x00000200 |
---|
| 340 | #define OR1K_SPR_SYS_IMMUCFGR_PRI_GET(X) (((X) >> 9) & 0x1) |
---|
| 341 | #define OR1K_SPR_SYS_IMMUCFGR_PRI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffdff)) | ((!!(Y)) << 9)) |
---|
| 342 | |
---|
| 343 | /* TLB Entry Invalidate Register Implemented */ |
---|
| 344 | #define OR1K_SPR_SYS_IMMUCFGR_TEIRI_OFFSET 10 |
---|
| 345 | #define OR1K_SPR_SYS_IMMUCFGR_TEIRI_MASK 0x00000400 |
---|
| 346 | #define OR1K_SPR_SYS_IMMUCFGR_TEIRI_GET(X) (((X) >> 10) & 0x1) |
---|
| 347 | #define OR1K_SPR_SYS_IMMUCFGR_TEIRI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffbff)) | ((!!(Y)) << 10)) |
---|
| 348 | |
---|
| 349 | /* Hardware TLB Reload */ |
---|
| 350 | #define OR1K_SPR_SYS_IMMUCFGR_HTR_OFFSET 11 |
---|
| 351 | #define OR1K_SPR_SYS_IMMUCFGR_HTR_MASK 0x00000800 |
---|
| 352 | #define OR1K_SPR_SYS_IMMUCFGR_HTR_GET(X) (((X) >> 11) & 0x1) |
---|
| 353 | #define OR1K_SPR_SYS_IMMUCFGR_HTR_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffff7ff)) | ((!!(Y)) << 11)) |
---|
| 354 | |
---|
| 355 | /* DTLB reloaded in software */ |
---|
| 356 | #define OR1K_SPR_SYS_IMMUCFGR_HTR_SW 0 |
---|
| 357 | /* DTLB reloaded in hardware */ |
---|
| 358 | #define OR1K_SPR_SYS_IMMUCFGR_HTR_HW 1 |
---|
| 359 | |
---|
| 360 | /* Data Cache Configuration Register */ |
---|
| 361 | #define OR1K_SPR_SYS_DCCFGR_INDEX OR1K_UNSIGNED(0x005) |
---|
| 362 | #define OR1K_SPR_SYS_DCCFGR_ADDR OR1K_UNSIGNED(0x0005) |
---|
| 363 | |
---|
| 364 | /* Number of Cache Ways */ |
---|
| 365 | #define OR1K_SPR_SYS_DCCFGR_NCW_LSB 0 |
---|
| 366 | #define OR1K_SPR_SYS_DCCFGR_NCW_MSB 2 |
---|
| 367 | #define OR1K_SPR_SYS_DCCFGR_NCW_BITS 3 |
---|
| 368 | #define OR1K_SPR_SYS_DCCFGR_NCW_MASK OR1K_UNSIGNED(0x00000007) |
---|
| 369 | #define OR1K_SPR_SYS_DCCFGR_NCW_GET(X) (((X) >> 0) & OR1K_UNSIGNED(0x00000007)) |
---|
| 370 | #define OR1K_SPR_SYS_DCCFGR_NCW_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff8)) | ((Y) << 0)) |
---|
| 371 | |
---|
| 372 | /* Number of Cache Sets */ |
---|
| 373 | #define OR1K_SPR_SYS_DCCFGR_NCS_LSB 3 |
---|
| 374 | #define OR1K_SPR_SYS_DCCFGR_NCS_MSB 6 |
---|
| 375 | #define OR1K_SPR_SYS_DCCFGR_NCS_BITS 4 |
---|
| 376 | #define OR1K_SPR_SYS_DCCFGR_NCS_MASK OR1K_UNSIGNED(0x00000078) |
---|
| 377 | #define OR1K_SPR_SYS_DCCFGR_NCS_GET(X) (((X) >> 3) & OR1K_UNSIGNED(0x0000000f)) |
---|
| 378 | #define OR1K_SPR_SYS_DCCFGR_NCS_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff87)) | ((Y) << 3)) |
---|
| 379 | |
---|
| 380 | /* Cache Block Size */ |
---|
| 381 | #define OR1K_SPR_SYS_DCCFGR_CBS_OFFSET 7 |
---|
| 382 | #define OR1K_SPR_SYS_DCCFGR_CBS_MASK 0x00000080 |
---|
| 383 | #define OR1K_SPR_SYS_DCCFGR_CBS_GET(X) (((X) >> 7) & 0x1) |
---|
| 384 | #define OR1K_SPR_SYS_DCCFGR_CBS_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7)) |
---|
| 385 | |
---|
| 386 | /* 16 Bytes */ |
---|
| 387 | #define OR1K_SPR_SYS_DCCFGR_CBS_16 0 |
---|
| 388 | /* 32 Bytes */ |
---|
| 389 | #define OR1K_SPR_SYS_DCCFGR_CBS_32 1 |
---|
| 390 | /* Cache Write Strategy */ |
---|
| 391 | #define OR1K_SPR_SYS_DCCFGR_CWS_OFFSET 8 |
---|
| 392 | #define OR1K_SPR_SYS_DCCFGR_CWS_MASK 0x00000100 |
---|
| 393 | #define OR1K_SPR_SYS_DCCFGR_CWS_GET(X) (((X) >> 8) & 0x1) |
---|
| 394 | #define OR1K_SPR_SYS_DCCFGR_CWS_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffeff)) | ((!!(Y)) << 8)) |
---|
| 395 | |
---|
| 396 | /* Write Through */ |
---|
| 397 | #define OR1K_SPR_SYS_DCCFGR_CWS_WT 0 |
---|
| 398 | /* Write Back */ |
---|
| 399 | #define OR1K_SPR_SYS_DCCFGR_CWS_WB 1 |
---|
| 400 | /* Cache Control Register Implemented */ |
---|
| 401 | #define OR1K_SPR_SYS_DCCFGR_CCRI_OFFSET 9 |
---|
| 402 | #define OR1K_SPR_SYS_DCCFGR_CCRI_MASK 0x00000200 |
---|
| 403 | #define OR1K_SPR_SYS_DCCFGR_CCRI_GET(X) (((X) >> 9) & 0x1) |
---|
| 404 | #define OR1K_SPR_SYS_DCCFGR_CCRI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffdff)) | ((!!(Y)) << 9)) |
---|
| 405 | |
---|
| 406 | /* Cache Block Invalidate Register Implemented */ |
---|
| 407 | #define OR1K_SPR_SYS_DCCFGR_CBIRI_OFFSET 10 |
---|
| 408 | #define OR1K_SPR_SYS_DCCFGR_CBIRI_MASK 0x00000400 |
---|
| 409 | #define OR1K_SPR_SYS_DCCFGR_CBIRI_GET(X) (((X) >> 10) & 0x1) |
---|
| 410 | #define OR1K_SPR_SYS_DCCFGR_CBIRI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffbff)) | ((!!(Y)) << 10)) |
---|
| 411 | |
---|
| 412 | /* Cache Block Prefetch Register Implemented */ |
---|
| 413 | #define OR1K_SPR_SYS_DCCFGR_CBPRI_OFFSET 11 |
---|
| 414 | #define OR1K_SPR_SYS_DCCFGR_CBPRI_MASK 0x00000800 |
---|
| 415 | #define OR1K_SPR_SYS_DCCFGR_CBPRI_GET(X) (((X) >> 11) & 0x1) |
---|
| 416 | #define OR1K_SPR_SYS_DCCFGR_CBPRI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffff7ff)) | ((!!(Y)) << 11)) |
---|
| 417 | |
---|
| 418 | /* Cache Block Lock Register Implemented */ |
---|
| 419 | #define OR1K_SPR_SYS_DCCFGR_CBLRI_OFFSET 12 |
---|
| 420 | #define OR1K_SPR_SYS_DCCFGR_CBLRI_MASK 0x00001000 |
---|
| 421 | #define OR1K_SPR_SYS_DCCFGR_CBLRI_GET(X) (((X) >> 12) & 0x1) |
---|
| 422 | #define OR1K_SPR_SYS_DCCFGR_CBLRI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffefff)) | ((!!(Y)) << 12)) |
---|
| 423 | |
---|
| 424 | /* Cache Block Flush Register Implemented */ |
---|
| 425 | #define OR1K_SPR_SYS_DCCFGR_CBFRI_OFFSET 13 |
---|
| 426 | #define OR1K_SPR_SYS_DCCFGR_CBFRI_MASK 0x00002000 |
---|
| 427 | #define OR1K_SPR_SYS_DCCFGR_CBFRI_GET(X) (((X) >> 13) & 0x1) |
---|
| 428 | #define OR1K_SPR_SYS_DCCFGR_CBFRI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffdfff)) | ((!!(Y)) << 13)) |
---|
| 429 | |
---|
| 430 | /* Cache Block Write-back Register Implemented */ |
---|
| 431 | #define OR1K_SPR_SYS_DCCFGR_CBWBRI_OFFSET 14 |
---|
| 432 | #define OR1K_SPR_SYS_DCCFGR_CBWBRI_MASK 0x00004000 |
---|
| 433 | #define OR1K_SPR_SYS_DCCFGR_CBWBRI_GET(X) (((X) >> 14) & 0x1) |
---|
| 434 | #define OR1K_SPR_SYS_DCCFGR_CBWBRI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffbfff)) | ((!!(Y)) << 14)) |
---|
| 435 | |
---|
| 436 | |
---|
| 437 | /* Instruction Cache Configuration Register */ |
---|
| 438 | #define OR1K_SPR_SYS_ICCFGR_INDEX OR1K_UNSIGNED(0x006) |
---|
| 439 | #define OR1K_SPR_SYS_ICCFGR_ADDR OR1K_UNSIGNED(0x0006) |
---|
| 440 | |
---|
| 441 | /* Number of Cache Ways */ |
---|
| 442 | #define OR1K_SPR_SYS_ICCFGR_NCW_LSB 0 |
---|
| 443 | #define OR1K_SPR_SYS_ICCFGR_NCW_MSB 2 |
---|
| 444 | #define OR1K_SPR_SYS_ICCFGR_NCW_BITS 3 |
---|
| 445 | #define OR1K_SPR_SYS_ICCFGR_NCW_MASK OR1K_UNSIGNED(0x00000007) |
---|
| 446 | #define OR1K_SPR_SYS_ICCFGR_NCW_GET(X) (((X) >> 0) & OR1K_UNSIGNED(0x00000007)) |
---|
| 447 | #define OR1K_SPR_SYS_ICCFGR_NCW_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff8)) | ((Y) << 0)) |
---|
| 448 | |
---|
| 449 | /* Number of Cache Sets */ |
---|
| 450 | #define OR1K_SPR_SYS_ICCFGR_NCS_LSB 3 |
---|
| 451 | #define OR1K_SPR_SYS_ICCFGR_NCS_MSB 6 |
---|
| 452 | #define OR1K_SPR_SYS_ICCFGR_NCS_BITS 4 |
---|
| 453 | #define OR1K_SPR_SYS_ICCFGR_NCS_MASK OR1K_UNSIGNED(0x00000078) |
---|
| 454 | #define OR1K_SPR_SYS_ICCFGR_NCS_GET(X) (((X) >> 3) & OR1K_UNSIGNED(0x0000000f)) |
---|
| 455 | #define OR1K_SPR_SYS_ICCFGR_NCS_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff87)) | ((Y) << 3)) |
---|
| 456 | |
---|
| 457 | /* Cache Block Size */ |
---|
| 458 | #define OR1K_SPR_SYS_ICCFGR_CBS_OFFSET 7 |
---|
| 459 | #define OR1K_SPR_SYS_ICCFGR_CBS_MASK 0x00000080 |
---|
| 460 | #define OR1K_SPR_SYS_ICCFGR_CBS_GET(X) (((X) >> 7) & 0x1) |
---|
| 461 | #define OR1K_SPR_SYS_ICCFGR_CBS_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7)) |
---|
| 462 | |
---|
| 463 | /* 16 Bytes */ |
---|
| 464 | #define OR1K_SPR_SYS_ICCFGR_CBS_16 0 |
---|
| 465 | /* 32 Bytes */ |
---|
| 466 | #define OR1K_SPR_SYS_ICCFGR_CBS_32 1 |
---|
| 467 | /* Cache Control Register Implemented */ |
---|
| 468 | #define OR1K_SPR_SYS_ICCFGR_CCRI_OFFSET 9 |
---|
| 469 | #define OR1K_SPR_SYS_ICCFGR_CCRI_MASK 0x00000200 |
---|
| 470 | #define OR1K_SPR_SYS_ICCFGR_CCRI_GET(X) (((X) >> 9) & 0x1) |
---|
| 471 | #define OR1K_SPR_SYS_ICCFGR_CCRI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffdff)) | ((!!(Y)) << 9)) |
---|
| 472 | |
---|
| 473 | /* Cache Block Invalidate Register Implemented */ |
---|
| 474 | #define OR1K_SPR_SYS_ICCFGR_CBIRI_OFFSET 10 |
---|
| 475 | #define OR1K_SPR_SYS_ICCFGR_CBIRI_MASK 0x00000400 |
---|
| 476 | #define OR1K_SPR_SYS_ICCFGR_CBIRI_GET(X) (((X) >> 10) & 0x1) |
---|
| 477 | #define OR1K_SPR_SYS_ICCFGR_CBIRI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffbff)) | ((!!(Y)) << 10)) |
---|
| 478 | |
---|
| 479 | /* Cache Block Prefetch Register Implemented */ |
---|
| 480 | #define OR1K_SPR_SYS_ICCFGR_CBPRI_OFFSET 11 |
---|
| 481 | #define OR1K_SPR_SYS_ICCFGR_CBPRI_MASK 0x00000800 |
---|
| 482 | #define OR1K_SPR_SYS_ICCFGR_CBPRI_GET(X) (((X) >> 11) & 0x1) |
---|
| 483 | #define OR1K_SPR_SYS_ICCFGR_CBPRI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffff7ff)) | ((!!(Y)) << 11)) |
---|
| 484 | |
---|
| 485 | /* Cache Block Lock Register Implemented */ |
---|
| 486 | #define OR1K_SPR_SYS_ICCFGR_CBLRI_OFFSET 12 |
---|
| 487 | #define OR1K_SPR_SYS_ICCFGR_CBLRI_MASK 0x00001000 |
---|
| 488 | #define OR1K_SPR_SYS_ICCFGR_CBLRI_GET(X) (((X) >> 12) & 0x1) |
---|
| 489 | #define OR1K_SPR_SYS_ICCFGR_CBLRI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffefff)) | ((!!(Y)) << 12)) |
---|
| 490 | |
---|
| 491 | |
---|
| 492 | /* Debug Configuration Register */ |
---|
| 493 | #define OR1K_SPR_SYS_DCFGR_INDEX OR1K_UNSIGNED(0x007) |
---|
| 494 | #define OR1K_SPR_SYS_DCFGR_ADDR OR1K_UNSIGNED(0x0007) |
---|
| 495 | |
---|
| 496 | /* Number of Debug Pairs */ |
---|
| 497 | #define OR1K_SPR_SYS_DCFGR_NDP_LSB 0 |
---|
| 498 | #define OR1K_SPR_SYS_DCFGR_NDP_MSB 2 |
---|
| 499 | #define OR1K_SPR_SYS_DCFGR_NDP_BITS 3 |
---|
| 500 | #define OR1K_SPR_SYS_DCFGR_NDP_MASK OR1K_UNSIGNED(0x00000007) |
---|
| 501 | #define OR1K_SPR_SYS_DCFGR_NDP_GET(X) (((X) >> 0) & OR1K_UNSIGNED(0x00000007)) |
---|
| 502 | #define OR1K_SPR_SYS_DCFGR_NDP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff8)) | ((Y) << 0)) |
---|
| 503 | |
---|
| 504 | /* Watchpoint Counters Implemented */ |
---|
| 505 | #define OR1K_SPR_SYS_DCFGR_WPCI_OFFSET 3 |
---|
| 506 | #define OR1K_SPR_SYS_DCFGR_WPCI_MASK 0x00000008 |
---|
| 507 | #define OR1K_SPR_SYS_DCFGR_WPCI_GET(X) (((X) >> 3) & 0x1) |
---|
| 508 | #define OR1K_SPR_SYS_DCFGR_WPCI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff7)) | ((!!(Y)) << 3)) |
---|
| 509 | |
---|
| 510 | |
---|
| 511 | /* Performance Counters Configuration */ |
---|
| 512 | #define OR1K_SPR_SYS_PCCFGR_INDEX OR1K_UNSIGNED(0x008) |
---|
| 513 | #define OR1K_SPR_SYS_PCCFGR_ADDR OR1K_UNSIGNED(0x0008) |
---|
| 514 | |
---|
| 515 | /* Number of Performance Counters */ |
---|
| 516 | #define OR1K_SPR_SYS_PCCFGR_NPC_LSB 0 |
---|
| 517 | #define OR1K_SPR_SYS_PCCFGR_NPC_MSB 2 |
---|
| 518 | #define OR1K_SPR_SYS_PCCFGR_NPC_BITS 3 |
---|
| 519 | #define OR1K_SPR_SYS_PCCFGR_NPC_MASK OR1K_UNSIGNED(0x00000007) |
---|
| 520 | #define OR1K_SPR_SYS_PCCFGR_NPC_GET(X) (((X) >> 0) & OR1K_UNSIGNED(0x00000007)) |
---|
| 521 | #define OR1K_SPR_SYS_PCCFGR_NPC_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff8)) | ((Y) << 0)) |
---|
| 522 | |
---|
| 523 | |
---|
| 524 | /* Version Register 2 */ |
---|
| 525 | #define OR1K_SPR_SYS_VR2_INDEX OR1K_UNSIGNED(0x009) |
---|
| 526 | #define OR1K_SPR_SYS_VR2_ADDR OR1K_UNSIGNED(0x0009) |
---|
| 527 | |
---|
| 528 | /* Version */ |
---|
| 529 | #define OR1K_SPR_SYS_VR2_VER_LSB 0 |
---|
| 530 | #define OR1K_SPR_SYS_VR2_VER_MSB 23 |
---|
| 531 | #define OR1K_SPR_SYS_VR2_VER_BITS 24 |
---|
| 532 | #define OR1K_SPR_SYS_VR2_VER_MASK OR1K_UNSIGNED(0x00ffffff) |
---|
| 533 | #define OR1K_SPR_SYS_VR2_VER_GET(X) (((X) >> 0) & OR1K_UNSIGNED(0x00ffffff)) |
---|
| 534 | #define OR1K_SPR_SYS_VR2_VER_SET(X, Y) (((X) & OR1K_UNSIGNED(0xff000000)) | ((Y) << 0)) |
---|
| 535 | |
---|
| 536 | /* CPU Identification Number */ |
---|
| 537 | #define OR1K_SPR_SYS_VR2_CPUID_LSB 24 |
---|
| 538 | #define OR1K_SPR_SYS_VR2_CPUID_MSB 31 |
---|
| 539 | #define OR1K_SPR_SYS_VR2_CPUID_BITS 8 |
---|
| 540 | #define OR1K_SPR_SYS_VR2_CPUID_MASK OR1K_UNSIGNED(0xff000000) |
---|
| 541 | #define OR1K_SPR_SYS_VR2_CPUID_GET(X) (((X) >> 24) & OR1K_UNSIGNED(0x000000ff)) |
---|
| 542 | #define OR1K_SPR_SYS_VR2_CPUID_SET(X, Y) (((X) & OR1K_UNSIGNED(0x00ffffff)) | ((Y) << 24)) |
---|
| 543 | |
---|
| 544 | |
---|
| 545 | /* Architecture Version Register */ |
---|
| 546 | #define OR1K_SPR_SYS_AVR_INDEX OR1K_UNSIGNED(0x00a) |
---|
| 547 | #define OR1K_SPR_SYS_AVR_ADDR OR1K_UNSIGNED(0x000a) |
---|
| 548 | |
---|
| 549 | /* Major Architecture Version Number */ |
---|
| 550 | #define OR1K_SPR_SYS_AVR_REV_LSB 8 |
---|
| 551 | #define OR1K_SPR_SYS_AVR_REV_MSB 15 |
---|
| 552 | #define OR1K_SPR_SYS_AVR_REV_BITS 8 |
---|
| 553 | #define OR1K_SPR_SYS_AVR_REV_MASK OR1K_UNSIGNED(0x0000ff00) |
---|
| 554 | #define OR1K_SPR_SYS_AVR_REV_GET(X) (((X) >> 8) & OR1K_UNSIGNED(0x000000ff)) |
---|
| 555 | #define OR1K_SPR_SYS_AVR_REV_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffff00ff)) | ((Y) << 8)) |
---|
| 556 | |
---|
| 557 | /* Minor Architecture Version Number */ |
---|
| 558 | #define OR1K_SPR_SYS_AVR_MIN_LSB 16 |
---|
| 559 | #define OR1K_SPR_SYS_AVR_MIN_MSB 23 |
---|
| 560 | #define OR1K_SPR_SYS_AVR_MIN_BITS 8 |
---|
| 561 | #define OR1K_SPR_SYS_AVR_MIN_MASK OR1K_UNSIGNED(0x00ff0000) |
---|
| 562 | #define OR1K_SPR_SYS_AVR_MIN_GET(X) (((X) >> 16) & OR1K_UNSIGNED(0x000000ff)) |
---|
| 563 | #define OR1K_SPR_SYS_AVR_MIN_SET(X, Y) (((X) & OR1K_UNSIGNED(0xff00ffff)) | ((Y) << 16)) |
---|
| 564 | |
---|
| 565 | /* Architecture Revision Number */ |
---|
| 566 | #define OR1K_SPR_SYS_AVR_MAJ_LSB 24 |
---|
| 567 | #define OR1K_SPR_SYS_AVR_MAJ_MSB 31 |
---|
| 568 | #define OR1K_SPR_SYS_AVR_MAJ_BITS 8 |
---|
| 569 | #define OR1K_SPR_SYS_AVR_MAJ_MASK OR1K_UNSIGNED(0xff000000) |
---|
| 570 | #define OR1K_SPR_SYS_AVR_MAJ_GET(X) (((X) >> 24) & OR1K_UNSIGNED(0x000000ff)) |
---|
| 571 | #define OR1K_SPR_SYS_AVR_MAJ_SET(X, Y) (((X) & OR1K_UNSIGNED(0x00ffffff)) | ((Y) << 24)) |
---|
| 572 | |
---|
| 573 | |
---|
| 574 | /* Exception Vector Base Address Register */ |
---|
| 575 | #define OR1K_SPR_SYS_EVBAR_INDEX OR1K_UNSIGNED(0x00b) |
---|
| 576 | #define OR1K_SPR_SYS_EVBAR_ADDR OR1K_UNSIGNED(0x000b) |
---|
| 577 | |
---|
| 578 | /* Exception Vector Base Address */ |
---|
| 579 | #define OR1K_SPR_SYS_EVBAR_EVBA_LSB 13 |
---|
| 580 | #define OR1K_SPR_SYS_EVBAR_EVBA_MSB 31 |
---|
| 581 | #define OR1K_SPR_SYS_EVBAR_EVBA_BITS 19 |
---|
| 582 | #define OR1K_SPR_SYS_EVBAR_EVBA_MASK OR1K_UNSIGNED(0xffffe000) |
---|
| 583 | #define OR1K_SPR_SYS_EVBAR_EVBA_GET(X) (((X) >> 13) & OR1K_UNSIGNED(0x0007ffff)) |
---|
| 584 | #define OR1K_SPR_SYS_EVBAR_EVBA_SET(X, Y) (((X) & OR1K_UNSIGNED(0x00001fff)) | ((Y) << 13)) |
---|
| 585 | |
---|
| 586 | |
---|
| 587 | /* Arithmetic Exception Control Register */ |
---|
| 588 | #define OR1K_SPR_SYS_AECR_INDEX OR1K_UNSIGNED(0x00c) |
---|
| 589 | #define OR1K_SPR_SYS_AECR_ADDR OR1K_UNSIGNED(0x000c) |
---|
| 590 | |
---|
| 591 | /* Carry on Add Exception Enabled */ |
---|
| 592 | #define OR1K_SPR_SYS_AECR_CYADDE_OFFSET 0 |
---|
| 593 | #define OR1K_SPR_SYS_AECR_CYADDE_MASK 0x00000001 |
---|
| 594 | #define OR1K_SPR_SYS_AECR_CYADDE_GET(X) (((X) >> 0) & 0x1) |
---|
| 595 | #define OR1K_SPR_SYS_AECR_CYADDE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 596 | |
---|
| 597 | /* Overflow on Add Exception Enabled */ |
---|
| 598 | #define OR1K_SPR_SYS_AECR_OVADDE_OFFSET 1 |
---|
| 599 | #define OR1K_SPR_SYS_AECR_OVADDE_MASK 0x00000002 |
---|
| 600 | #define OR1K_SPR_SYS_AECR_OVADDE_GET(X) (((X) >> 1) & 0x1) |
---|
| 601 | #define OR1K_SPR_SYS_AECR_OVADDE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffd)) | ((!!(Y)) << 1)) |
---|
| 602 | |
---|
| 603 | /* Carry on Multiply Exception Enabled */ |
---|
| 604 | #define OR1K_SPR_SYS_AECR_CYMULE_OFFSET 2 |
---|
| 605 | #define OR1K_SPR_SYS_AECR_CYMULE_MASK 0x00000004 |
---|
| 606 | #define OR1K_SPR_SYS_AECR_CYMULE_GET(X) (((X) >> 2) & 0x1) |
---|
| 607 | #define OR1K_SPR_SYS_AECR_CYMULE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffb)) | ((!!(Y)) << 2)) |
---|
| 608 | |
---|
| 609 | /* Overflow on Multiply Exception Enabled */ |
---|
| 610 | #define OR1K_SPR_SYS_AECR_OVMULE_OFFSET 3 |
---|
| 611 | #define OR1K_SPR_SYS_AECR_OVMULE_MASK 0x00000008 |
---|
| 612 | #define OR1K_SPR_SYS_AECR_OVMULE_GET(X) (((X) >> 3) & 0x1) |
---|
| 613 | #define OR1K_SPR_SYS_AECR_OVMULE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff7)) | ((!!(Y)) << 3)) |
---|
| 614 | |
---|
| 615 | /* Divide by Zero Exception Enabled */ |
---|
| 616 | #define OR1K_SPR_SYS_AECR_DBZE_OFFSET 4 |
---|
| 617 | #define OR1K_SPR_SYS_AECR_DBZE_MASK 0x00000010 |
---|
| 618 | #define OR1K_SPR_SYS_AECR_DBZE_GET(X) (((X) >> 4) & 0x1) |
---|
| 619 | #define OR1K_SPR_SYS_AECR_DBZE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffef)) | ((!!(Y)) << 4)) |
---|
| 620 | |
---|
| 621 | /* Carry on MAC Addition Exception Enabled */ |
---|
| 622 | #define OR1K_SPR_SYS_AECR_CYMACADDE_OFFSET 5 |
---|
| 623 | #define OR1K_SPR_SYS_AECR_CYMACADDE_MASK 0x00000020 |
---|
| 624 | #define OR1K_SPR_SYS_AECR_CYMACADDE_GET(X) (((X) >> 5) & 0x1) |
---|
| 625 | #define OR1K_SPR_SYS_AECR_CYMACADDE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 626 | |
---|
| 627 | /* Overflow on MAC Addition Exception Enabled */ |
---|
| 628 | #define OR1K_SPR_SYS_AECR_OVMACADDE_OFFSET 6 |
---|
| 629 | #define OR1K_SPR_SYS_AECR_OVMACADDE_MASK 0x00000040 |
---|
| 630 | #define OR1K_SPR_SYS_AECR_OVMACADDE_GET(X) (((X) >> 6) & 0x1) |
---|
| 631 | #define OR1K_SPR_SYS_AECR_OVMACADDE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6)) |
---|
| 632 | |
---|
| 633 | |
---|
| 634 | /* Arithmetic Exception Status Register */ |
---|
| 635 | #define OR1K_SPR_SYS_AESR_INDEX OR1K_UNSIGNED(0x00d) |
---|
| 636 | #define OR1K_SPR_SYS_AESR_ADDR OR1K_UNSIGNED(0x000d) |
---|
| 637 | |
---|
| 638 | /* Carry on Add Exception */ |
---|
| 639 | #define OR1K_SPR_SYS_AESR_CYADDE_OFFSET 0 |
---|
| 640 | #define OR1K_SPR_SYS_AESR_CYADDE_MASK 0x00000001 |
---|
| 641 | #define OR1K_SPR_SYS_AESR_CYADDE_GET(X) (((X) >> 0) & 0x1) |
---|
| 642 | #define OR1K_SPR_SYS_AESR_CYADDE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 643 | |
---|
| 644 | /* Overflow on Add Exception */ |
---|
| 645 | #define OR1K_SPR_SYS_AESR_OVADDE_OFFSET 1 |
---|
| 646 | #define OR1K_SPR_SYS_AESR_OVADDE_MASK 0x00000002 |
---|
| 647 | #define OR1K_SPR_SYS_AESR_OVADDE_GET(X) (((X) >> 1) & 0x1) |
---|
| 648 | #define OR1K_SPR_SYS_AESR_OVADDE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffd)) | ((!!(Y)) << 1)) |
---|
| 649 | |
---|
| 650 | /* Carry on Multiply Exception */ |
---|
| 651 | #define OR1K_SPR_SYS_AESR_CYMULE_OFFSET 2 |
---|
| 652 | #define OR1K_SPR_SYS_AESR_CYMULE_MASK 0x00000004 |
---|
| 653 | #define OR1K_SPR_SYS_AESR_CYMULE_GET(X) (((X) >> 2) & 0x1) |
---|
| 654 | #define OR1K_SPR_SYS_AESR_CYMULE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffb)) | ((!!(Y)) << 2)) |
---|
| 655 | |
---|
| 656 | /* Overflow on Multiply Exception */ |
---|
| 657 | #define OR1K_SPR_SYS_AESR_OVMULE_OFFSET 3 |
---|
| 658 | #define OR1K_SPR_SYS_AESR_OVMULE_MASK 0x00000008 |
---|
| 659 | #define OR1K_SPR_SYS_AESR_OVMULE_GET(X) (((X) >> 3) & 0x1) |
---|
| 660 | #define OR1K_SPR_SYS_AESR_OVMULE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff7)) | ((!!(Y)) << 3)) |
---|
| 661 | |
---|
| 662 | /* Divide by Zero Exception */ |
---|
| 663 | #define OR1K_SPR_SYS_AESR_DBZE_OFFSET 4 |
---|
| 664 | #define OR1K_SPR_SYS_AESR_DBZE_MASK 0x00000010 |
---|
| 665 | #define OR1K_SPR_SYS_AESR_DBZE_GET(X) (((X) >> 4) & 0x1) |
---|
| 666 | #define OR1K_SPR_SYS_AESR_DBZE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffef)) | ((!!(Y)) << 4)) |
---|
| 667 | |
---|
| 668 | /* Carry on MAC Addition Exception */ |
---|
| 669 | #define OR1K_SPR_SYS_AESR_CYMACADDE_OFFSET 5 |
---|
| 670 | #define OR1K_SPR_SYS_AESR_CYMACADDE_MASK 0x00000020 |
---|
| 671 | #define OR1K_SPR_SYS_AESR_CYMACADDE_GET(X) (((X) >> 5) & 0x1) |
---|
| 672 | #define OR1K_SPR_SYS_AESR_CYMACADDE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 673 | |
---|
| 674 | /* Overflow on MAC Addition Exception */ |
---|
| 675 | #define OR1K_SPR_SYS_AESR_OVMACADDE_OFFSET 6 |
---|
| 676 | #define OR1K_SPR_SYS_AESR_OVMACADDE_MASK 0x00000040 |
---|
| 677 | #define OR1K_SPR_SYS_AESR_OVMACADDE_GET(X) (((X) >> 6) & 0x1) |
---|
| 678 | #define OR1K_SPR_SYS_AESR_OVMACADDE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6)) |
---|
| 679 | |
---|
| 680 | |
---|
| 681 | /* Next Program Counter */ |
---|
| 682 | #define OR1K_SPR_SYS_NPC_INDEX OR1K_UNSIGNED(0x010) |
---|
| 683 | #define OR1K_SPR_SYS_NPC_ADDR OR1K_UNSIGNED(0x0010) |
---|
| 684 | |
---|
| 685 | |
---|
| 686 | /* Supervision Register */ |
---|
| 687 | #define OR1K_SPR_SYS_SR_INDEX OR1K_UNSIGNED(0x011) |
---|
| 688 | #define OR1K_SPR_SYS_SR_ADDR OR1K_UNSIGNED(0x0011) |
---|
| 689 | |
---|
| 690 | /* Supervisor Mode */ |
---|
| 691 | #define OR1K_SPR_SYS_SR_SM_OFFSET 0 |
---|
| 692 | #define OR1K_SPR_SYS_SR_SM_MASK 0x00000001 |
---|
| 693 | #define OR1K_SPR_SYS_SR_SM_GET(X) (((X) >> 0) & 0x1) |
---|
| 694 | #define OR1K_SPR_SYS_SR_SM_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 695 | |
---|
| 696 | /* Tick Timer Exception Enabled */ |
---|
| 697 | #define OR1K_SPR_SYS_SR_TEE_OFFSET 1 |
---|
| 698 | #define OR1K_SPR_SYS_SR_TEE_MASK 0x00000002 |
---|
| 699 | #define OR1K_SPR_SYS_SR_TEE_GET(X) (((X) >> 1) & 0x1) |
---|
| 700 | #define OR1K_SPR_SYS_SR_TEE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffd)) | ((!!(Y)) << 1)) |
---|
| 701 | |
---|
| 702 | /* Interrupt Exception Enabled */ |
---|
| 703 | #define OR1K_SPR_SYS_SR_IEE_OFFSET 2 |
---|
| 704 | #define OR1K_SPR_SYS_SR_IEE_MASK 0x00000004 |
---|
| 705 | #define OR1K_SPR_SYS_SR_IEE_GET(X) (((X) >> 2) & 0x1) |
---|
| 706 | #define OR1K_SPR_SYS_SR_IEE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffb)) | ((!!(Y)) << 2)) |
---|
| 707 | |
---|
| 708 | /* Data Cache Enabled */ |
---|
| 709 | #define OR1K_SPR_SYS_SR_DCE_OFFSET 3 |
---|
| 710 | #define OR1K_SPR_SYS_SR_DCE_MASK 0x00000008 |
---|
| 711 | #define OR1K_SPR_SYS_SR_DCE_GET(X) (((X) >> 3) & 0x1) |
---|
| 712 | #define OR1K_SPR_SYS_SR_DCE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff7)) | ((!!(Y)) << 3)) |
---|
| 713 | |
---|
| 714 | /* Instruction Cache Enabled */ |
---|
| 715 | #define OR1K_SPR_SYS_SR_ICE_OFFSET 4 |
---|
| 716 | #define OR1K_SPR_SYS_SR_ICE_MASK 0x00000010 |
---|
| 717 | #define OR1K_SPR_SYS_SR_ICE_GET(X) (((X) >> 4) & 0x1) |
---|
| 718 | #define OR1K_SPR_SYS_SR_ICE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffef)) | ((!!(Y)) << 4)) |
---|
| 719 | |
---|
| 720 | /* Data MMU Enabled */ |
---|
| 721 | #define OR1K_SPR_SYS_SR_DME_OFFSET 5 |
---|
| 722 | #define OR1K_SPR_SYS_SR_DME_MASK 0x00000020 |
---|
| 723 | #define OR1K_SPR_SYS_SR_DME_GET(X) (((X) >> 5) & 0x1) |
---|
| 724 | #define OR1K_SPR_SYS_SR_DME_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 725 | |
---|
| 726 | /* Instruction MMU Enabled */ |
---|
| 727 | #define OR1K_SPR_SYS_SR_IME_OFFSET 6 |
---|
| 728 | #define OR1K_SPR_SYS_SR_IME_MASK 0x00000040 |
---|
| 729 | #define OR1K_SPR_SYS_SR_IME_GET(X) (((X) >> 6) & 0x1) |
---|
| 730 | #define OR1K_SPR_SYS_SR_IME_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6)) |
---|
| 731 | |
---|
| 732 | /* Little Endian Enabled */ |
---|
| 733 | #define OR1K_SPR_SYS_SR_LEE_OFFSET 7 |
---|
| 734 | #define OR1K_SPR_SYS_SR_LEE_MASK 0x00000080 |
---|
| 735 | #define OR1K_SPR_SYS_SR_LEE_GET(X) (((X) >> 7) & 0x1) |
---|
| 736 | #define OR1K_SPR_SYS_SR_LEE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7)) |
---|
| 737 | |
---|
| 738 | /* CID Enable */ |
---|
| 739 | #define OR1K_SPR_SYS_SR_CE_OFFSET 8 |
---|
| 740 | #define OR1K_SPR_SYS_SR_CE_MASK 0x00000100 |
---|
| 741 | #define OR1K_SPR_SYS_SR_CE_GET(X) (((X) >> 8) & 0x1) |
---|
| 742 | #define OR1K_SPR_SYS_SR_CE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffeff)) | ((!!(Y)) << 8)) |
---|
| 743 | |
---|
| 744 | /* Flag */ |
---|
| 745 | #define OR1K_SPR_SYS_SR_F_OFFSET 9 |
---|
| 746 | #define OR1K_SPR_SYS_SR_F_MASK 0x00000200 |
---|
| 747 | #define OR1K_SPR_SYS_SR_F_GET(X) (((X) >> 9) & 0x1) |
---|
| 748 | #define OR1K_SPR_SYS_SR_F_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffdff)) | ((!!(Y)) << 9)) |
---|
| 749 | |
---|
| 750 | /* Carry */ |
---|
| 751 | #define OR1K_SPR_SYS_SR_CY_OFFSET 10 |
---|
| 752 | #define OR1K_SPR_SYS_SR_CY_MASK 0x00000400 |
---|
| 753 | #define OR1K_SPR_SYS_SR_CY_GET(X) (((X) >> 10) & 0x1) |
---|
| 754 | #define OR1K_SPR_SYS_SR_CY_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffbff)) | ((!!(Y)) << 10)) |
---|
| 755 | |
---|
| 756 | /* Overflow */ |
---|
| 757 | #define OR1K_SPR_SYS_SR_OV_OFFSET 11 |
---|
| 758 | #define OR1K_SPR_SYS_SR_OV_MASK 0x00000800 |
---|
| 759 | #define OR1K_SPR_SYS_SR_OV_GET(X) (((X) >> 11) & 0x1) |
---|
| 760 | #define OR1K_SPR_SYS_SR_OV_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffff7ff)) | ((!!(Y)) << 11)) |
---|
| 761 | |
---|
| 762 | /* Overflow Exception Enabled */ |
---|
| 763 | #define OR1K_SPR_SYS_SR_OVE_OFFSET 12 |
---|
| 764 | #define OR1K_SPR_SYS_SR_OVE_MASK 0x00001000 |
---|
| 765 | #define OR1K_SPR_SYS_SR_OVE_GET(X) (((X) >> 12) & 0x1) |
---|
| 766 | #define OR1K_SPR_SYS_SR_OVE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffefff)) | ((!!(Y)) << 12)) |
---|
| 767 | |
---|
| 768 | /* Delay-slot Exception */ |
---|
| 769 | #define OR1K_SPR_SYS_SR_DSX_OFFSET 13 |
---|
| 770 | #define OR1K_SPR_SYS_SR_DSX_MASK 0x00002000 |
---|
| 771 | #define OR1K_SPR_SYS_SR_DSX_GET(X) (((X) >> 13) & 0x1) |
---|
| 772 | #define OR1K_SPR_SYS_SR_DSX_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffdfff)) | ((!!(Y)) << 13)) |
---|
| 773 | |
---|
| 774 | /* Exception Prefix High */ |
---|
| 775 | #define OR1K_SPR_SYS_SR_EPH_OFFSET 14 |
---|
| 776 | #define OR1K_SPR_SYS_SR_EPH_MASK 0x00004000 |
---|
| 777 | #define OR1K_SPR_SYS_SR_EPH_GET(X) (((X) >> 14) & 0x1) |
---|
| 778 | #define OR1K_SPR_SYS_SR_EPH_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffbfff)) | ((!!(Y)) << 14)) |
---|
| 779 | |
---|
| 780 | /* Fixed One */ |
---|
| 781 | #define OR1K_SPR_SYS_SR_FO_OFFSET 15 |
---|
| 782 | #define OR1K_SPR_SYS_SR_FO_MASK 0x00008000 |
---|
| 783 | #define OR1K_SPR_SYS_SR_FO_GET(X) (((X) >> 15) & 0x1) |
---|
| 784 | #define OR1K_SPR_SYS_SR_FO_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffff7fff)) | ((!!(Y)) << 15)) |
---|
| 785 | |
---|
| 786 | /* SPR User Mode Read Access */ |
---|
| 787 | #define OR1K_SPR_SYS_SR_SUMRA_OFFSET 16 |
---|
| 788 | #define OR1K_SPR_SYS_SR_SUMRA_MASK 0x00010000 |
---|
| 789 | #define OR1K_SPR_SYS_SR_SUMRA_GET(X) (((X) >> 16) & 0x1) |
---|
| 790 | #define OR1K_SPR_SYS_SR_SUMRA_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffeffff)) | ((!!(Y)) << 16)) |
---|
| 791 | |
---|
| 792 | /* Context ID */ |
---|
| 793 | #define OR1K_SPR_SYS_SR_CID_LSB 28 |
---|
| 794 | #define OR1K_SPR_SYS_SR_CID_MSB 31 |
---|
| 795 | #define OR1K_SPR_SYS_SR_CID_BITS 4 |
---|
| 796 | #define OR1K_SPR_SYS_SR_CID_MASK OR1K_UNSIGNED(0xf0000000) |
---|
| 797 | #define OR1K_SPR_SYS_SR_CID_GET(X) (((X) >> 28) & OR1K_UNSIGNED(0x0000000f)) |
---|
| 798 | #define OR1K_SPR_SYS_SR_CID_SET(X, Y) (((X) & OR1K_UNSIGNED(0x0fffffff)) | ((Y) << 28)) |
---|
| 799 | |
---|
| 800 | |
---|
| 801 | /* Previous Program Counter */ |
---|
| 802 | #define OR1K_SPR_SYS_PPC_INDEX OR1K_UNSIGNED(0x012) |
---|
| 803 | #define OR1K_SPR_SYS_PPC_ADDR OR1K_UNSIGNED(0x0012) |
---|
| 804 | |
---|
| 805 | |
---|
| 806 | /* Floating Point Control Status Register */ |
---|
| 807 | #define OR1K_SPR_SYS_FPCSR_INDEX OR1K_UNSIGNED(0x014) |
---|
| 808 | #define OR1K_SPR_SYS_FPCSR_ADDR OR1K_UNSIGNED(0x0014) |
---|
| 809 | |
---|
| 810 | /* Floating Point Exception Enabled */ |
---|
| 811 | #define OR1K_SPR_SYS_FPCSR_FPEE_OFFSET 0 |
---|
| 812 | #define OR1K_SPR_SYS_FPCSR_FPEE_MASK 0x00000001 |
---|
| 813 | #define OR1K_SPR_SYS_FPCSR_FPEE_GET(X) (((X) >> 0) & 0x1) |
---|
| 814 | #define OR1K_SPR_SYS_FPCSR_FPEE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 815 | |
---|
| 816 | /* Rounding Mode */ |
---|
| 817 | #define OR1K_SPR_SYS_FPCSR_RM_LSB 1 |
---|
| 818 | #define OR1K_SPR_SYS_FPCSR_RM_MSB 2 |
---|
| 819 | #define OR1K_SPR_SYS_FPCSR_RM_BITS 2 |
---|
| 820 | #define OR1K_SPR_SYS_FPCSR_RM_MASK OR1K_UNSIGNED(0x00000006) |
---|
| 821 | #define OR1K_SPR_SYS_FPCSR_RM_GET(X) (((X) >> 1) & OR1K_UNSIGNED(0x00000003)) |
---|
| 822 | #define OR1K_SPR_SYS_FPCSR_RM_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff9)) | ((Y) << 1)) |
---|
| 823 | |
---|
| 824 | /* Round to nearest */ |
---|
| 825 | #define OR1K_SPR_SYS_FPCSR_RM_NEAREST 0 |
---|
| 826 | /* Round to zero */ |
---|
| 827 | #define OR1K_SPR_SYS_FPCSR_RM_ZERO 1 |
---|
| 828 | /* Round to infinity+ */ |
---|
| 829 | #define OR1K_SPR_SYS_FPCSR_RM_INFPLUS 2 |
---|
| 830 | /* Round to infinity- */ |
---|
| 831 | #define OR1K_SPR_SYS_FPCSR_RM_INFMINUS 3 |
---|
| 832 | /* Overflow Flag */ |
---|
| 833 | #define OR1K_SPR_SYS_FPCSR_OVF_OFFSET 3 |
---|
| 834 | #define OR1K_SPR_SYS_FPCSR_OVF_MASK 0x00000008 |
---|
| 835 | #define OR1K_SPR_SYS_FPCSR_OVF_GET(X) (((X) >> 3) & 0x1) |
---|
| 836 | #define OR1K_SPR_SYS_FPCSR_OVF_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff7)) | ((!!(Y)) << 3)) |
---|
| 837 | |
---|
| 838 | /* Underflow Flag */ |
---|
| 839 | #define OR1K_SPR_SYS_FPCSR_UNF_OFFSET 4 |
---|
| 840 | #define OR1K_SPR_SYS_FPCSR_UNF_MASK 0x00000010 |
---|
| 841 | #define OR1K_SPR_SYS_FPCSR_UNF_GET(X) (((X) >> 4) & 0x1) |
---|
| 842 | #define OR1K_SPR_SYS_FPCSR_UNF_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffef)) | ((!!(Y)) << 4)) |
---|
| 843 | |
---|
| 844 | /* SNAN Flag */ |
---|
| 845 | #define OR1K_SPR_SYS_FPCSR_SNF_OFFSET 5 |
---|
| 846 | #define OR1K_SPR_SYS_FPCSR_SNF_MASK 0x00000020 |
---|
| 847 | #define OR1K_SPR_SYS_FPCSR_SNF_GET(X) (((X) >> 5) & 0x1) |
---|
| 848 | #define OR1K_SPR_SYS_FPCSR_SNF_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 849 | |
---|
| 850 | /* QNAN Flag */ |
---|
| 851 | #define OR1K_SPR_SYS_FPCSR_QNF_OFFSET 6 |
---|
| 852 | #define OR1K_SPR_SYS_FPCSR_QNF_MASK 0x00000040 |
---|
| 853 | #define OR1K_SPR_SYS_FPCSR_QNF_GET(X) (((X) >> 6) & 0x1) |
---|
| 854 | #define OR1K_SPR_SYS_FPCSR_QNF_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6)) |
---|
| 855 | |
---|
| 856 | /* Zero Flag */ |
---|
| 857 | #define OR1K_SPR_SYS_FPCSR_ZF_OFFSET 7 |
---|
| 858 | #define OR1K_SPR_SYS_FPCSR_ZF_MASK 0x00000080 |
---|
| 859 | #define OR1K_SPR_SYS_FPCSR_ZF_GET(X) (((X) >> 7) & 0x1) |
---|
| 860 | #define OR1K_SPR_SYS_FPCSR_ZF_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7)) |
---|
| 861 | |
---|
| 862 | /* Inexact Flag */ |
---|
| 863 | #define OR1K_SPR_SYS_FPCSR_IXF_OFFSET 8 |
---|
| 864 | #define OR1K_SPR_SYS_FPCSR_IXF_MASK 0x00000100 |
---|
| 865 | #define OR1K_SPR_SYS_FPCSR_IXF_GET(X) (((X) >> 8) & 0x1) |
---|
| 866 | #define OR1K_SPR_SYS_FPCSR_IXF_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffeff)) | ((!!(Y)) << 8)) |
---|
| 867 | |
---|
| 868 | /* Invalid Flag */ |
---|
| 869 | #define OR1K_SPR_SYS_FPCSR_IVF_OFFSET 9 |
---|
| 870 | #define OR1K_SPR_SYS_FPCSR_IVF_MASK 0x00000200 |
---|
| 871 | #define OR1K_SPR_SYS_FPCSR_IVF_GET(X) (((X) >> 9) & 0x1) |
---|
| 872 | #define OR1K_SPR_SYS_FPCSR_IVF_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffdff)) | ((!!(Y)) << 9)) |
---|
| 873 | |
---|
| 874 | /* Infinity Flag */ |
---|
| 875 | #define OR1K_SPR_SYS_FPCSR_INF_OFFSET 10 |
---|
| 876 | #define OR1K_SPR_SYS_FPCSR_INF_MASK 0x00000400 |
---|
| 877 | #define OR1K_SPR_SYS_FPCSR_INF_GET(X) (((X) >> 10) & 0x1) |
---|
| 878 | #define OR1K_SPR_SYS_FPCSR_INF_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffbff)) | ((!!(Y)) << 10)) |
---|
| 879 | |
---|
| 880 | /* Divide by Zero Flag */ |
---|
| 881 | #define OR1K_SPR_SYS_FPCSR_DZF_OFFSET 11 |
---|
| 882 | #define OR1K_SPR_SYS_FPCSR_DZF_MASK 0x00000800 |
---|
| 883 | #define OR1K_SPR_SYS_FPCSR_DZF_GET(X) (((X) >> 11) & 0x1) |
---|
| 884 | #define OR1K_SPR_SYS_FPCSR_DZF_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffff7ff)) | ((!!(Y)) << 11)) |
---|
| 885 | |
---|
| 886 | |
---|
| 887 | /* Implementation-specific Registers */ |
---|
| 888 | #define OR1K_SPR_SYS_ISR_BASE OR1K_UNSIGNED(0x015) |
---|
| 889 | #define OR1K_SPR_SYS_ISR_COUNT OR1K_UNSIGNED(0x008) |
---|
| 890 | #define OR1K_SPR_SYS_ISR_STEP OR1K_UNSIGNED(0x001) |
---|
| 891 | #define OR1K_SPR_SYS_ISR_INDEX(N) (OR1K_SPR_SYS_ISR_BASE + ((N) * OR1K_SPR_SYS_ISR_STEP)) |
---|
| 892 | #define OR1K_SPR_SYS_ISR_ADDR(N) ((OR1K_SPR_SYS_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_SYS_ISR_INDEX(N)) |
---|
| 893 | |
---|
| 894 | |
---|
| 895 | /* Exception PC Registers */ |
---|
| 896 | #define OR1K_SPR_SYS_EPCR_BASE OR1K_UNSIGNED(0x020) |
---|
| 897 | #define OR1K_SPR_SYS_EPCR_COUNT OR1K_UNSIGNED(0x010) |
---|
| 898 | #define OR1K_SPR_SYS_EPCR_STEP OR1K_UNSIGNED(0x001) |
---|
| 899 | #define OR1K_SPR_SYS_EPCR_INDEX(N) (OR1K_SPR_SYS_EPCR_BASE + ((N) * OR1K_SPR_SYS_EPCR_STEP)) |
---|
| 900 | #define OR1K_SPR_SYS_EPCR_ADDR(N) ((OR1K_SPR_SYS_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_SYS_EPCR_INDEX(N)) |
---|
| 901 | |
---|
| 902 | |
---|
| 903 | /* Exception Effective Address Registers */ |
---|
| 904 | #define OR1K_SPR_SYS_EEAR_BASE OR1K_UNSIGNED(0x030) |
---|
| 905 | #define OR1K_SPR_SYS_EEAR_COUNT OR1K_UNSIGNED(0x010) |
---|
| 906 | #define OR1K_SPR_SYS_EEAR_STEP OR1K_UNSIGNED(0x001) |
---|
| 907 | #define OR1K_SPR_SYS_EEAR_INDEX(N) (OR1K_SPR_SYS_EEAR_BASE + ((N) * OR1K_SPR_SYS_EEAR_STEP)) |
---|
| 908 | #define OR1K_SPR_SYS_EEAR_ADDR(N) ((OR1K_SPR_SYS_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_SYS_EEAR_INDEX(N)) |
---|
| 909 | |
---|
| 910 | |
---|
| 911 | /* Exception Supervision Registers */ |
---|
| 912 | #define OR1K_SPR_SYS_ESR_BASE OR1K_UNSIGNED(0x040) |
---|
| 913 | #define OR1K_SPR_SYS_ESR_COUNT OR1K_UNSIGNED(0x010) |
---|
| 914 | #define OR1K_SPR_SYS_ESR_STEP OR1K_UNSIGNED(0x001) |
---|
| 915 | #define OR1K_SPR_SYS_ESR_INDEX(N) (OR1K_SPR_SYS_ESR_BASE + ((N) * OR1K_SPR_SYS_ESR_STEP)) |
---|
| 916 | #define OR1K_SPR_SYS_ESR_ADDR(N) ((OR1K_SPR_SYS_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_SYS_ESR_INDEX(N)) |
---|
| 917 | |
---|
| 918 | /* Supervisor Mode */ |
---|
| 919 | #define OR1K_SPR_SYS_ESR_SM_OFFSET 0 |
---|
| 920 | #define OR1K_SPR_SYS_ESR_SM_MASK 0x00000001 |
---|
| 921 | #define OR1K_SPR_SYS_ESR_SM_GET(X) (((X) >> 0) & 0x1) |
---|
| 922 | #define OR1K_SPR_SYS_ESR_SM_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 923 | |
---|
| 924 | /* Tick Timer Exception Enabled */ |
---|
| 925 | #define OR1K_SPR_SYS_ESR_TEE_OFFSET 1 |
---|
| 926 | #define OR1K_SPR_SYS_ESR_TEE_MASK 0x00000002 |
---|
| 927 | #define OR1K_SPR_SYS_ESR_TEE_GET(X) (((X) >> 1) & 0x1) |
---|
| 928 | #define OR1K_SPR_SYS_ESR_TEE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffd)) | ((!!(Y)) << 1)) |
---|
| 929 | |
---|
| 930 | /* Interrupt Exception Enabled */ |
---|
| 931 | #define OR1K_SPR_SYS_ESR_IEE_OFFSET 2 |
---|
| 932 | #define OR1K_SPR_SYS_ESR_IEE_MASK 0x00000004 |
---|
| 933 | #define OR1K_SPR_SYS_ESR_IEE_GET(X) (((X) >> 2) & 0x1) |
---|
| 934 | #define OR1K_SPR_SYS_ESR_IEE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffb)) | ((!!(Y)) << 2)) |
---|
| 935 | |
---|
| 936 | /* Data Cache Enabled */ |
---|
| 937 | #define OR1K_SPR_SYS_ESR_DCE_OFFSET 3 |
---|
| 938 | #define OR1K_SPR_SYS_ESR_DCE_MASK 0x00000008 |
---|
| 939 | #define OR1K_SPR_SYS_ESR_DCE_GET(X) (((X) >> 3) & 0x1) |
---|
| 940 | #define OR1K_SPR_SYS_ESR_DCE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff7)) | ((!!(Y)) << 3)) |
---|
| 941 | |
---|
| 942 | /* Instruction Cache Enabled */ |
---|
| 943 | #define OR1K_SPR_SYS_ESR_ICE_OFFSET 4 |
---|
| 944 | #define OR1K_SPR_SYS_ESR_ICE_MASK 0x00000010 |
---|
| 945 | #define OR1K_SPR_SYS_ESR_ICE_GET(X) (((X) >> 4) & 0x1) |
---|
| 946 | #define OR1K_SPR_SYS_ESR_ICE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffef)) | ((!!(Y)) << 4)) |
---|
| 947 | |
---|
| 948 | /* Data MMU Enabled */ |
---|
| 949 | #define OR1K_SPR_SYS_ESR_DME_OFFSET 5 |
---|
| 950 | #define OR1K_SPR_SYS_ESR_DME_MASK 0x00000020 |
---|
| 951 | #define OR1K_SPR_SYS_ESR_DME_GET(X) (((X) >> 5) & 0x1) |
---|
| 952 | #define OR1K_SPR_SYS_ESR_DME_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 953 | |
---|
| 954 | /* Instruction MMU Enabled */ |
---|
| 955 | #define OR1K_SPR_SYS_ESR_IME_OFFSET 6 |
---|
| 956 | #define OR1K_SPR_SYS_ESR_IME_MASK 0x00000040 |
---|
| 957 | #define OR1K_SPR_SYS_ESR_IME_GET(X) (((X) >> 6) & 0x1) |
---|
| 958 | #define OR1K_SPR_SYS_ESR_IME_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6)) |
---|
| 959 | |
---|
| 960 | /* Little Endian Enabled */ |
---|
| 961 | #define OR1K_SPR_SYS_ESR_LEE_OFFSET 7 |
---|
| 962 | #define OR1K_SPR_SYS_ESR_LEE_MASK 0x00000080 |
---|
| 963 | #define OR1K_SPR_SYS_ESR_LEE_GET(X) (((X) >> 7) & 0x1) |
---|
| 964 | #define OR1K_SPR_SYS_ESR_LEE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7)) |
---|
| 965 | |
---|
| 966 | /* CID Enable */ |
---|
| 967 | #define OR1K_SPR_SYS_ESR_CE_OFFSET 8 |
---|
| 968 | #define OR1K_SPR_SYS_ESR_CE_MASK 0x00000100 |
---|
| 969 | #define OR1K_SPR_SYS_ESR_CE_GET(X) (((X) >> 8) & 0x1) |
---|
| 970 | #define OR1K_SPR_SYS_ESR_CE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffeff)) | ((!!(Y)) << 8)) |
---|
| 971 | |
---|
| 972 | /* Flag */ |
---|
| 973 | #define OR1K_SPR_SYS_ESR_F_OFFSET 9 |
---|
| 974 | #define OR1K_SPR_SYS_ESR_F_MASK 0x00000200 |
---|
| 975 | #define OR1K_SPR_SYS_ESR_F_GET(X) (((X) >> 9) & 0x1) |
---|
| 976 | #define OR1K_SPR_SYS_ESR_F_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffdff)) | ((!!(Y)) << 9)) |
---|
| 977 | |
---|
| 978 | /* Carry */ |
---|
| 979 | #define OR1K_SPR_SYS_ESR_CY_OFFSET 10 |
---|
| 980 | #define OR1K_SPR_SYS_ESR_CY_MASK 0x00000400 |
---|
| 981 | #define OR1K_SPR_SYS_ESR_CY_GET(X) (((X) >> 10) & 0x1) |
---|
| 982 | #define OR1K_SPR_SYS_ESR_CY_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffbff)) | ((!!(Y)) << 10)) |
---|
| 983 | |
---|
| 984 | /* Overflow */ |
---|
| 985 | #define OR1K_SPR_SYS_ESR_OV_OFFSET 11 |
---|
| 986 | #define OR1K_SPR_SYS_ESR_OV_MASK 0x00000800 |
---|
| 987 | #define OR1K_SPR_SYS_ESR_OV_GET(X) (((X) >> 11) & 0x1) |
---|
| 988 | #define OR1K_SPR_SYS_ESR_OV_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffff7ff)) | ((!!(Y)) << 11)) |
---|
| 989 | |
---|
| 990 | /* Overflow Exception Enabled */ |
---|
| 991 | #define OR1K_SPR_SYS_ESR_OVE_OFFSET 12 |
---|
| 992 | #define OR1K_SPR_SYS_ESR_OVE_MASK 0x00001000 |
---|
| 993 | #define OR1K_SPR_SYS_ESR_OVE_GET(X) (((X) >> 12) & 0x1) |
---|
| 994 | #define OR1K_SPR_SYS_ESR_OVE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffefff)) | ((!!(Y)) << 12)) |
---|
| 995 | |
---|
| 996 | /* Delay-slot Exception */ |
---|
| 997 | #define OR1K_SPR_SYS_ESR_DSX_OFFSET 13 |
---|
| 998 | #define OR1K_SPR_SYS_ESR_DSX_MASK 0x00002000 |
---|
| 999 | #define OR1K_SPR_SYS_ESR_DSX_GET(X) (((X) >> 13) & 0x1) |
---|
| 1000 | #define OR1K_SPR_SYS_ESR_DSX_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffdfff)) | ((!!(Y)) << 13)) |
---|
| 1001 | |
---|
| 1002 | /* Exception Prefix High */ |
---|
| 1003 | #define OR1K_SPR_SYS_ESR_EPH_OFFSET 14 |
---|
| 1004 | #define OR1K_SPR_SYS_ESR_EPH_MASK 0x00004000 |
---|
| 1005 | #define OR1K_SPR_SYS_ESR_EPH_GET(X) (((X) >> 14) & 0x1) |
---|
| 1006 | #define OR1K_SPR_SYS_ESR_EPH_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffbfff)) | ((!!(Y)) << 14)) |
---|
| 1007 | |
---|
| 1008 | /* Fixed One */ |
---|
| 1009 | #define OR1K_SPR_SYS_ESR_FO_OFFSET 15 |
---|
| 1010 | #define OR1K_SPR_SYS_ESR_FO_MASK 0x00008000 |
---|
| 1011 | #define OR1K_SPR_SYS_ESR_FO_GET(X) (((X) >> 15) & 0x1) |
---|
| 1012 | #define OR1K_SPR_SYS_ESR_FO_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffff7fff)) | ((!!(Y)) << 15)) |
---|
| 1013 | |
---|
| 1014 | /* SPR User Mode Read Access */ |
---|
| 1015 | #define OR1K_SPR_SYS_ESR_SUMRA_OFFSET 16 |
---|
| 1016 | #define OR1K_SPR_SYS_ESR_SUMRA_MASK 0x00010000 |
---|
| 1017 | #define OR1K_SPR_SYS_ESR_SUMRA_GET(X) (((X) >> 16) & 0x1) |
---|
| 1018 | #define OR1K_SPR_SYS_ESR_SUMRA_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffeffff)) | ((!!(Y)) << 16)) |
---|
| 1019 | |
---|
| 1020 | /* Context ID */ |
---|
| 1021 | #define OR1K_SPR_SYS_ESR_CID_LSB 28 |
---|
| 1022 | #define OR1K_SPR_SYS_ESR_CID_MSB 31 |
---|
| 1023 | #define OR1K_SPR_SYS_ESR_CID_BITS 4 |
---|
| 1024 | #define OR1K_SPR_SYS_ESR_CID_MASK OR1K_UNSIGNED(0xf0000000) |
---|
| 1025 | #define OR1K_SPR_SYS_ESR_CID_GET(X) (((X) >> 28) & OR1K_UNSIGNED(0x0000000f)) |
---|
| 1026 | #define OR1K_SPR_SYS_ESR_CID_SET(X, Y) (((X) & OR1K_UNSIGNED(0x0fffffff)) | ((Y) << 28)) |
---|
| 1027 | |
---|
| 1028 | |
---|
| 1029 | /* Core identifier (multicore) */ |
---|
| 1030 | #define OR1K_SPR_SYS_COREID_INDEX OR1K_UNSIGNED(0x080) |
---|
| 1031 | #define OR1K_SPR_SYS_COREID_ADDR OR1K_UNSIGNED(0x0080) |
---|
| 1032 | |
---|
| 1033 | |
---|
| 1034 | /* Number of cores (multicore) */ |
---|
| 1035 | #define OR1K_SPR_SYS_NUMCORES_INDEX OR1K_UNSIGNED(0x081) |
---|
| 1036 | #define OR1K_SPR_SYS_NUMCORES_ADDR OR1K_UNSIGNED(0x0081) |
---|
| 1037 | |
---|
| 1038 | |
---|
| 1039 | /* General Purpose Registers */ |
---|
| 1040 | #define OR1K_SPR_SYS_GPR_BASE OR1K_UNSIGNED(0x400) |
---|
| 1041 | #define OR1K_SPR_SYS_GPR_COUNT OR1K_UNSIGNED(0x100) |
---|
| 1042 | #define OR1K_SPR_SYS_GPR_STEP OR1K_UNSIGNED(0x001) |
---|
| 1043 | #define OR1K_SPR_SYS_GPR_INDEX(N) (OR1K_SPR_SYS_GPR_BASE + ((N) * OR1K_SPR_SYS_GPR_STEP)) |
---|
| 1044 | #define OR1K_SPR_SYS_GPR_ADDR(N) ((OR1K_SPR_SYS_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_SYS_GPR_INDEX(N)) |
---|
| 1045 | |
---|
| 1046 | |
---|
| 1047 | /******************/ |
---|
| 1048 | /* Data MMU Group */ |
---|
| 1049 | /******************/ |
---|
| 1050 | #define OR1K_SPR_DMMU_GROUP 0x01 |
---|
| 1051 | |
---|
| 1052 | /* Instruction MMU Control Register */ |
---|
| 1053 | #define OR1K_SPR_DMMU_DMMUCR_INDEX OR1K_UNSIGNED(0x000) |
---|
| 1054 | #define OR1K_SPR_DMMU_DMMUCR_ADDR OR1K_UNSIGNED(0x0800) |
---|
| 1055 | |
---|
| 1056 | /* DTLB Flush */ |
---|
| 1057 | #define OR1K_SPR_DMMU_DMMUCR_DTF_OFFSET 0 |
---|
| 1058 | #define OR1K_SPR_DMMU_DMMUCR_DTF_MASK 0x00000001 |
---|
| 1059 | #define OR1K_SPR_DMMU_DMMUCR_DTF_GET(X) (((X) >> 0) & 0x1) |
---|
| 1060 | #define OR1K_SPR_DMMU_DMMUCR_DTF_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 1061 | |
---|
| 1062 | /* Page Table Base Pointer */ |
---|
| 1063 | #define OR1K_SPR_DMMU_DMMUCR_PTBP_LSB 10 |
---|
| 1064 | #define OR1K_SPR_DMMU_DMMUCR_PTBP_MSB 31 |
---|
| 1065 | #define OR1K_SPR_DMMU_DMMUCR_PTBP_BITS 22 |
---|
| 1066 | #define OR1K_SPR_DMMU_DMMUCR_PTBP_MASK OR1K_UNSIGNED(0xfffffc00) |
---|
| 1067 | #define OR1K_SPR_DMMU_DMMUCR_PTBP_GET(X) (((X) >> 10) & OR1K_UNSIGNED(0x003fffff)) |
---|
| 1068 | #define OR1K_SPR_DMMU_DMMUCR_PTBP_SET(X, Y) (((X) & OR1K_UNSIGNED(0x000003ff)) | ((Y) << 10)) |
---|
| 1069 | |
---|
| 1070 | |
---|
| 1071 | /* Data MMU Protection Register */ |
---|
| 1072 | #define OR1K_SPR_DMMU_DMMUPR_INDEX OR1K_UNSIGNED(0x001) |
---|
| 1073 | #define OR1K_SPR_DMMU_DMMUPR_ADDR OR1K_UNSIGNED(0x0801) |
---|
| 1074 | |
---|
| 1075 | /* Supervisor Read Enable 1 */ |
---|
| 1076 | #define OR1K_SPR_DMMU_DMMUPR_SRE1_OFFSET 0 |
---|
| 1077 | #define OR1K_SPR_DMMU_DMMUPR_SRE1_MASK 0x00000001 |
---|
| 1078 | #define OR1K_SPR_DMMU_DMMUPR_SRE1_GET(X) (((X) >> 0) & 0x1) |
---|
| 1079 | #define OR1K_SPR_DMMU_DMMUPR_SRE1_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 1080 | |
---|
| 1081 | /* Supervisor Write Enable 1 */ |
---|
| 1082 | #define OR1K_SPR_DMMU_DMMUPR_SWE1_OFFSET 1 |
---|
| 1083 | #define OR1K_SPR_DMMU_DMMUPR_SWE1_MASK 0x00000002 |
---|
| 1084 | #define OR1K_SPR_DMMU_DMMUPR_SWE1_GET(X) (((X) >> 1) & 0x1) |
---|
| 1085 | #define OR1K_SPR_DMMU_DMMUPR_SWE1_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffd)) | ((!!(Y)) << 1)) |
---|
| 1086 | |
---|
| 1087 | /* User Read Enable 1 */ |
---|
| 1088 | #define OR1K_SPR_DMMU_DMMUPR_URE1_OFFSET 2 |
---|
| 1089 | #define OR1K_SPR_DMMU_DMMUPR_URE1_MASK 0x00000004 |
---|
| 1090 | #define OR1K_SPR_DMMU_DMMUPR_URE1_GET(X) (((X) >> 2) & 0x1) |
---|
| 1091 | #define OR1K_SPR_DMMU_DMMUPR_URE1_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffb)) | ((!!(Y)) << 2)) |
---|
| 1092 | |
---|
| 1093 | /* User Write Enable 1 */ |
---|
| 1094 | #define OR1K_SPR_DMMU_DMMUPR_UWE1_OFFSET 3 |
---|
| 1095 | #define OR1K_SPR_DMMU_DMMUPR_UWE1_MASK 0x00000008 |
---|
| 1096 | #define OR1K_SPR_DMMU_DMMUPR_UWE1_GET(X) (((X) >> 3) & 0x1) |
---|
| 1097 | #define OR1K_SPR_DMMU_DMMUPR_UWE1_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff7)) | ((!!(Y)) << 3)) |
---|
| 1098 | |
---|
| 1099 | /* Supervisor Read Enable 2 */ |
---|
| 1100 | #define OR1K_SPR_DMMU_DMMUPR_SRE2_OFFSET 4 |
---|
| 1101 | #define OR1K_SPR_DMMU_DMMUPR_SRE2_MASK 0x00000010 |
---|
| 1102 | #define OR1K_SPR_DMMU_DMMUPR_SRE2_GET(X) (((X) >> 4) & 0x1) |
---|
| 1103 | #define OR1K_SPR_DMMU_DMMUPR_SRE2_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffef)) | ((!!(Y)) << 4)) |
---|
| 1104 | |
---|
| 1105 | /* Supervisor Write Enable 2 */ |
---|
| 1106 | #define OR1K_SPR_DMMU_DMMUPR_SWE2_OFFSET 5 |
---|
| 1107 | #define OR1K_SPR_DMMU_DMMUPR_SWE2_MASK 0x00000020 |
---|
| 1108 | #define OR1K_SPR_DMMU_DMMUPR_SWE2_GET(X) (((X) >> 5) & 0x1) |
---|
| 1109 | #define OR1K_SPR_DMMU_DMMUPR_SWE2_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 1110 | |
---|
| 1111 | /* User Read Enable 2 */ |
---|
| 1112 | #define OR1K_SPR_DMMU_DMMUPR_URE2_OFFSET 6 |
---|
| 1113 | #define OR1K_SPR_DMMU_DMMUPR_URE2_MASK 0x00000040 |
---|
| 1114 | #define OR1K_SPR_DMMU_DMMUPR_URE2_GET(X) (((X) >> 6) & 0x1) |
---|
| 1115 | #define OR1K_SPR_DMMU_DMMUPR_URE2_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6)) |
---|
| 1116 | |
---|
| 1117 | /* User Write Enable 2 */ |
---|
| 1118 | #define OR1K_SPR_DMMU_DMMUPR_UWE2_OFFSET 7 |
---|
| 1119 | #define OR1K_SPR_DMMU_DMMUPR_UWE2_MASK 0x00000080 |
---|
| 1120 | #define OR1K_SPR_DMMU_DMMUPR_UWE2_GET(X) (((X) >> 7) & 0x1) |
---|
| 1121 | #define OR1K_SPR_DMMU_DMMUPR_UWE2_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7)) |
---|
| 1122 | |
---|
| 1123 | /* Supervisor Read Enable 3 */ |
---|
| 1124 | #define OR1K_SPR_DMMU_DMMUPR_SRE3_OFFSET 8 |
---|
| 1125 | #define OR1K_SPR_DMMU_DMMUPR_SRE3_MASK 0x00000100 |
---|
| 1126 | #define OR1K_SPR_DMMU_DMMUPR_SRE3_GET(X) (((X) >> 8) & 0x1) |
---|
| 1127 | #define OR1K_SPR_DMMU_DMMUPR_SRE3_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffeff)) | ((!!(Y)) << 8)) |
---|
| 1128 | |
---|
| 1129 | /* Supervisor Write Enable 3 */ |
---|
| 1130 | #define OR1K_SPR_DMMU_DMMUPR_SWE3_OFFSET 9 |
---|
| 1131 | #define OR1K_SPR_DMMU_DMMUPR_SWE3_MASK 0x00000200 |
---|
| 1132 | #define OR1K_SPR_DMMU_DMMUPR_SWE3_GET(X) (((X) >> 9) & 0x1) |
---|
| 1133 | #define OR1K_SPR_DMMU_DMMUPR_SWE3_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffdff)) | ((!!(Y)) << 9)) |
---|
| 1134 | |
---|
| 1135 | /* User Read Enable 3 */ |
---|
| 1136 | #define OR1K_SPR_DMMU_DMMUPR_URE3_OFFSET 10 |
---|
| 1137 | #define OR1K_SPR_DMMU_DMMUPR_URE3_MASK 0x00000400 |
---|
| 1138 | #define OR1K_SPR_DMMU_DMMUPR_URE3_GET(X) (((X) >> 10) & 0x1) |
---|
| 1139 | #define OR1K_SPR_DMMU_DMMUPR_URE3_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffbff)) | ((!!(Y)) << 10)) |
---|
| 1140 | |
---|
| 1141 | /* User Write Enable 3 */ |
---|
| 1142 | #define OR1K_SPR_DMMU_DMMUPR_UWE3_OFFSET 11 |
---|
| 1143 | #define OR1K_SPR_DMMU_DMMUPR_UWE3_MASK 0x00000800 |
---|
| 1144 | #define OR1K_SPR_DMMU_DMMUPR_UWE3_GET(X) (((X) >> 11) & 0x1) |
---|
| 1145 | #define OR1K_SPR_DMMU_DMMUPR_UWE3_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffff7ff)) | ((!!(Y)) << 11)) |
---|
| 1146 | |
---|
| 1147 | /* Supervisor Read Enable 4 */ |
---|
| 1148 | #define OR1K_SPR_DMMU_DMMUPR_SRE4_OFFSET 12 |
---|
| 1149 | #define OR1K_SPR_DMMU_DMMUPR_SRE4_MASK 0x00001000 |
---|
| 1150 | #define OR1K_SPR_DMMU_DMMUPR_SRE4_GET(X) (((X) >> 12) & 0x1) |
---|
| 1151 | #define OR1K_SPR_DMMU_DMMUPR_SRE4_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffefff)) | ((!!(Y)) << 12)) |
---|
| 1152 | |
---|
| 1153 | /* Supervisor Write Enable 4 */ |
---|
| 1154 | #define OR1K_SPR_DMMU_DMMUPR_SWE4_OFFSET 13 |
---|
| 1155 | #define OR1K_SPR_DMMU_DMMUPR_SWE4_MASK 0x00002000 |
---|
| 1156 | #define OR1K_SPR_DMMU_DMMUPR_SWE4_GET(X) (((X) >> 13) & 0x1) |
---|
| 1157 | #define OR1K_SPR_DMMU_DMMUPR_SWE4_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffdfff)) | ((!!(Y)) << 13)) |
---|
| 1158 | |
---|
| 1159 | /* User Read Enable 4 */ |
---|
| 1160 | #define OR1K_SPR_DMMU_DMMUPR_URE4_OFFSET 14 |
---|
| 1161 | #define OR1K_SPR_DMMU_DMMUPR_URE4_MASK 0x00004000 |
---|
| 1162 | #define OR1K_SPR_DMMU_DMMUPR_URE4_GET(X) (((X) >> 14) & 0x1) |
---|
| 1163 | #define OR1K_SPR_DMMU_DMMUPR_URE4_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffbfff)) | ((!!(Y)) << 14)) |
---|
| 1164 | |
---|
| 1165 | /* User Write Enable 4 */ |
---|
| 1166 | #define OR1K_SPR_DMMU_DMMUPR_UWE4_OFFSET 15 |
---|
| 1167 | #define OR1K_SPR_DMMU_DMMUPR_UWE4_MASK 0x00008000 |
---|
| 1168 | #define OR1K_SPR_DMMU_DMMUPR_UWE4_GET(X) (((X) >> 15) & 0x1) |
---|
| 1169 | #define OR1K_SPR_DMMU_DMMUPR_UWE4_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffff7fff)) | ((!!(Y)) << 15)) |
---|
| 1170 | |
---|
| 1171 | /* Supervisor Read Enable 5 */ |
---|
| 1172 | #define OR1K_SPR_DMMU_DMMUPR_SRE5_OFFSET 16 |
---|
| 1173 | #define OR1K_SPR_DMMU_DMMUPR_SRE5_MASK 0x00010000 |
---|
| 1174 | #define OR1K_SPR_DMMU_DMMUPR_SRE5_GET(X) (((X) >> 16) & 0x1) |
---|
| 1175 | #define OR1K_SPR_DMMU_DMMUPR_SRE5_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffeffff)) | ((!!(Y)) << 16)) |
---|
| 1176 | |
---|
| 1177 | /* Supervisor Write Enable 5 */ |
---|
| 1178 | #define OR1K_SPR_DMMU_DMMUPR_SWE5_OFFSET 17 |
---|
| 1179 | #define OR1K_SPR_DMMU_DMMUPR_SWE5_MASK 0x00020000 |
---|
| 1180 | #define OR1K_SPR_DMMU_DMMUPR_SWE5_GET(X) (((X) >> 17) & 0x1) |
---|
| 1181 | #define OR1K_SPR_DMMU_DMMUPR_SWE5_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffdffff)) | ((!!(Y)) << 17)) |
---|
| 1182 | |
---|
| 1183 | /* User Read Enable 5 */ |
---|
| 1184 | #define OR1K_SPR_DMMU_DMMUPR_URE5_OFFSET 18 |
---|
| 1185 | #define OR1K_SPR_DMMU_DMMUPR_URE5_MASK 0x00040000 |
---|
| 1186 | #define OR1K_SPR_DMMU_DMMUPR_URE5_GET(X) (((X) >> 18) & 0x1) |
---|
| 1187 | #define OR1K_SPR_DMMU_DMMUPR_URE5_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffbffff)) | ((!!(Y)) << 18)) |
---|
| 1188 | |
---|
| 1189 | /* User Write Enable 5 */ |
---|
| 1190 | #define OR1K_SPR_DMMU_DMMUPR_UWE5_OFFSET 19 |
---|
| 1191 | #define OR1K_SPR_DMMU_DMMUPR_UWE5_MASK 0x00080000 |
---|
| 1192 | #define OR1K_SPR_DMMU_DMMUPR_UWE5_GET(X) (((X) >> 19) & 0x1) |
---|
| 1193 | #define OR1K_SPR_DMMU_DMMUPR_UWE5_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfff7ffff)) | ((!!(Y)) << 19)) |
---|
| 1194 | |
---|
| 1195 | /* Supervisor Read Enable 6 */ |
---|
| 1196 | #define OR1K_SPR_DMMU_DMMUPR_SRE6_OFFSET 20 |
---|
| 1197 | #define OR1K_SPR_DMMU_DMMUPR_SRE6_MASK 0x00100000 |
---|
| 1198 | #define OR1K_SPR_DMMU_DMMUPR_SRE6_GET(X) (((X) >> 20) & 0x1) |
---|
| 1199 | #define OR1K_SPR_DMMU_DMMUPR_SRE6_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffefffff)) | ((!!(Y)) << 20)) |
---|
| 1200 | |
---|
| 1201 | /* Supervisor Write Enable 6 */ |
---|
| 1202 | #define OR1K_SPR_DMMU_DMMUPR_SWE6_OFFSET 21 |
---|
| 1203 | #define OR1K_SPR_DMMU_DMMUPR_SWE6_MASK 0x00200000 |
---|
| 1204 | #define OR1K_SPR_DMMU_DMMUPR_SWE6_GET(X) (((X) >> 21) & 0x1) |
---|
| 1205 | #define OR1K_SPR_DMMU_DMMUPR_SWE6_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffdfffff)) | ((!!(Y)) << 21)) |
---|
| 1206 | |
---|
| 1207 | /* User Read Enable 6 */ |
---|
| 1208 | #define OR1K_SPR_DMMU_DMMUPR_URE6_OFFSET 22 |
---|
| 1209 | #define OR1K_SPR_DMMU_DMMUPR_URE6_MASK 0x00400000 |
---|
| 1210 | #define OR1K_SPR_DMMU_DMMUPR_URE6_GET(X) (((X) >> 22) & 0x1) |
---|
| 1211 | #define OR1K_SPR_DMMU_DMMUPR_URE6_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffbfffff)) | ((!!(Y)) << 22)) |
---|
| 1212 | |
---|
| 1213 | /* User Write Enable 6 */ |
---|
| 1214 | #define OR1K_SPR_DMMU_DMMUPR_UWE6_OFFSET 23 |
---|
| 1215 | #define OR1K_SPR_DMMU_DMMUPR_UWE6_MASK 0x00800000 |
---|
| 1216 | #define OR1K_SPR_DMMU_DMMUPR_UWE6_GET(X) (((X) >> 23) & 0x1) |
---|
| 1217 | #define OR1K_SPR_DMMU_DMMUPR_UWE6_SET(X, Y) (((X) & OR1K_UNSIGNED(0xff7fffff)) | ((!!(Y)) << 23)) |
---|
| 1218 | |
---|
| 1219 | /* Supervisor Read Enable 7 */ |
---|
| 1220 | #define OR1K_SPR_DMMU_DMMUPR_SRE7_OFFSET 24 |
---|
| 1221 | #define OR1K_SPR_DMMU_DMMUPR_SRE7_MASK 0x01000000 |
---|
| 1222 | #define OR1K_SPR_DMMU_DMMUPR_SRE7_GET(X) (((X) >> 24) & 0x1) |
---|
| 1223 | #define OR1K_SPR_DMMU_DMMUPR_SRE7_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfeffffff)) | ((!!(Y)) << 24)) |
---|
| 1224 | |
---|
| 1225 | /* Supervisor Write Enable 7 */ |
---|
| 1226 | #define OR1K_SPR_DMMU_DMMUPR_SWE7_OFFSET 25 |
---|
| 1227 | #define OR1K_SPR_DMMU_DMMUPR_SWE7_MASK 0x02000000 |
---|
| 1228 | #define OR1K_SPR_DMMU_DMMUPR_SWE7_GET(X) (((X) >> 25) & 0x1) |
---|
| 1229 | #define OR1K_SPR_DMMU_DMMUPR_SWE7_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfdffffff)) | ((!!(Y)) << 25)) |
---|
| 1230 | |
---|
| 1231 | /* User Read Enable 7 */ |
---|
| 1232 | #define OR1K_SPR_DMMU_DMMUPR_URE7_OFFSET 26 |
---|
| 1233 | #define OR1K_SPR_DMMU_DMMUPR_URE7_MASK 0x04000000 |
---|
| 1234 | #define OR1K_SPR_DMMU_DMMUPR_URE7_GET(X) (((X) >> 26) & 0x1) |
---|
| 1235 | #define OR1K_SPR_DMMU_DMMUPR_URE7_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfbffffff)) | ((!!(Y)) << 26)) |
---|
| 1236 | |
---|
| 1237 | /* User Write Enable 7 */ |
---|
| 1238 | #define OR1K_SPR_DMMU_DMMUPR_UWE7_OFFSET 27 |
---|
| 1239 | #define OR1K_SPR_DMMU_DMMUPR_UWE7_MASK 0x08000000 |
---|
| 1240 | #define OR1K_SPR_DMMU_DMMUPR_UWE7_GET(X) (((X) >> 27) & 0x1) |
---|
| 1241 | #define OR1K_SPR_DMMU_DMMUPR_UWE7_SET(X, Y) (((X) & OR1K_UNSIGNED(0xf7ffffff)) | ((!!(Y)) << 27)) |
---|
| 1242 | |
---|
| 1243 | |
---|
| 1244 | /* Data TLB Entry Invalidate Register */ |
---|
| 1245 | #define OR1K_SPR_DMMU_DTLBEIR_INDEX OR1K_UNSIGNED(0x002) |
---|
| 1246 | #define OR1K_SPR_DMMU_DTLBEIR_ADDR OR1K_UNSIGNED(0x0802) |
---|
| 1247 | |
---|
| 1248 | |
---|
| 1249 | /* Data ATB Match Registers */ |
---|
| 1250 | #define OR1K_SPR_DMMU_DATBMR_BASE OR1K_UNSIGNED(0x004) |
---|
| 1251 | #define OR1K_SPR_DMMU_DATBMR_COUNT OR1K_UNSIGNED(0x004) |
---|
| 1252 | #define OR1K_SPR_DMMU_DATBMR_STEP OR1K_UNSIGNED(0x001) |
---|
| 1253 | #define OR1K_SPR_DMMU_DATBMR_INDEX(N) (OR1K_SPR_DMMU_DATBMR_BASE + ((N) * OR1K_SPR_DMMU_DATBMR_STEP)) |
---|
| 1254 | #define OR1K_SPR_DMMU_DATBMR_ADDR(N) ((OR1K_SPR_DMMU_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_DMMU_DATBMR_INDEX(N)) |
---|
| 1255 | |
---|
| 1256 | /* Valid */ |
---|
| 1257 | #define OR1K_SPR_DMMU_DATBMR_V_OFFSET 0 |
---|
| 1258 | #define OR1K_SPR_DMMU_DATBMR_V_MASK 0x00000001 |
---|
| 1259 | #define OR1K_SPR_DMMU_DATBMR_V_GET(X) (((X) >> 0) & 0x1) |
---|
| 1260 | #define OR1K_SPR_DMMU_DATBMR_V_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 1261 | |
---|
| 1262 | /* Context ID */ |
---|
| 1263 | #define OR1K_SPR_DMMU_DATBMR_CID_LSB 1 |
---|
| 1264 | #define OR1K_SPR_DMMU_DATBMR_CID_MSB 4 |
---|
| 1265 | #define OR1K_SPR_DMMU_DATBMR_CID_BITS 4 |
---|
| 1266 | #define OR1K_SPR_DMMU_DATBMR_CID_MASK OR1K_UNSIGNED(0x0000001e) |
---|
| 1267 | #define OR1K_SPR_DMMU_DATBMR_CID_GET(X) (((X) >> 1) & OR1K_UNSIGNED(0x0000000f)) |
---|
| 1268 | #define OR1K_SPR_DMMU_DATBMR_CID_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffe1)) | ((Y) << 1)) |
---|
| 1269 | |
---|
| 1270 | /* Page Size */ |
---|
| 1271 | #define OR1K_SPR_DMMU_DATBMR_PS_OFFSET 5 |
---|
| 1272 | #define OR1K_SPR_DMMU_DATBMR_PS_MASK 0x00000020 |
---|
| 1273 | #define OR1K_SPR_DMMU_DATBMR_PS_GET(X) (((X) >> 5) & 0x1) |
---|
| 1274 | #define OR1K_SPR_DMMU_DATBMR_PS_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 1275 | |
---|
| 1276 | /* Virtual Page Number */ |
---|
| 1277 | #define OR1K_SPR_DMMU_DATBMR_VPN_LSB 10 |
---|
| 1278 | #define OR1K_SPR_DMMU_DATBMR_VPN_MSB 31 |
---|
| 1279 | #define OR1K_SPR_DMMU_DATBMR_VPN_BITS 22 |
---|
| 1280 | #define OR1K_SPR_DMMU_DATBMR_VPN_MASK OR1K_UNSIGNED(0xfffffc00) |
---|
| 1281 | #define OR1K_SPR_DMMU_DATBMR_VPN_GET(X) (((X) >> 10) & OR1K_UNSIGNED(0x003fffff)) |
---|
| 1282 | #define OR1K_SPR_DMMU_DATBMR_VPN_SET(X, Y) (((X) & OR1K_UNSIGNED(0x000003ff)) | ((Y) << 10)) |
---|
| 1283 | |
---|
| 1284 | |
---|
| 1285 | /* Data ATB Translate Registers */ |
---|
| 1286 | #define OR1K_SPR_DMMU_DATBTR_BASE OR1K_UNSIGNED(0x008) |
---|
| 1287 | #define OR1K_SPR_DMMU_DATBTR_COUNT OR1K_UNSIGNED(0x004) |
---|
| 1288 | #define OR1K_SPR_DMMU_DATBTR_STEP OR1K_UNSIGNED(0x001) |
---|
| 1289 | #define OR1K_SPR_DMMU_DATBTR_INDEX(N) (OR1K_SPR_DMMU_DATBTR_BASE + ((N) * OR1K_SPR_DMMU_DATBTR_STEP)) |
---|
| 1290 | #define OR1K_SPR_DMMU_DATBTR_ADDR(N) ((OR1K_SPR_DMMU_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_DMMU_DATBTR_INDEX(N)) |
---|
| 1291 | |
---|
| 1292 | /* Cache Coherency */ |
---|
| 1293 | #define OR1K_SPR_DMMU_DATBTR_CC_OFFSET 0 |
---|
| 1294 | #define OR1K_SPR_DMMU_DATBTR_CC_MASK 0x00000001 |
---|
| 1295 | #define OR1K_SPR_DMMU_DATBTR_CC_GET(X) (((X) >> 0) & 0x1) |
---|
| 1296 | #define OR1K_SPR_DMMU_DATBTR_CC_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 1297 | |
---|
| 1298 | /* Cache Inhibit */ |
---|
| 1299 | #define OR1K_SPR_DMMU_DATBTR_CI_OFFSET 1 |
---|
| 1300 | #define OR1K_SPR_DMMU_DATBTR_CI_MASK 0x00000002 |
---|
| 1301 | #define OR1K_SPR_DMMU_DATBTR_CI_GET(X) (((X) >> 1) & 0x1) |
---|
| 1302 | #define OR1K_SPR_DMMU_DATBTR_CI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffd)) | ((!!(Y)) << 1)) |
---|
| 1303 | |
---|
| 1304 | /* Write-back Cache */ |
---|
| 1305 | #define OR1K_SPR_DMMU_DATBTR_WBC_OFFSET 2 |
---|
| 1306 | #define OR1K_SPR_DMMU_DATBTR_WBC_MASK 0x00000004 |
---|
| 1307 | #define OR1K_SPR_DMMU_DATBTR_WBC_GET(X) (((X) >> 2) & 0x1) |
---|
| 1308 | #define OR1K_SPR_DMMU_DATBTR_WBC_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffb)) | ((!!(Y)) << 2)) |
---|
| 1309 | |
---|
| 1310 | /* Weakly-ordered Memory */ |
---|
| 1311 | #define OR1K_SPR_DMMU_DATBTR_WOM_OFFSET 3 |
---|
| 1312 | #define OR1K_SPR_DMMU_DATBTR_WOM_MASK 0x00000008 |
---|
| 1313 | #define OR1K_SPR_DMMU_DATBTR_WOM_GET(X) (((X) >> 3) & 0x1) |
---|
| 1314 | #define OR1K_SPR_DMMU_DATBTR_WOM_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff7)) | ((!!(Y)) << 3)) |
---|
| 1315 | |
---|
| 1316 | /* Accessed */ |
---|
| 1317 | #define OR1K_SPR_DMMU_DATBTR_A_OFFSET 4 |
---|
| 1318 | #define OR1K_SPR_DMMU_DATBTR_A_MASK 0x00000010 |
---|
| 1319 | #define OR1K_SPR_DMMU_DATBTR_A_GET(X) (((X) >> 4) & 0x1) |
---|
| 1320 | #define OR1K_SPR_DMMU_DATBTR_A_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffef)) | ((!!(Y)) << 4)) |
---|
| 1321 | |
---|
| 1322 | /* Dirty */ |
---|
| 1323 | #define OR1K_SPR_DMMU_DATBTR_D_OFFSET 5 |
---|
| 1324 | #define OR1K_SPR_DMMU_DATBTR_D_MASK 0x00000020 |
---|
| 1325 | #define OR1K_SPR_DMMU_DATBTR_D_GET(X) (((X) >> 5) & 0x1) |
---|
| 1326 | #define OR1K_SPR_DMMU_DATBTR_D_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 1327 | |
---|
| 1328 | /* Supervisor Read Enable */ |
---|
| 1329 | #define OR1K_SPR_DMMU_DATBTR_SRE_OFFSET 6 |
---|
| 1330 | #define OR1K_SPR_DMMU_DATBTR_SRE_MASK 0x00000040 |
---|
| 1331 | #define OR1K_SPR_DMMU_DATBTR_SRE_GET(X) (((X) >> 6) & 0x1) |
---|
| 1332 | #define OR1K_SPR_DMMU_DATBTR_SRE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6)) |
---|
| 1333 | |
---|
| 1334 | /* Supervisor Write Enable */ |
---|
| 1335 | #define OR1K_SPR_DMMU_DATBTR_SWE_OFFSET 7 |
---|
| 1336 | #define OR1K_SPR_DMMU_DATBTR_SWE_MASK 0x00000080 |
---|
| 1337 | #define OR1K_SPR_DMMU_DATBTR_SWE_GET(X) (((X) >> 7) & 0x1) |
---|
| 1338 | #define OR1K_SPR_DMMU_DATBTR_SWE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7)) |
---|
| 1339 | |
---|
| 1340 | /* User Read Enable */ |
---|
| 1341 | #define OR1K_SPR_DMMU_DATBTR_URE_OFFSET 8 |
---|
| 1342 | #define OR1K_SPR_DMMU_DATBTR_URE_MASK 0x00000100 |
---|
| 1343 | #define OR1K_SPR_DMMU_DATBTR_URE_GET(X) (((X) >> 8) & 0x1) |
---|
| 1344 | #define OR1K_SPR_DMMU_DATBTR_URE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffeff)) | ((!!(Y)) << 8)) |
---|
| 1345 | |
---|
| 1346 | /* User Write Enable */ |
---|
| 1347 | #define OR1K_SPR_DMMU_DATBTR_UWE_OFFSET 9 |
---|
| 1348 | #define OR1K_SPR_DMMU_DATBTR_UWE_MASK 0x00000200 |
---|
| 1349 | #define OR1K_SPR_DMMU_DATBTR_UWE_GET(X) (((X) >> 9) & 0x1) |
---|
| 1350 | #define OR1K_SPR_DMMU_DATBTR_UWE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffdff)) | ((!!(Y)) << 9)) |
---|
| 1351 | |
---|
| 1352 | /* Physical Page Number */ |
---|
| 1353 | #define OR1K_SPR_DMMU_DATBTR_PPN_LSB 10 |
---|
| 1354 | #define OR1K_SPR_DMMU_DATBTR_PPN_MSB 31 |
---|
| 1355 | #define OR1K_SPR_DMMU_DATBTR_PPN_BITS 22 |
---|
| 1356 | #define OR1K_SPR_DMMU_DATBTR_PPN_MASK OR1K_UNSIGNED(0xfffffc00) |
---|
| 1357 | #define OR1K_SPR_DMMU_DATBTR_PPN_GET(X) (((X) >> 10) & OR1K_UNSIGNED(0x003fffff)) |
---|
| 1358 | #define OR1K_SPR_DMMU_DATBTR_PPN_SET(X, Y) (((X) & OR1K_UNSIGNED(0x000003ff)) | ((Y) << 10)) |
---|
| 1359 | |
---|
| 1360 | |
---|
| 1361 | /* Data TLB */ |
---|
| 1362 | #define OR1K_SPR_DMMU_DTLBW_BASE OR1K_UNSIGNED(0x200) |
---|
| 1363 | #define OR1K_SPR_DMMU_DTLBW_COUNT OR1K_UNSIGNED(0x004) |
---|
| 1364 | #define OR1K_SPR_DMMU_DTLBW_STEP OR1K_UNSIGNED(0x100) |
---|
| 1365 | #define OR1K_SPR_DMMU_DTLBW_SUBBASE(N0) (OR1K_SPR_DMMU_DTLBW_BASE + ((N0)*OR1K_SPR_DMMU_DTLBW_STEP)) |
---|
| 1366 | |
---|
| 1367 | /* Data TLB Match Registers */ |
---|
| 1368 | #define OR1K_SPR_DMMU_DTLBW_MR_BASE OR1K_UNSIGNED(0x000) |
---|
| 1369 | #define OR1K_SPR_DMMU_DTLBW_MR_COUNT OR1K_UNSIGNED(0x080) |
---|
| 1370 | #define OR1K_SPR_DMMU_DTLBW_MR_STEP OR1K_UNSIGNED(0x001) |
---|
| 1371 | |
---|
| 1372 | #define OR1K_SPR_DMMU_DTLBW_MR_INDEX(N0, N1) (OR1K_SPR_DMMU_DTLBW_SUBBASE(N0) + OR1K_SPR_DMMU_DTLBW_MR_BASE + ((N1) * OR1K_SPR_DMMU_DTLBW_MR_STEP)) |
---|
| 1373 | #define OR1K_SPR_DMMU_DTLBW_MR_ADDR(N0, N1) ((OR1K_SPR_DMMU_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_DMMU_DTLBW_MR_INDEX(N0, N1)) |
---|
| 1374 | |
---|
| 1375 | /* Valid */ |
---|
| 1376 | #define OR1K_SPR_DMMU_DTLBW_MR_V_OFFSET 0 |
---|
| 1377 | #define OR1K_SPR_DMMU_DTLBW_MR_V_MASK 0x00000001 |
---|
| 1378 | #define OR1K_SPR_DMMU_DTLBW_MR_V_GET(X) (((X) >> 0) & 0x1) |
---|
| 1379 | #define OR1K_SPR_DMMU_DTLBW_MR_V_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 1380 | |
---|
| 1381 | /* Page Level 1 */ |
---|
| 1382 | #define OR1K_SPR_DMMU_DTLBW_MR_PL1_OFFSET 1 |
---|
| 1383 | #define OR1K_SPR_DMMU_DTLBW_MR_PL1_MASK 0x00000002 |
---|
| 1384 | #define OR1K_SPR_DMMU_DTLBW_MR_PL1_GET(X) (((X) >> 1) & 0x1) |
---|
| 1385 | #define OR1K_SPR_DMMU_DTLBW_MR_PL1_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffd)) | ((!!(Y)) << 1)) |
---|
| 1386 | |
---|
| 1387 | /* Context ID */ |
---|
| 1388 | #define OR1K_SPR_DMMU_DTLBW_MR_CID_LSB 2 |
---|
| 1389 | #define OR1K_SPR_DMMU_DTLBW_MR_CID_MSB 5 |
---|
| 1390 | #define OR1K_SPR_DMMU_DTLBW_MR_CID_BITS 4 |
---|
| 1391 | #define OR1K_SPR_DMMU_DTLBW_MR_CID_MASK OR1K_UNSIGNED(0x0000003c) |
---|
| 1392 | #define OR1K_SPR_DMMU_DTLBW_MR_CID_GET(X) (((X) >> 2) & OR1K_UNSIGNED(0x0000000f)) |
---|
| 1393 | #define OR1K_SPR_DMMU_DTLBW_MR_CID_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffc3)) | ((Y) << 2)) |
---|
| 1394 | |
---|
| 1395 | /* Least Recently Used */ |
---|
| 1396 | #define OR1K_SPR_DMMU_DTLBW_MR_LRU_LSB 6 |
---|
| 1397 | #define OR1K_SPR_DMMU_DTLBW_MR_LRU_MSB 7 |
---|
| 1398 | #define OR1K_SPR_DMMU_DTLBW_MR_LRU_BITS 2 |
---|
| 1399 | #define OR1K_SPR_DMMU_DTLBW_MR_LRU_MASK OR1K_UNSIGNED(0x000000c0) |
---|
| 1400 | #define OR1K_SPR_DMMU_DTLBW_MR_LRU_GET(X) (((X) >> 6) & OR1K_UNSIGNED(0x00000003)) |
---|
| 1401 | #define OR1K_SPR_DMMU_DTLBW_MR_LRU_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff3f)) | ((Y) << 6)) |
---|
| 1402 | |
---|
| 1403 | /* Virtual Page Number */ |
---|
| 1404 | #define OR1K_SPR_DMMU_DTLBW_MR_VPN_LSB 13 |
---|
| 1405 | #define OR1K_SPR_DMMU_DTLBW_MR_VPN_MSB 31 |
---|
| 1406 | #define OR1K_SPR_DMMU_DTLBW_MR_VPN_BITS 19 |
---|
| 1407 | #define OR1K_SPR_DMMU_DTLBW_MR_VPN_MASK OR1K_UNSIGNED(0xffffe000) |
---|
| 1408 | #define OR1K_SPR_DMMU_DTLBW_MR_VPN_GET(X) (((X) >> 13) & OR1K_UNSIGNED(0x0007ffff)) |
---|
| 1409 | #define OR1K_SPR_DMMU_DTLBW_MR_VPN_SET(X, Y) (((X) & OR1K_UNSIGNED(0x00001fff)) | ((Y) << 13)) |
---|
| 1410 | |
---|
| 1411 | /* Data TLB Translate Registers */ |
---|
| 1412 | #define OR1K_SPR_DMMU_DTLBW_TR_BASE OR1K_UNSIGNED(0x080) |
---|
| 1413 | #define OR1K_SPR_DMMU_DTLBW_TR_COUNT OR1K_UNSIGNED(0x080) |
---|
| 1414 | #define OR1K_SPR_DMMU_DTLBW_TR_STEP OR1K_UNSIGNED(0x001) |
---|
| 1415 | |
---|
| 1416 | #define OR1K_SPR_DMMU_DTLBW_TR_INDEX(N0, N1) (OR1K_SPR_DMMU_DTLBW_SUBBASE(N0) + OR1K_SPR_DMMU_DTLBW_TR_BASE + ((N1) * OR1K_SPR_DMMU_DTLBW_TR_STEP)) |
---|
| 1417 | #define OR1K_SPR_DMMU_DTLBW_TR_ADDR(N0, N1) ((OR1K_SPR_DMMU_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_DMMU_DTLBW_TR_INDEX(N0, N1)) |
---|
| 1418 | |
---|
| 1419 | /* Cache Coherency */ |
---|
| 1420 | #define OR1K_SPR_DMMU_DTLBW_TR_CC_OFFSET 0 |
---|
| 1421 | #define OR1K_SPR_DMMU_DTLBW_TR_CC_MASK 0x00000001 |
---|
| 1422 | #define OR1K_SPR_DMMU_DTLBW_TR_CC_GET(X) (((X) >> 0) & 0x1) |
---|
| 1423 | #define OR1K_SPR_DMMU_DTLBW_TR_CC_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 1424 | |
---|
| 1425 | /* Cache Inhibit */ |
---|
| 1426 | #define OR1K_SPR_DMMU_DTLBW_TR_CI_OFFSET 1 |
---|
| 1427 | #define OR1K_SPR_DMMU_DTLBW_TR_CI_MASK 0x00000002 |
---|
| 1428 | #define OR1K_SPR_DMMU_DTLBW_TR_CI_GET(X) (((X) >> 1) & 0x1) |
---|
| 1429 | #define OR1K_SPR_DMMU_DTLBW_TR_CI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffd)) | ((!!(Y)) << 1)) |
---|
| 1430 | |
---|
| 1431 | /* Write-back Cache */ |
---|
| 1432 | #define OR1K_SPR_DMMU_DTLBW_TR_WBC_OFFSET 2 |
---|
| 1433 | #define OR1K_SPR_DMMU_DTLBW_TR_WBC_MASK 0x00000004 |
---|
| 1434 | #define OR1K_SPR_DMMU_DTLBW_TR_WBC_GET(X) (((X) >> 2) & 0x1) |
---|
| 1435 | #define OR1K_SPR_DMMU_DTLBW_TR_WBC_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffb)) | ((!!(Y)) << 2)) |
---|
| 1436 | |
---|
| 1437 | /* Weakly-ordered Memory */ |
---|
| 1438 | #define OR1K_SPR_DMMU_DTLBW_TR_WOM_OFFSET 3 |
---|
| 1439 | #define OR1K_SPR_DMMU_DTLBW_TR_WOM_MASK 0x00000008 |
---|
| 1440 | #define OR1K_SPR_DMMU_DTLBW_TR_WOM_GET(X) (((X) >> 3) & 0x1) |
---|
| 1441 | #define OR1K_SPR_DMMU_DTLBW_TR_WOM_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff7)) | ((!!(Y)) << 3)) |
---|
| 1442 | |
---|
| 1443 | /* Accessed */ |
---|
| 1444 | #define OR1K_SPR_DMMU_DTLBW_TR_A_OFFSET 4 |
---|
| 1445 | #define OR1K_SPR_DMMU_DTLBW_TR_A_MASK 0x00000010 |
---|
| 1446 | #define OR1K_SPR_DMMU_DTLBW_TR_A_GET(X) (((X) >> 4) & 0x1) |
---|
| 1447 | #define OR1K_SPR_DMMU_DTLBW_TR_A_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffef)) | ((!!(Y)) << 4)) |
---|
| 1448 | |
---|
| 1449 | /* Dirty */ |
---|
| 1450 | #define OR1K_SPR_DMMU_DTLBW_TR_D_OFFSET 5 |
---|
| 1451 | #define OR1K_SPR_DMMU_DTLBW_TR_D_MASK 0x00000020 |
---|
| 1452 | #define OR1K_SPR_DMMU_DTLBW_TR_D_GET(X) (((X) >> 5) & 0x1) |
---|
| 1453 | #define OR1K_SPR_DMMU_DTLBW_TR_D_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 1454 | |
---|
| 1455 | /* User Read Enable */ |
---|
| 1456 | #define OR1K_SPR_DMMU_DTLBW_TR_URE_OFFSET 6 |
---|
| 1457 | #define OR1K_SPR_DMMU_DTLBW_TR_URE_MASK 0x00000040 |
---|
| 1458 | #define OR1K_SPR_DMMU_DTLBW_TR_URE_GET(X) (((X) >> 6) & 0x1) |
---|
| 1459 | #define OR1K_SPR_DMMU_DTLBW_TR_URE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6)) |
---|
| 1460 | |
---|
| 1461 | /* User Write Enable */ |
---|
| 1462 | #define OR1K_SPR_DMMU_DTLBW_TR_UWE_OFFSET 7 |
---|
| 1463 | #define OR1K_SPR_DMMU_DTLBW_TR_UWE_MASK 0x00000080 |
---|
| 1464 | #define OR1K_SPR_DMMU_DTLBW_TR_UWE_GET(X) (((X) >> 7) & 0x1) |
---|
| 1465 | #define OR1K_SPR_DMMU_DTLBW_TR_UWE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7)) |
---|
| 1466 | |
---|
| 1467 | /* Supervisor Read Enable */ |
---|
| 1468 | #define OR1K_SPR_DMMU_DTLBW_TR_SRE_OFFSET 8 |
---|
| 1469 | #define OR1K_SPR_DMMU_DTLBW_TR_SRE_MASK 0x00000100 |
---|
| 1470 | #define OR1K_SPR_DMMU_DTLBW_TR_SRE_GET(X) (((X) >> 8) & 0x1) |
---|
| 1471 | #define OR1K_SPR_DMMU_DTLBW_TR_SRE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffeff)) | ((!!(Y)) << 8)) |
---|
| 1472 | |
---|
| 1473 | /* Supervisor Write Enable */ |
---|
| 1474 | #define OR1K_SPR_DMMU_DTLBW_TR_SWE_OFFSET 9 |
---|
| 1475 | #define OR1K_SPR_DMMU_DTLBW_TR_SWE_MASK 0x00000200 |
---|
| 1476 | #define OR1K_SPR_DMMU_DTLBW_TR_SWE_GET(X) (((X) >> 9) & 0x1) |
---|
| 1477 | #define OR1K_SPR_DMMU_DTLBW_TR_SWE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffdff)) | ((!!(Y)) << 9)) |
---|
| 1478 | |
---|
| 1479 | /* Physical Page Number */ |
---|
| 1480 | #define OR1K_SPR_DMMU_DTLBW_TR_PPN_LSB 13 |
---|
| 1481 | #define OR1K_SPR_DMMU_DTLBW_TR_PPN_MSB 31 |
---|
| 1482 | #define OR1K_SPR_DMMU_DTLBW_TR_PPN_BITS 19 |
---|
| 1483 | #define OR1K_SPR_DMMU_DTLBW_TR_PPN_MASK OR1K_UNSIGNED(0xffffe000) |
---|
| 1484 | #define OR1K_SPR_DMMU_DTLBW_TR_PPN_GET(X) (((X) >> 13) & OR1K_UNSIGNED(0x0007ffff)) |
---|
| 1485 | #define OR1K_SPR_DMMU_DTLBW_TR_PPN_SET(X, Y) (((X) & OR1K_UNSIGNED(0x00001fff)) | ((Y) << 13)) |
---|
| 1486 | |
---|
| 1487 | |
---|
| 1488 | /*************************/ |
---|
| 1489 | /* Instruction MMU Group */ |
---|
| 1490 | /*************************/ |
---|
| 1491 | #define OR1K_SPR_IMMU_GROUP 0x02 |
---|
| 1492 | |
---|
| 1493 | /* Instruction MMU Control Register */ |
---|
| 1494 | #define OR1K_SPR_IMMU_IMMUCR_INDEX OR1K_UNSIGNED(0x000) |
---|
| 1495 | #define OR1K_SPR_IMMU_IMMUCR_ADDR OR1K_UNSIGNED(0x1000) |
---|
| 1496 | |
---|
| 1497 | /* ITLB Flush */ |
---|
| 1498 | #define OR1K_SPR_IMMU_IMMUCR_ITF_OFFSET 0 |
---|
| 1499 | #define OR1K_SPR_IMMU_IMMUCR_ITF_MASK 0x00000001 |
---|
| 1500 | #define OR1K_SPR_IMMU_IMMUCR_ITF_GET(X) (((X) >> 0) & 0x1) |
---|
| 1501 | #define OR1K_SPR_IMMU_IMMUCR_ITF_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 1502 | |
---|
| 1503 | /* Page Table Base Pointer */ |
---|
| 1504 | #define OR1K_SPR_IMMU_IMMUCR_PTBP_LSB 10 |
---|
| 1505 | #define OR1K_SPR_IMMU_IMMUCR_PTBP_MSB 31 |
---|
| 1506 | #define OR1K_SPR_IMMU_IMMUCR_PTBP_BITS 22 |
---|
| 1507 | #define OR1K_SPR_IMMU_IMMUCR_PTBP_MASK OR1K_UNSIGNED(0xfffffc00) |
---|
| 1508 | #define OR1K_SPR_IMMU_IMMUCR_PTBP_GET(X) (((X) >> 10) & OR1K_UNSIGNED(0x003fffff)) |
---|
| 1509 | #define OR1K_SPR_IMMU_IMMUCR_PTBP_SET(X, Y) (((X) & OR1K_UNSIGNED(0x000003ff)) | ((Y) << 10)) |
---|
| 1510 | |
---|
| 1511 | |
---|
| 1512 | /* Instruction MMU Protection Register */ |
---|
| 1513 | #define OR1K_SPR_IMMU_IMMUPR_INDEX OR1K_UNSIGNED(0x001) |
---|
| 1514 | #define OR1K_SPR_IMMU_IMMUPR_ADDR OR1K_UNSIGNED(0x1001) |
---|
| 1515 | |
---|
| 1516 | /* Supervisor Execute Enable 1 */ |
---|
| 1517 | #define OR1K_SPR_IMMU_IMMUPR_SXE1_OFFSET 0 |
---|
| 1518 | #define OR1K_SPR_IMMU_IMMUPR_SXE1_MASK 0x00000001 |
---|
| 1519 | #define OR1K_SPR_IMMU_IMMUPR_SXE1_GET(X) (((X) >> 0) & 0x1) |
---|
| 1520 | #define OR1K_SPR_IMMU_IMMUPR_SXE1_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 1521 | |
---|
| 1522 | /* User Execute Enable 1 */ |
---|
| 1523 | #define OR1K_SPR_IMMU_IMMUPR_UXE1_OFFSET 1 |
---|
| 1524 | #define OR1K_SPR_IMMU_IMMUPR_UXE1_MASK 0x00000002 |
---|
| 1525 | #define OR1K_SPR_IMMU_IMMUPR_UXE1_GET(X) (((X) >> 1) & 0x1) |
---|
| 1526 | #define OR1K_SPR_IMMU_IMMUPR_UXE1_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffd)) | ((!!(Y)) << 1)) |
---|
| 1527 | |
---|
| 1528 | /* Supervisor Execute Enable 2 */ |
---|
| 1529 | #define OR1K_SPR_IMMU_IMMUPR_SXE2_OFFSET 2 |
---|
| 1530 | #define OR1K_SPR_IMMU_IMMUPR_SXE2_MASK 0x00000004 |
---|
| 1531 | #define OR1K_SPR_IMMU_IMMUPR_SXE2_GET(X) (((X) >> 2) & 0x1) |
---|
| 1532 | #define OR1K_SPR_IMMU_IMMUPR_SXE2_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffb)) | ((!!(Y)) << 2)) |
---|
| 1533 | |
---|
| 1534 | /* User Execute Enable 2 */ |
---|
| 1535 | #define OR1K_SPR_IMMU_IMMUPR_UXE2_OFFSET 3 |
---|
| 1536 | #define OR1K_SPR_IMMU_IMMUPR_UXE2_MASK 0x00000008 |
---|
| 1537 | #define OR1K_SPR_IMMU_IMMUPR_UXE2_GET(X) (((X) >> 3) & 0x1) |
---|
| 1538 | #define OR1K_SPR_IMMU_IMMUPR_UXE2_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff7)) | ((!!(Y)) << 3)) |
---|
| 1539 | |
---|
| 1540 | /* Supervisor Execute Enable 3 */ |
---|
| 1541 | #define OR1K_SPR_IMMU_IMMUPR_SXE3_OFFSET 4 |
---|
| 1542 | #define OR1K_SPR_IMMU_IMMUPR_SXE3_MASK 0x00000010 |
---|
| 1543 | #define OR1K_SPR_IMMU_IMMUPR_SXE3_GET(X) (((X) >> 4) & 0x1) |
---|
| 1544 | #define OR1K_SPR_IMMU_IMMUPR_SXE3_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffef)) | ((!!(Y)) << 4)) |
---|
| 1545 | |
---|
| 1546 | /* User Execute Enable 3 */ |
---|
| 1547 | #define OR1K_SPR_IMMU_IMMUPR_UXE3_OFFSET 5 |
---|
| 1548 | #define OR1K_SPR_IMMU_IMMUPR_UXE3_MASK 0x00000020 |
---|
| 1549 | #define OR1K_SPR_IMMU_IMMUPR_UXE3_GET(X) (((X) >> 5) & 0x1) |
---|
| 1550 | #define OR1K_SPR_IMMU_IMMUPR_UXE3_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 1551 | |
---|
| 1552 | /* Supervisor Execute Enable 4 */ |
---|
| 1553 | #define OR1K_SPR_IMMU_IMMUPR_SXE4_OFFSET 6 |
---|
| 1554 | #define OR1K_SPR_IMMU_IMMUPR_SXE4_MASK 0x00000040 |
---|
| 1555 | #define OR1K_SPR_IMMU_IMMUPR_SXE4_GET(X) (((X) >> 6) & 0x1) |
---|
| 1556 | #define OR1K_SPR_IMMU_IMMUPR_SXE4_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6)) |
---|
| 1557 | |
---|
| 1558 | /* User Execute Enable 4 */ |
---|
| 1559 | #define OR1K_SPR_IMMU_IMMUPR_UXE4_OFFSET 7 |
---|
| 1560 | #define OR1K_SPR_IMMU_IMMUPR_UXE4_MASK 0x00000080 |
---|
| 1561 | #define OR1K_SPR_IMMU_IMMUPR_UXE4_GET(X) (((X) >> 7) & 0x1) |
---|
| 1562 | #define OR1K_SPR_IMMU_IMMUPR_UXE4_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7)) |
---|
| 1563 | |
---|
| 1564 | /* Supervisor Execute Enable 5 */ |
---|
| 1565 | #define OR1K_SPR_IMMU_IMMUPR_SXE5_OFFSET 8 |
---|
| 1566 | #define OR1K_SPR_IMMU_IMMUPR_SXE5_MASK 0x00000100 |
---|
| 1567 | #define OR1K_SPR_IMMU_IMMUPR_SXE5_GET(X) (((X) >> 8) & 0x1) |
---|
| 1568 | #define OR1K_SPR_IMMU_IMMUPR_SXE5_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffeff)) | ((!!(Y)) << 8)) |
---|
| 1569 | |
---|
| 1570 | /* User Execute Enable 5 */ |
---|
| 1571 | #define OR1K_SPR_IMMU_IMMUPR_UXE5_OFFSET 9 |
---|
| 1572 | #define OR1K_SPR_IMMU_IMMUPR_UXE5_MASK 0x00000200 |
---|
| 1573 | #define OR1K_SPR_IMMU_IMMUPR_UXE5_GET(X) (((X) >> 9) & 0x1) |
---|
| 1574 | #define OR1K_SPR_IMMU_IMMUPR_UXE5_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffdff)) | ((!!(Y)) << 9)) |
---|
| 1575 | |
---|
| 1576 | /* Supervisor Execute Enable 6 */ |
---|
| 1577 | #define OR1K_SPR_IMMU_IMMUPR_SXE6_OFFSET 10 |
---|
| 1578 | #define OR1K_SPR_IMMU_IMMUPR_SXE6_MASK 0x00000400 |
---|
| 1579 | #define OR1K_SPR_IMMU_IMMUPR_SXE6_GET(X) (((X) >> 10) & 0x1) |
---|
| 1580 | #define OR1K_SPR_IMMU_IMMUPR_SXE6_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffbff)) | ((!!(Y)) << 10)) |
---|
| 1581 | |
---|
| 1582 | /* User Execute Enable 6 */ |
---|
| 1583 | #define OR1K_SPR_IMMU_IMMUPR_UXE6_OFFSET 11 |
---|
| 1584 | #define OR1K_SPR_IMMU_IMMUPR_UXE6_MASK 0x00000800 |
---|
| 1585 | #define OR1K_SPR_IMMU_IMMUPR_UXE6_GET(X) (((X) >> 11) & 0x1) |
---|
| 1586 | #define OR1K_SPR_IMMU_IMMUPR_UXE6_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffff7ff)) | ((!!(Y)) << 11)) |
---|
| 1587 | |
---|
| 1588 | /* Supervisor Execute Enable 7 */ |
---|
| 1589 | #define OR1K_SPR_IMMU_IMMUPR_SXE7_OFFSET 12 |
---|
| 1590 | #define OR1K_SPR_IMMU_IMMUPR_SXE7_MASK 0x00001000 |
---|
| 1591 | #define OR1K_SPR_IMMU_IMMUPR_SXE7_GET(X) (((X) >> 12) & 0x1) |
---|
| 1592 | #define OR1K_SPR_IMMU_IMMUPR_SXE7_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffefff)) | ((!!(Y)) << 12)) |
---|
| 1593 | |
---|
| 1594 | /* User Execute Enable 7 */ |
---|
| 1595 | #define OR1K_SPR_IMMU_IMMUPR_UXE7_OFFSET 13 |
---|
| 1596 | #define OR1K_SPR_IMMU_IMMUPR_UXE7_MASK 0x00002000 |
---|
| 1597 | #define OR1K_SPR_IMMU_IMMUPR_UXE7_GET(X) (((X) >> 13) & 0x1) |
---|
| 1598 | #define OR1K_SPR_IMMU_IMMUPR_UXE7_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffdfff)) | ((!!(Y)) << 13)) |
---|
| 1599 | |
---|
| 1600 | |
---|
| 1601 | /* Instruction TLB Entry Invalidate Register */ |
---|
| 1602 | #define OR1K_SPR_IMMU_ITLBEIR_INDEX OR1K_UNSIGNED(0x002) |
---|
| 1603 | #define OR1K_SPR_IMMU_ITLBEIR_ADDR OR1K_UNSIGNED(0x1002) |
---|
| 1604 | |
---|
| 1605 | |
---|
| 1606 | /* Instruction ATB Match Registers */ |
---|
| 1607 | #define OR1K_SPR_IMMU_IATBMR_BASE OR1K_UNSIGNED(0x004) |
---|
| 1608 | #define OR1K_SPR_IMMU_IATBMR_COUNT OR1K_UNSIGNED(0x004) |
---|
| 1609 | #define OR1K_SPR_IMMU_IATBMR_STEP OR1K_UNSIGNED(0x001) |
---|
| 1610 | #define OR1K_SPR_IMMU_IATBMR_INDEX(N) (OR1K_SPR_IMMU_IATBMR_BASE + ((N) * OR1K_SPR_IMMU_IATBMR_STEP)) |
---|
| 1611 | #define OR1K_SPR_IMMU_IATBMR_ADDR(N) ((OR1K_SPR_IMMU_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_IMMU_IATBMR_INDEX(N)) |
---|
| 1612 | |
---|
| 1613 | /* Valid */ |
---|
| 1614 | #define OR1K_SPR_IMMU_IATBMR_V_OFFSET 0 |
---|
| 1615 | #define OR1K_SPR_IMMU_IATBMR_V_MASK 0x00000001 |
---|
| 1616 | #define OR1K_SPR_IMMU_IATBMR_V_GET(X) (((X) >> 0) & 0x1) |
---|
| 1617 | #define OR1K_SPR_IMMU_IATBMR_V_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 1618 | |
---|
| 1619 | /* Context ID */ |
---|
| 1620 | #define OR1K_SPR_IMMU_IATBMR_CID_LSB 1 |
---|
| 1621 | #define OR1K_SPR_IMMU_IATBMR_CID_MSB 4 |
---|
| 1622 | #define OR1K_SPR_IMMU_IATBMR_CID_BITS 4 |
---|
| 1623 | #define OR1K_SPR_IMMU_IATBMR_CID_MASK OR1K_UNSIGNED(0x0000001e) |
---|
| 1624 | #define OR1K_SPR_IMMU_IATBMR_CID_GET(X) (((X) >> 1) & OR1K_UNSIGNED(0x0000000f)) |
---|
| 1625 | #define OR1K_SPR_IMMU_IATBMR_CID_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffe1)) | ((Y) << 1)) |
---|
| 1626 | |
---|
| 1627 | /* Page Size */ |
---|
| 1628 | #define OR1K_SPR_IMMU_IATBMR_PS_OFFSET 5 |
---|
| 1629 | #define OR1K_SPR_IMMU_IATBMR_PS_MASK 0x00000020 |
---|
| 1630 | #define OR1K_SPR_IMMU_IATBMR_PS_GET(X) (((X) >> 5) & 0x1) |
---|
| 1631 | #define OR1K_SPR_IMMU_IATBMR_PS_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 1632 | |
---|
| 1633 | /* Virtual Page Number */ |
---|
| 1634 | #define OR1K_SPR_IMMU_IATBMR_VPN_LSB 10 |
---|
| 1635 | #define OR1K_SPR_IMMU_IATBMR_VPN_MSB 31 |
---|
| 1636 | #define OR1K_SPR_IMMU_IATBMR_VPN_BITS 22 |
---|
| 1637 | #define OR1K_SPR_IMMU_IATBMR_VPN_MASK OR1K_UNSIGNED(0xfffffc00) |
---|
| 1638 | #define OR1K_SPR_IMMU_IATBMR_VPN_GET(X) (((X) >> 10) & OR1K_UNSIGNED(0x003fffff)) |
---|
| 1639 | #define OR1K_SPR_IMMU_IATBMR_VPN_SET(X, Y) (((X) & OR1K_UNSIGNED(0x000003ff)) | ((Y) << 10)) |
---|
| 1640 | |
---|
| 1641 | |
---|
| 1642 | /* Instruction ATB Translate Registers */ |
---|
| 1643 | #define OR1K_SPR_IMMU_IATBTR_BASE OR1K_UNSIGNED(0x008) |
---|
| 1644 | #define OR1K_SPR_IMMU_IATBTR_COUNT OR1K_UNSIGNED(0x004) |
---|
| 1645 | #define OR1K_SPR_IMMU_IATBTR_STEP OR1K_UNSIGNED(0x001) |
---|
| 1646 | #define OR1K_SPR_IMMU_IATBTR_INDEX(N) (OR1K_SPR_IMMU_IATBTR_BASE + ((N) * OR1K_SPR_IMMU_IATBTR_STEP)) |
---|
| 1647 | #define OR1K_SPR_IMMU_IATBTR_ADDR(N) ((OR1K_SPR_IMMU_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_IMMU_IATBTR_INDEX(N)) |
---|
| 1648 | |
---|
| 1649 | /* Cache Coherency */ |
---|
| 1650 | #define OR1K_SPR_IMMU_IATBTR_CC_OFFSET 0 |
---|
| 1651 | #define OR1K_SPR_IMMU_IATBTR_CC_MASK 0x00000001 |
---|
| 1652 | #define OR1K_SPR_IMMU_IATBTR_CC_GET(X) (((X) >> 0) & 0x1) |
---|
| 1653 | #define OR1K_SPR_IMMU_IATBTR_CC_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 1654 | |
---|
| 1655 | /* Cache Inhibit */ |
---|
| 1656 | #define OR1K_SPR_IMMU_IATBTR_CI_OFFSET 1 |
---|
| 1657 | #define OR1K_SPR_IMMU_IATBTR_CI_MASK 0x00000002 |
---|
| 1658 | #define OR1K_SPR_IMMU_IATBTR_CI_GET(X) (((X) >> 1) & 0x1) |
---|
| 1659 | #define OR1K_SPR_IMMU_IATBTR_CI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffd)) | ((!!(Y)) << 1)) |
---|
| 1660 | |
---|
| 1661 | /* Write-back Cache */ |
---|
| 1662 | #define OR1K_SPR_IMMU_IATBTR_WBC_OFFSET 2 |
---|
| 1663 | #define OR1K_SPR_IMMU_IATBTR_WBC_MASK 0x00000004 |
---|
| 1664 | #define OR1K_SPR_IMMU_IATBTR_WBC_GET(X) (((X) >> 2) & 0x1) |
---|
| 1665 | #define OR1K_SPR_IMMU_IATBTR_WBC_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffb)) | ((!!(Y)) << 2)) |
---|
| 1666 | |
---|
| 1667 | /* Weakly-ordered Memory */ |
---|
| 1668 | #define OR1K_SPR_IMMU_IATBTR_WOM_OFFSET 3 |
---|
| 1669 | #define OR1K_SPR_IMMU_IATBTR_WOM_MASK 0x00000008 |
---|
| 1670 | #define OR1K_SPR_IMMU_IATBTR_WOM_GET(X) (((X) >> 3) & 0x1) |
---|
| 1671 | #define OR1K_SPR_IMMU_IATBTR_WOM_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff7)) | ((!!(Y)) << 3)) |
---|
| 1672 | |
---|
| 1673 | /* Accessed */ |
---|
| 1674 | #define OR1K_SPR_IMMU_IATBTR_A_OFFSET 4 |
---|
| 1675 | #define OR1K_SPR_IMMU_IATBTR_A_MASK 0x00000010 |
---|
| 1676 | #define OR1K_SPR_IMMU_IATBTR_A_GET(X) (((X) >> 4) & 0x1) |
---|
| 1677 | #define OR1K_SPR_IMMU_IATBTR_A_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffef)) | ((!!(Y)) << 4)) |
---|
| 1678 | |
---|
| 1679 | /* Dirty */ |
---|
| 1680 | #define OR1K_SPR_IMMU_IATBTR_D_OFFSET 5 |
---|
| 1681 | #define OR1K_SPR_IMMU_IATBTR_D_MASK 0x00000020 |
---|
| 1682 | #define OR1K_SPR_IMMU_IATBTR_D_GET(X) (((X) >> 5) & 0x1) |
---|
| 1683 | #define OR1K_SPR_IMMU_IATBTR_D_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 1684 | |
---|
| 1685 | /* Supervisor Execute Enable */ |
---|
| 1686 | #define OR1K_SPR_IMMU_IATBTR_SRE_OFFSET 6 |
---|
| 1687 | #define OR1K_SPR_IMMU_IATBTR_SRE_MASK 0x00000040 |
---|
| 1688 | #define OR1K_SPR_IMMU_IATBTR_SRE_GET(X) (((X) >> 6) & 0x1) |
---|
| 1689 | #define OR1K_SPR_IMMU_IATBTR_SRE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6)) |
---|
| 1690 | |
---|
| 1691 | /* User Execute Enable */ |
---|
| 1692 | #define OR1K_SPR_IMMU_IATBTR_URE_OFFSET 7 |
---|
| 1693 | #define OR1K_SPR_IMMU_IATBTR_URE_MASK 0x00000080 |
---|
| 1694 | #define OR1K_SPR_IMMU_IATBTR_URE_GET(X) (((X) >> 7) & 0x1) |
---|
| 1695 | #define OR1K_SPR_IMMU_IATBTR_URE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7)) |
---|
| 1696 | |
---|
| 1697 | /* Physical Page Number */ |
---|
| 1698 | #define OR1K_SPR_IMMU_IATBTR_PPN_LSB 10 |
---|
| 1699 | #define OR1K_SPR_IMMU_IATBTR_PPN_MSB 31 |
---|
| 1700 | #define OR1K_SPR_IMMU_IATBTR_PPN_BITS 22 |
---|
| 1701 | #define OR1K_SPR_IMMU_IATBTR_PPN_MASK OR1K_UNSIGNED(0xfffffc00) |
---|
| 1702 | #define OR1K_SPR_IMMU_IATBTR_PPN_GET(X) (((X) >> 10) & OR1K_UNSIGNED(0x003fffff)) |
---|
| 1703 | #define OR1K_SPR_IMMU_IATBTR_PPN_SET(X, Y) (((X) & OR1K_UNSIGNED(0x000003ff)) | ((Y) << 10)) |
---|
| 1704 | |
---|
| 1705 | |
---|
| 1706 | /* Instruction TLB */ |
---|
| 1707 | #define OR1K_SPR_IMMU_ITLBW_BASE OR1K_UNSIGNED(0x200) |
---|
| 1708 | #define OR1K_SPR_IMMU_ITLBW_COUNT OR1K_UNSIGNED(0x004) |
---|
| 1709 | #define OR1K_SPR_IMMU_ITLBW_STEP OR1K_UNSIGNED(0x100) |
---|
| 1710 | #define OR1K_SPR_IMMU_ITLBW_SUBBASE(N0) (OR1K_SPR_IMMU_ITLBW_BASE + ((N0)*OR1K_SPR_IMMU_ITLBW_STEP)) |
---|
| 1711 | |
---|
| 1712 | /* Instruction TLB Match Registers */ |
---|
| 1713 | #define OR1K_SPR_IMMU_ITLBW_MR_BASE OR1K_UNSIGNED(0x000) |
---|
| 1714 | #define OR1K_SPR_IMMU_ITLBW_MR_COUNT OR1K_UNSIGNED(0x080) |
---|
| 1715 | #define OR1K_SPR_IMMU_ITLBW_MR_STEP OR1K_UNSIGNED(0x001) |
---|
| 1716 | |
---|
| 1717 | #define OR1K_SPR_IMMU_ITLBW_MR_INDEX(N0, N1) (OR1K_SPR_IMMU_ITLBW_SUBBASE(N0) + OR1K_SPR_IMMU_ITLBW_MR_BASE + ((N1) * OR1K_SPR_IMMU_ITLBW_MR_STEP)) |
---|
| 1718 | #define OR1K_SPR_IMMU_ITLBW_MR_ADDR(N0, N1) ((OR1K_SPR_IMMU_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_IMMU_ITLBW_MR_INDEX(N0, N1)) |
---|
| 1719 | |
---|
| 1720 | /* Valid */ |
---|
| 1721 | #define OR1K_SPR_IMMU_ITLBW_MR_V_OFFSET 0 |
---|
| 1722 | #define OR1K_SPR_IMMU_ITLBW_MR_V_MASK 0x00000001 |
---|
| 1723 | #define OR1K_SPR_IMMU_ITLBW_MR_V_GET(X) (((X) >> 0) & 0x1) |
---|
| 1724 | #define OR1K_SPR_IMMU_ITLBW_MR_V_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 1725 | |
---|
| 1726 | /* Page Level 1 */ |
---|
| 1727 | #define OR1K_SPR_IMMU_ITLBW_MR_PL1_OFFSET 1 |
---|
| 1728 | #define OR1K_SPR_IMMU_ITLBW_MR_PL1_MASK 0x00000002 |
---|
| 1729 | #define OR1K_SPR_IMMU_ITLBW_MR_PL1_GET(X) (((X) >> 1) & 0x1) |
---|
| 1730 | #define OR1K_SPR_IMMU_ITLBW_MR_PL1_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffd)) | ((!!(Y)) << 1)) |
---|
| 1731 | |
---|
| 1732 | /* Context ID */ |
---|
| 1733 | #define OR1K_SPR_IMMU_ITLBW_MR_CID_LSB 2 |
---|
| 1734 | #define OR1K_SPR_IMMU_ITLBW_MR_CID_MSB 5 |
---|
| 1735 | #define OR1K_SPR_IMMU_ITLBW_MR_CID_BITS 4 |
---|
| 1736 | #define OR1K_SPR_IMMU_ITLBW_MR_CID_MASK OR1K_UNSIGNED(0x0000003c) |
---|
| 1737 | #define OR1K_SPR_IMMU_ITLBW_MR_CID_GET(X) (((X) >> 2) & OR1K_UNSIGNED(0x0000000f)) |
---|
| 1738 | #define OR1K_SPR_IMMU_ITLBW_MR_CID_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffc3)) | ((Y) << 2)) |
---|
| 1739 | |
---|
| 1740 | /* Least Recently Used */ |
---|
| 1741 | #define OR1K_SPR_IMMU_ITLBW_MR_LRU_LSB 6 |
---|
| 1742 | #define OR1K_SPR_IMMU_ITLBW_MR_LRU_MSB 7 |
---|
| 1743 | #define OR1K_SPR_IMMU_ITLBW_MR_LRU_BITS 2 |
---|
| 1744 | #define OR1K_SPR_IMMU_ITLBW_MR_LRU_MASK OR1K_UNSIGNED(0x000000c0) |
---|
| 1745 | #define OR1K_SPR_IMMU_ITLBW_MR_LRU_GET(X) (((X) >> 6) & OR1K_UNSIGNED(0x00000003)) |
---|
| 1746 | #define OR1K_SPR_IMMU_ITLBW_MR_LRU_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff3f)) | ((Y) << 6)) |
---|
| 1747 | |
---|
| 1748 | /* Virtual Page Number */ |
---|
| 1749 | #define OR1K_SPR_IMMU_ITLBW_MR_VPN_LSB 13 |
---|
| 1750 | #define OR1K_SPR_IMMU_ITLBW_MR_VPN_MSB 31 |
---|
| 1751 | #define OR1K_SPR_IMMU_ITLBW_MR_VPN_BITS 19 |
---|
| 1752 | #define OR1K_SPR_IMMU_ITLBW_MR_VPN_MASK OR1K_UNSIGNED(0xffffe000) |
---|
| 1753 | #define OR1K_SPR_IMMU_ITLBW_MR_VPN_GET(X) (((X) >> 13) & OR1K_UNSIGNED(0x0007ffff)) |
---|
| 1754 | #define OR1K_SPR_IMMU_ITLBW_MR_VPN_SET(X, Y) (((X) & OR1K_UNSIGNED(0x00001fff)) | ((Y) << 13)) |
---|
| 1755 | |
---|
| 1756 | /* Instruction TLB Translate Registers */ |
---|
| 1757 | #define OR1K_SPR_IMMU_ITLBW_TR_BASE OR1K_UNSIGNED(0x080) |
---|
| 1758 | #define OR1K_SPR_IMMU_ITLBW_TR_COUNT OR1K_UNSIGNED(0x080) |
---|
| 1759 | #define OR1K_SPR_IMMU_ITLBW_TR_STEP OR1K_UNSIGNED(0x001) |
---|
| 1760 | |
---|
| 1761 | #define OR1K_SPR_IMMU_ITLBW_TR_INDEX(N0, N1) (OR1K_SPR_IMMU_ITLBW_SUBBASE(N0) + OR1K_SPR_IMMU_ITLBW_TR_BASE + ((N1) * OR1K_SPR_IMMU_ITLBW_TR_STEP)) |
---|
| 1762 | #define OR1K_SPR_IMMU_ITLBW_TR_ADDR(N0, N1) ((OR1K_SPR_IMMU_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_IMMU_ITLBW_TR_INDEX(N0, N1)) |
---|
| 1763 | |
---|
| 1764 | /* Cache Coherency */ |
---|
| 1765 | #define OR1K_SPR_IMMU_ITLBW_TR_CC_OFFSET 0 |
---|
| 1766 | #define OR1K_SPR_IMMU_ITLBW_TR_CC_MASK 0x00000001 |
---|
| 1767 | #define OR1K_SPR_IMMU_ITLBW_TR_CC_GET(X) (((X) >> 0) & 0x1) |
---|
| 1768 | #define OR1K_SPR_IMMU_ITLBW_TR_CC_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 1769 | |
---|
| 1770 | /* Cache Inhibit */ |
---|
| 1771 | #define OR1K_SPR_IMMU_ITLBW_TR_CI_OFFSET 1 |
---|
| 1772 | #define OR1K_SPR_IMMU_ITLBW_TR_CI_MASK 0x00000002 |
---|
| 1773 | #define OR1K_SPR_IMMU_ITLBW_TR_CI_GET(X) (((X) >> 1) & 0x1) |
---|
| 1774 | #define OR1K_SPR_IMMU_ITLBW_TR_CI_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffd)) | ((!!(Y)) << 1)) |
---|
| 1775 | |
---|
| 1776 | /* Write-back Cache */ |
---|
| 1777 | #define OR1K_SPR_IMMU_ITLBW_TR_WBC_OFFSET 2 |
---|
| 1778 | #define OR1K_SPR_IMMU_ITLBW_TR_WBC_MASK 0x00000004 |
---|
| 1779 | #define OR1K_SPR_IMMU_ITLBW_TR_WBC_GET(X) (((X) >> 2) & 0x1) |
---|
| 1780 | #define OR1K_SPR_IMMU_ITLBW_TR_WBC_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffb)) | ((!!(Y)) << 2)) |
---|
| 1781 | |
---|
| 1782 | /* Weakly-ordered Memory */ |
---|
| 1783 | #define OR1K_SPR_IMMU_ITLBW_TR_WOM_OFFSET 3 |
---|
| 1784 | #define OR1K_SPR_IMMU_ITLBW_TR_WOM_MASK 0x00000008 |
---|
| 1785 | #define OR1K_SPR_IMMU_ITLBW_TR_WOM_GET(X) (((X) >> 3) & 0x1) |
---|
| 1786 | #define OR1K_SPR_IMMU_ITLBW_TR_WOM_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff7)) | ((!!(Y)) << 3)) |
---|
| 1787 | |
---|
| 1788 | /* Accessed */ |
---|
| 1789 | #define OR1K_SPR_IMMU_ITLBW_TR_A_OFFSET 4 |
---|
| 1790 | #define OR1K_SPR_IMMU_ITLBW_TR_A_MASK 0x00000010 |
---|
| 1791 | #define OR1K_SPR_IMMU_ITLBW_TR_A_GET(X) (((X) >> 4) & 0x1) |
---|
| 1792 | #define OR1K_SPR_IMMU_ITLBW_TR_A_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffef)) | ((!!(Y)) << 4)) |
---|
| 1793 | |
---|
| 1794 | /* Dirty */ |
---|
| 1795 | #define OR1K_SPR_IMMU_ITLBW_TR_D_OFFSET 5 |
---|
| 1796 | #define OR1K_SPR_IMMU_ITLBW_TR_D_MASK 0x00000020 |
---|
| 1797 | #define OR1K_SPR_IMMU_ITLBW_TR_D_GET(X) (((X) >> 5) & 0x1) |
---|
| 1798 | #define OR1K_SPR_IMMU_ITLBW_TR_D_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 1799 | |
---|
| 1800 | /* User Execute Enable */ |
---|
| 1801 | #define OR1K_SPR_IMMU_ITLBW_TR_UXE_OFFSET 6 |
---|
| 1802 | #define OR1K_SPR_IMMU_ITLBW_TR_UXE_MASK 0x00000040 |
---|
| 1803 | #define OR1K_SPR_IMMU_ITLBW_TR_UXE_GET(X) (((X) >> 6) & 0x1) |
---|
| 1804 | #define OR1K_SPR_IMMU_ITLBW_TR_UXE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6)) |
---|
| 1805 | |
---|
| 1806 | /* Supervisor Execute Enable */ |
---|
| 1807 | #define OR1K_SPR_IMMU_ITLBW_TR_SXE_OFFSET 7 |
---|
| 1808 | #define OR1K_SPR_IMMU_ITLBW_TR_SXE_MASK 0x00000080 |
---|
| 1809 | #define OR1K_SPR_IMMU_ITLBW_TR_SXE_GET(X) (((X) >> 7) & 0x1) |
---|
| 1810 | #define OR1K_SPR_IMMU_ITLBW_TR_SXE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7)) |
---|
| 1811 | |
---|
| 1812 | /* Physical Page Number */ |
---|
| 1813 | #define OR1K_SPR_IMMU_ITLBW_TR_PPN_LSB 13 |
---|
| 1814 | #define OR1K_SPR_IMMU_ITLBW_TR_PPN_MSB 31 |
---|
| 1815 | #define OR1K_SPR_IMMU_ITLBW_TR_PPN_BITS 19 |
---|
| 1816 | #define OR1K_SPR_IMMU_ITLBW_TR_PPN_MASK OR1K_UNSIGNED(0xffffe000) |
---|
| 1817 | #define OR1K_SPR_IMMU_ITLBW_TR_PPN_GET(X) (((X) >> 13) & OR1K_UNSIGNED(0x0007ffff)) |
---|
| 1818 | #define OR1K_SPR_IMMU_ITLBW_TR_PPN_SET(X, Y) (((X) & OR1K_UNSIGNED(0x00001fff)) | ((Y) << 13)) |
---|
| 1819 | |
---|
| 1820 | |
---|
| 1821 | /********************/ |
---|
| 1822 | /* Data Cache Group */ |
---|
| 1823 | /********************/ |
---|
| 1824 | #define OR1K_SPR_DCACHE_GROUP 0x03 |
---|
| 1825 | |
---|
| 1826 | /* Data Cache Control Register */ |
---|
| 1827 | #define OR1K_SPR_DCACHE_DCCR_INDEX OR1K_UNSIGNED(0x000) |
---|
| 1828 | #define OR1K_SPR_DCACHE_DCCR_ADDR OR1K_UNSIGNED(0x1800) |
---|
| 1829 | |
---|
| 1830 | /* Enable Ways */ |
---|
| 1831 | #define OR1K_SPR_DCACHE_DCCR_EW_LSB 0 |
---|
| 1832 | #define OR1K_SPR_DCACHE_DCCR_EW_MSB 7 |
---|
| 1833 | #define OR1K_SPR_DCACHE_DCCR_EW_BITS 8 |
---|
| 1834 | #define OR1K_SPR_DCACHE_DCCR_EW_MASK OR1K_UNSIGNED(0x000000ff) |
---|
| 1835 | #define OR1K_SPR_DCACHE_DCCR_EW_GET(X) (((X) >> 0) & OR1K_UNSIGNED(0x000000ff)) |
---|
| 1836 | #define OR1K_SPR_DCACHE_DCCR_EW_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff00)) | ((Y) << 0)) |
---|
| 1837 | |
---|
| 1838 | |
---|
| 1839 | /* Data Cache Block Prefetch Register */ |
---|
| 1840 | #define OR1K_SPR_DCACHE_DCBPR_INDEX OR1K_UNSIGNED(0x001) |
---|
| 1841 | #define OR1K_SPR_DCACHE_DCBPR_ADDR OR1K_UNSIGNED(0x1801) |
---|
| 1842 | |
---|
| 1843 | |
---|
| 1844 | /* Data Cache Block Flush Register */ |
---|
| 1845 | #define OR1K_SPR_DCACHE_DCBFR_INDEX OR1K_UNSIGNED(0x002) |
---|
| 1846 | #define OR1K_SPR_DCACHE_DCBFR_ADDR OR1K_UNSIGNED(0x1802) |
---|
| 1847 | |
---|
| 1848 | |
---|
| 1849 | /* Data Cache Block Invalidate Register */ |
---|
| 1850 | #define OR1K_SPR_DCACHE_DCBIR_INDEX OR1K_UNSIGNED(0x003) |
---|
| 1851 | #define OR1K_SPR_DCACHE_DCBIR_ADDR OR1K_UNSIGNED(0x1803) |
---|
| 1852 | |
---|
| 1853 | |
---|
| 1854 | /* Data Cache Block Write-back Register */ |
---|
| 1855 | #define OR1K_SPR_DCACHE_DCBWR_INDEX OR1K_UNSIGNED(0x004) |
---|
| 1856 | #define OR1K_SPR_DCACHE_DCBWR_ADDR OR1K_UNSIGNED(0x1804) |
---|
| 1857 | |
---|
| 1858 | |
---|
| 1859 | /* Data Cache Block Lock Register */ |
---|
| 1860 | #define OR1K_SPR_DCACHE_DCBLR_INDEX OR1K_UNSIGNED(0x005) |
---|
| 1861 | #define OR1K_SPR_DCACHE_DCBLR_ADDR OR1K_UNSIGNED(0x1805) |
---|
| 1862 | |
---|
| 1863 | |
---|
| 1864 | /***************************/ |
---|
| 1865 | /* Instruction Cache Group */ |
---|
| 1866 | /***************************/ |
---|
| 1867 | #define OR1K_SPR_ICACHE_GROUP 0x04 |
---|
| 1868 | |
---|
| 1869 | /* Instruction Cache Control Register */ |
---|
| 1870 | #define OR1K_SPR_ICACHE_ICCR_INDEX OR1K_UNSIGNED(0x000) |
---|
| 1871 | #define OR1K_SPR_ICACHE_ICCR_ADDR OR1K_UNSIGNED(0x2000) |
---|
| 1872 | |
---|
| 1873 | /* Enable Ways */ |
---|
| 1874 | #define OR1K_SPR_ICACHE_ICCR_EW_LSB 0 |
---|
| 1875 | #define OR1K_SPR_ICACHE_ICCR_EW_MSB 7 |
---|
| 1876 | #define OR1K_SPR_ICACHE_ICCR_EW_BITS 8 |
---|
| 1877 | #define OR1K_SPR_ICACHE_ICCR_EW_MASK OR1K_UNSIGNED(0x000000ff) |
---|
| 1878 | #define OR1K_SPR_ICACHE_ICCR_EW_GET(X) (((X) >> 0) & OR1K_UNSIGNED(0x000000ff)) |
---|
| 1879 | #define OR1K_SPR_ICACHE_ICCR_EW_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff00)) | ((Y) << 0)) |
---|
| 1880 | |
---|
| 1881 | |
---|
| 1882 | /* Instruction Cache Block Prefetch Register */ |
---|
| 1883 | #define OR1K_SPR_ICACHE_ICBPR_INDEX OR1K_UNSIGNED(0x001) |
---|
| 1884 | #define OR1K_SPR_ICACHE_ICBPR_ADDR OR1K_UNSIGNED(0x2001) |
---|
| 1885 | |
---|
| 1886 | |
---|
| 1887 | /* Instruction Cache Block Invalidate Register */ |
---|
| 1888 | #define OR1K_SPR_ICACHE_ICBIR_INDEX OR1K_UNSIGNED(0x002) |
---|
| 1889 | #define OR1K_SPR_ICACHE_ICBIR_ADDR OR1K_UNSIGNED(0x2002) |
---|
| 1890 | |
---|
| 1891 | |
---|
| 1892 | /* Instruction Cache Block Lock Register */ |
---|
| 1893 | #define OR1K_SPR_ICACHE_ICBLR_INDEX OR1K_UNSIGNED(0x003) |
---|
| 1894 | #define OR1K_SPR_ICACHE_ICBLR_ADDR OR1K_UNSIGNED(0x2003) |
---|
| 1895 | |
---|
| 1896 | |
---|
| 1897 | /*********************************/ |
---|
| 1898 | /* Multiply and Accumulate Group */ |
---|
| 1899 | /*********************************/ |
---|
| 1900 | #define OR1K_SPR_MAC_GROUP 0x05 |
---|
| 1901 | |
---|
| 1902 | /* MAC Result Low Word */ |
---|
| 1903 | #define OR1K_SPR_MAC_MACLO_INDEX OR1K_UNSIGNED(0x001) |
---|
| 1904 | #define OR1K_SPR_MAC_MACLO_ADDR OR1K_UNSIGNED(0x2801) |
---|
| 1905 | |
---|
| 1906 | |
---|
| 1907 | /* MAC Result High Word */ |
---|
| 1908 | #define OR1K_SPR_MAC_MACHI_INDEX OR1K_UNSIGNED(0x002) |
---|
| 1909 | #define OR1K_SPR_MAC_MACHI_ADDR OR1K_UNSIGNED(0x2802) |
---|
| 1910 | |
---|
| 1911 | |
---|
| 1912 | /***************/ |
---|
| 1913 | /* Debug Group */ |
---|
| 1914 | /***************/ |
---|
| 1915 | #define OR1K_SPR_DEBUG_GROUP 0x06 |
---|
| 1916 | |
---|
| 1917 | /* Debug Value Registers */ |
---|
| 1918 | #define OR1K_SPR_DEBUG_DVR_BASE OR1K_UNSIGNED(0x000) |
---|
| 1919 | #define OR1K_SPR_DEBUG_DVR_COUNT OR1K_UNSIGNED(0x008) |
---|
| 1920 | #define OR1K_SPR_DEBUG_DVR_STEP OR1K_UNSIGNED(0x001) |
---|
| 1921 | #define OR1K_SPR_DEBUG_DVR_INDEX(N) (OR1K_SPR_DEBUG_DVR_BASE + ((N) * OR1K_SPR_DEBUG_DVR_STEP)) |
---|
| 1922 | #define OR1K_SPR_DEBUG_DVR_ADDR(N) ((OR1K_SPR_DEBUG_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_DEBUG_DVR_INDEX(N)) |
---|
| 1923 | |
---|
| 1924 | |
---|
| 1925 | /* Debug Control Registers */ |
---|
| 1926 | #define OR1K_SPR_DEBUG_DCR_BASE OR1K_UNSIGNED(0x008) |
---|
| 1927 | #define OR1K_SPR_DEBUG_DCR_COUNT OR1K_UNSIGNED(0x008) |
---|
| 1928 | #define OR1K_SPR_DEBUG_DCR_STEP OR1K_UNSIGNED(0x001) |
---|
| 1929 | #define OR1K_SPR_DEBUG_DCR_INDEX(N) (OR1K_SPR_DEBUG_DCR_BASE + ((N) * OR1K_SPR_DEBUG_DCR_STEP)) |
---|
| 1930 | #define OR1K_SPR_DEBUG_DCR_ADDR(N) ((OR1K_SPR_DEBUG_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_DEBUG_DCR_INDEX(N)) |
---|
| 1931 | |
---|
| 1932 | /* DVR/DCR Present */ |
---|
| 1933 | #define OR1K_SPR_DEBUG_DCR_DP_OFFSET 0 |
---|
| 1934 | #define OR1K_SPR_DEBUG_DCR_DP_MASK 0x00000001 |
---|
| 1935 | #define OR1K_SPR_DEBUG_DCR_DP_GET(X) (((X) >> 0) & 0x1) |
---|
| 1936 | #define OR1K_SPR_DEBUG_DCR_DP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 1937 | |
---|
| 1938 | /* Compare Condition */ |
---|
| 1939 | #define OR1K_SPR_DEBUG_DCR_CC_LSB 1 |
---|
| 1940 | #define OR1K_SPR_DEBUG_DCR_CC_MSB 3 |
---|
| 1941 | #define OR1K_SPR_DEBUG_DCR_CC_BITS 3 |
---|
| 1942 | #define OR1K_SPR_DEBUG_DCR_CC_MASK OR1K_UNSIGNED(0x0000000e) |
---|
| 1943 | #define OR1K_SPR_DEBUG_DCR_CC_GET(X) (((X) >> 1) & OR1K_UNSIGNED(0x00000007)) |
---|
| 1944 | #define OR1K_SPR_DEBUG_DCR_CC_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff1)) | ((Y) << 1)) |
---|
| 1945 | |
---|
| 1946 | /* Masked */ |
---|
| 1947 | #define OR1K_SPR_DEBUG_DCR_CC_MASKED 0 |
---|
| 1948 | /* Equal */ |
---|
| 1949 | #define OR1K_SPR_DEBUG_DCR_CC_EQ 1 |
---|
| 1950 | /* Less than */ |
---|
| 1951 | #define OR1K_SPR_DEBUG_DCR_CC_LT 2 |
---|
| 1952 | /* Less than or equal */ |
---|
| 1953 | #define OR1K_SPR_DEBUG_DCR_CC_LTE 3 |
---|
| 1954 | /* Greater than */ |
---|
| 1955 | #define OR1K_SPR_DEBUG_DCR_CC_GT 4 |
---|
| 1956 | /* Greater than or equal */ |
---|
| 1957 | #define OR1K_SPR_DEBUG_DCR_CC_GTE 5 |
---|
| 1958 | /* Not equal */ |
---|
| 1959 | #define OR1K_SPR_DEBUG_DCR_CC_NEQ 6 |
---|
| 1960 | /* Signed Comparison */ |
---|
| 1961 | #define OR1K_SPR_DEBUG_DCR_SC_OFFSET 4 |
---|
| 1962 | #define OR1K_SPR_DEBUG_DCR_SC_MASK 0x00000010 |
---|
| 1963 | #define OR1K_SPR_DEBUG_DCR_SC_GET(X) (((X) >> 4) & 0x1) |
---|
| 1964 | #define OR1K_SPR_DEBUG_DCR_SC_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffef)) | ((!!(Y)) << 4)) |
---|
| 1965 | |
---|
| 1966 | /* Compare To */ |
---|
| 1967 | #define OR1K_SPR_DEBUG_DCR_CT_LSB 5 |
---|
| 1968 | #define OR1K_SPR_DEBUG_DCR_CT_MSB 7 |
---|
| 1969 | #define OR1K_SPR_DEBUG_DCR_CT_BITS 3 |
---|
| 1970 | #define OR1K_SPR_DEBUG_DCR_CT_MASK OR1K_UNSIGNED(0x000000e0) |
---|
| 1971 | #define OR1K_SPR_DEBUG_DCR_CT_GET(X) (((X) >> 5) & OR1K_UNSIGNED(0x00000007)) |
---|
| 1972 | #define OR1K_SPR_DEBUG_DCR_CT_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff1f)) | ((Y) << 5)) |
---|
| 1973 | |
---|
| 1974 | /* Comparison disabled */ |
---|
| 1975 | #define OR1K_SPR_DEBUG_DCR_CT_DISABLED 0 |
---|
| 1976 | /* Instruction fetch EA */ |
---|
| 1977 | #define OR1K_SPR_DEBUG_DCR_CT_FEA 1 |
---|
| 1978 | /* Load EA */ |
---|
| 1979 | #define OR1K_SPR_DEBUG_DCR_CT_LEA 2 |
---|
| 1980 | /* Store EA */ |
---|
| 1981 | #define OR1K_SPR_DEBUG_DCR_CT_SEA 3 |
---|
| 1982 | /* Load data */ |
---|
| 1983 | #define OR1K_SPR_DEBUG_DCR_CT_LD 4 |
---|
| 1984 | /* Store data */ |
---|
| 1985 | #define OR1K_SPR_DEBUG_DCR_CT_SD 5 |
---|
| 1986 | /* Load/store EA */ |
---|
| 1987 | #define OR1K_SPR_DEBUG_DCR_CT_LSEA 6 |
---|
| 1988 | /* Load/store data */ |
---|
| 1989 | #define OR1K_SPR_DEBUG_DCR_CT_LSD 7 |
---|
| 1990 | |
---|
| 1991 | /* Debug Mode Register 1 */ |
---|
| 1992 | #define OR1K_SPR_DEBUG_DMR1_INDEX OR1K_UNSIGNED(0x010) |
---|
| 1993 | #define OR1K_SPR_DEBUG_DMR1_ADDR OR1K_UNSIGNED(0x3010) |
---|
| 1994 | |
---|
| 1995 | /* Chain Watchpoint 0 */ |
---|
| 1996 | #define OR1K_SPR_DEBUG_DMR1_CW0_LSB 0 |
---|
| 1997 | #define OR1K_SPR_DEBUG_DMR1_CW0_MSB 1 |
---|
| 1998 | #define OR1K_SPR_DEBUG_DMR1_CW0_BITS 2 |
---|
| 1999 | #define OR1K_SPR_DEBUG_DMR1_CW0_MASK OR1K_UNSIGNED(0x00000003) |
---|
| 2000 | #define OR1K_SPR_DEBUG_DMR1_CW0_GET(X) (((X) >> 0) & OR1K_UNSIGNED(0x00000003)) |
---|
| 2001 | #define OR1K_SPR_DEBUG_DMR1_CW0_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffc)) | ((Y) << 0)) |
---|
| 2002 | |
---|
| 2003 | /* Chain Watchpoint 1 */ |
---|
| 2004 | #define OR1K_SPR_DEBUG_DMR1_CW1_LSB 2 |
---|
| 2005 | #define OR1K_SPR_DEBUG_DMR1_CW1_MSB 3 |
---|
| 2006 | #define OR1K_SPR_DEBUG_DMR1_CW1_BITS 2 |
---|
| 2007 | #define OR1K_SPR_DEBUG_DMR1_CW1_MASK OR1K_UNSIGNED(0x0000000c) |
---|
| 2008 | #define OR1K_SPR_DEBUG_DMR1_CW1_GET(X) (((X) >> 2) & OR1K_UNSIGNED(0x00000003)) |
---|
| 2009 | #define OR1K_SPR_DEBUG_DMR1_CW1_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff3)) | ((Y) << 2)) |
---|
| 2010 | |
---|
| 2011 | /* Chain Watchpoint 2 */ |
---|
| 2012 | #define OR1K_SPR_DEBUG_DMR1_CW2_LSB 4 |
---|
| 2013 | #define OR1K_SPR_DEBUG_DMR1_CW2_MSB 5 |
---|
| 2014 | #define OR1K_SPR_DEBUG_DMR1_CW2_BITS 2 |
---|
| 2015 | #define OR1K_SPR_DEBUG_DMR1_CW2_MASK OR1K_UNSIGNED(0x00000030) |
---|
| 2016 | #define OR1K_SPR_DEBUG_DMR1_CW2_GET(X) (((X) >> 4) & OR1K_UNSIGNED(0x00000003)) |
---|
| 2017 | #define OR1K_SPR_DEBUG_DMR1_CW2_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffcf)) | ((Y) << 4)) |
---|
| 2018 | |
---|
| 2019 | /* Chain Watchpoint 3 */ |
---|
| 2020 | #define OR1K_SPR_DEBUG_DMR1_CW3_LSB 6 |
---|
| 2021 | #define OR1K_SPR_DEBUG_DMR1_CW3_MSB 7 |
---|
| 2022 | #define OR1K_SPR_DEBUG_DMR1_CW3_BITS 2 |
---|
| 2023 | #define OR1K_SPR_DEBUG_DMR1_CW3_MASK OR1K_UNSIGNED(0x000000c0) |
---|
| 2024 | #define OR1K_SPR_DEBUG_DMR1_CW3_GET(X) (((X) >> 6) & OR1K_UNSIGNED(0x00000003)) |
---|
| 2025 | #define OR1K_SPR_DEBUG_DMR1_CW3_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff3f)) | ((Y) << 6)) |
---|
| 2026 | |
---|
| 2027 | /* Chain Watchpoint 4 */ |
---|
| 2028 | #define OR1K_SPR_DEBUG_DMR1_CW4_LSB 9 |
---|
| 2029 | #define OR1K_SPR_DEBUG_DMR1_CW4_MSB 9 |
---|
| 2030 | #define OR1K_SPR_DEBUG_DMR1_CW4_BITS 1 |
---|
| 2031 | #define OR1K_SPR_DEBUG_DMR1_CW4_MASK OR1K_UNSIGNED(0x00000200) |
---|
| 2032 | #define OR1K_SPR_DEBUG_DMR1_CW4_GET(X) (((X) >> 9) & OR1K_UNSIGNED(0x00000001)) |
---|
| 2033 | #define OR1K_SPR_DEBUG_DMR1_CW4_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffdff)) | ((Y) << 9)) |
---|
| 2034 | |
---|
| 2035 | /* Chain Watchpoint 5 */ |
---|
| 2036 | #define OR1K_SPR_DEBUG_DMR1_CW5_LSB 10 |
---|
| 2037 | #define OR1K_SPR_DEBUG_DMR1_CW5_MSB 11 |
---|
| 2038 | #define OR1K_SPR_DEBUG_DMR1_CW5_BITS 2 |
---|
| 2039 | #define OR1K_SPR_DEBUG_DMR1_CW5_MASK OR1K_UNSIGNED(0x00000c00) |
---|
| 2040 | #define OR1K_SPR_DEBUG_DMR1_CW5_GET(X) (((X) >> 10) & OR1K_UNSIGNED(0x00000003)) |
---|
| 2041 | #define OR1K_SPR_DEBUG_DMR1_CW5_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffff3ff)) | ((Y) << 10)) |
---|
| 2042 | |
---|
| 2043 | /* Chain Watchpoint 6 */ |
---|
| 2044 | #define OR1K_SPR_DEBUG_DMR1_CW6_LSB 12 |
---|
| 2045 | #define OR1K_SPR_DEBUG_DMR1_CW6_MSB 13 |
---|
| 2046 | #define OR1K_SPR_DEBUG_DMR1_CW6_BITS 2 |
---|
| 2047 | #define OR1K_SPR_DEBUG_DMR1_CW6_MASK OR1K_UNSIGNED(0x00003000) |
---|
| 2048 | #define OR1K_SPR_DEBUG_DMR1_CW6_GET(X) (((X) >> 12) & OR1K_UNSIGNED(0x00000003)) |
---|
| 2049 | #define OR1K_SPR_DEBUG_DMR1_CW6_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffcfff)) | ((Y) << 12)) |
---|
| 2050 | |
---|
| 2051 | /* Chain Watchpoint 7 */ |
---|
| 2052 | #define OR1K_SPR_DEBUG_DMR1_CW7_LSB 14 |
---|
| 2053 | #define OR1K_SPR_DEBUG_DMR1_CW7_MSB 15 |
---|
| 2054 | #define OR1K_SPR_DEBUG_DMR1_CW7_BITS 2 |
---|
| 2055 | #define OR1K_SPR_DEBUG_DMR1_CW7_MASK OR1K_UNSIGNED(0x0000c000) |
---|
| 2056 | #define OR1K_SPR_DEBUG_DMR1_CW7_GET(X) (((X) >> 14) & OR1K_UNSIGNED(0x00000003)) |
---|
| 2057 | #define OR1K_SPR_DEBUG_DMR1_CW7_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffff3fff)) | ((Y) << 14)) |
---|
| 2058 | |
---|
| 2059 | /* Chain Watchpoint 8 */ |
---|
| 2060 | #define OR1K_SPR_DEBUG_DMR1_CW8_LSB 16 |
---|
| 2061 | #define OR1K_SPR_DEBUG_DMR1_CW8_MSB 17 |
---|
| 2062 | #define OR1K_SPR_DEBUG_DMR1_CW8_BITS 2 |
---|
| 2063 | #define OR1K_SPR_DEBUG_DMR1_CW8_MASK OR1K_UNSIGNED(0x00030000) |
---|
| 2064 | #define OR1K_SPR_DEBUG_DMR1_CW8_GET(X) (((X) >> 16) & OR1K_UNSIGNED(0x00000003)) |
---|
| 2065 | #define OR1K_SPR_DEBUG_DMR1_CW8_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffcffff)) | ((Y) << 16)) |
---|
| 2066 | |
---|
| 2067 | /* Chain Watchpoint 9 */ |
---|
| 2068 | #define OR1K_SPR_DEBUG_DMR1_CW9_LSB 18 |
---|
| 2069 | #define OR1K_SPR_DEBUG_DMR1_CW9_MSB 19 |
---|
| 2070 | #define OR1K_SPR_DEBUG_DMR1_CW9_BITS 2 |
---|
| 2071 | #define OR1K_SPR_DEBUG_DMR1_CW9_MASK OR1K_UNSIGNED(0x000c0000) |
---|
| 2072 | #define OR1K_SPR_DEBUG_DMR1_CW9_GET(X) (((X) >> 18) & OR1K_UNSIGNED(0x00000003)) |
---|
| 2073 | #define OR1K_SPR_DEBUG_DMR1_CW9_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfff3ffff)) | ((Y) << 18)) |
---|
| 2074 | |
---|
| 2075 | /* Single-step Trace */ |
---|
| 2076 | #define OR1K_SPR_DEBUG_DMR1_ST_OFFSET 22 |
---|
| 2077 | #define OR1K_SPR_DEBUG_DMR1_ST_MASK 0x00400000 |
---|
| 2078 | #define OR1K_SPR_DEBUG_DMR1_ST_GET(X) (((X) >> 22) & 0x1) |
---|
| 2079 | #define OR1K_SPR_DEBUG_DMR1_ST_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffbfffff)) | ((!!(Y)) << 22)) |
---|
| 2080 | |
---|
| 2081 | /* Branch Trace */ |
---|
| 2082 | #define OR1K_SPR_DEBUG_DMR1_BT_OFFSET 23 |
---|
| 2083 | #define OR1K_SPR_DEBUG_DMR1_BT_MASK 0x00800000 |
---|
| 2084 | #define OR1K_SPR_DEBUG_DMR1_BT_GET(X) (((X) >> 23) & 0x1) |
---|
| 2085 | #define OR1K_SPR_DEBUG_DMR1_BT_SET(X, Y) (((X) & OR1K_UNSIGNED(0xff7fffff)) | ((!!(Y)) << 23)) |
---|
| 2086 | |
---|
| 2087 | |
---|
| 2088 | /* Debug Mode Register 2 */ |
---|
| 2089 | #define OR1K_SPR_DEBUG_DMR2_INDEX OR1K_UNSIGNED(0x011) |
---|
| 2090 | #define OR1K_SPR_DEBUG_DMR2_ADDR OR1K_UNSIGNED(0x3011) |
---|
| 2091 | |
---|
| 2092 | /* Watchpoint Counter Enable 0 */ |
---|
| 2093 | #define OR1K_SPR_DEBUG_DMR2_WCE0_OFFSET 0 |
---|
| 2094 | #define OR1K_SPR_DEBUG_DMR2_WCE0_MASK 0x00000001 |
---|
| 2095 | #define OR1K_SPR_DEBUG_DMR2_WCE0_GET(X) (((X) >> 0) & 0x1) |
---|
| 2096 | #define OR1K_SPR_DEBUG_DMR2_WCE0_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 2097 | |
---|
| 2098 | /* Watchpoint Counter Enable 1 */ |
---|
| 2099 | #define OR1K_SPR_DEBUG_DMR2_WCE1_OFFSET 1 |
---|
| 2100 | #define OR1K_SPR_DEBUG_DMR2_WCE1_MASK 0x00000002 |
---|
| 2101 | #define OR1K_SPR_DEBUG_DMR2_WCE1_GET(X) (((X) >> 1) & 0x1) |
---|
| 2102 | #define OR1K_SPR_DEBUG_DMR2_WCE1_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffd)) | ((!!(Y)) << 1)) |
---|
| 2103 | |
---|
| 2104 | /* Assign Watchpoints to Counter */ |
---|
| 2105 | #define OR1K_SPR_DEBUG_DMR2_AWTC_LSB 2 |
---|
| 2106 | #define OR1K_SPR_DEBUG_DMR2_AWTC_MSB 11 |
---|
| 2107 | #define OR1K_SPR_DEBUG_DMR2_AWTC_BITS 10 |
---|
| 2108 | #define OR1K_SPR_DEBUG_DMR2_AWTC_MASK OR1K_UNSIGNED(0x00000ffc) |
---|
| 2109 | #define OR1K_SPR_DEBUG_DMR2_AWTC_GET(X) (((X) >> 2) & OR1K_UNSIGNED(0x000003ff)) |
---|
| 2110 | #define OR1K_SPR_DEBUG_DMR2_AWTC_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffff003)) | ((Y) << 2)) |
---|
| 2111 | |
---|
| 2112 | /* Watchpoints Generating Breakpoint */ |
---|
| 2113 | #define OR1K_SPR_DEBUG_DMR2_WGB_LSB 12 |
---|
| 2114 | #define OR1K_SPR_DEBUG_DMR2_WGB_MSB 21 |
---|
| 2115 | #define OR1K_SPR_DEBUG_DMR2_WGB_BITS 10 |
---|
| 2116 | #define OR1K_SPR_DEBUG_DMR2_WGB_MASK OR1K_UNSIGNED(0x003ff000) |
---|
| 2117 | #define OR1K_SPR_DEBUG_DMR2_WGB_GET(X) (((X) >> 12) & OR1K_UNSIGNED(0x000003ff)) |
---|
| 2118 | #define OR1K_SPR_DEBUG_DMR2_WGB_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffc00fff)) | ((Y) << 12)) |
---|
| 2119 | |
---|
| 2120 | /* Watchpoints Breakpoint Status */ |
---|
| 2121 | #define OR1K_SPR_DEBUG_DMR2_WBS_LSB 22 |
---|
| 2122 | #define OR1K_SPR_DEBUG_DMR2_WBS_MSB 31 |
---|
| 2123 | #define OR1K_SPR_DEBUG_DMR2_WBS_BITS 10 |
---|
| 2124 | #define OR1K_SPR_DEBUG_DMR2_WBS_MASK OR1K_UNSIGNED(0xffc00000) |
---|
| 2125 | #define OR1K_SPR_DEBUG_DMR2_WBS_GET(X) (((X) >> 22) & OR1K_UNSIGNED(0x000003ff)) |
---|
| 2126 | #define OR1K_SPR_DEBUG_DMR2_WBS_SET(X, Y) (((X) & OR1K_UNSIGNED(0x003fffff)) | ((Y) << 22)) |
---|
| 2127 | |
---|
| 2128 | |
---|
| 2129 | /* Debug Watchpoint Counter Registers */ |
---|
| 2130 | #define OR1K_SPR_DEBUG_DCWR_BASE OR1K_UNSIGNED(0x012) |
---|
| 2131 | #define OR1K_SPR_DEBUG_DCWR_COUNT OR1K_UNSIGNED(0x002) |
---|
| 2132 | #define OR1K_SPR_DEBUG_DCWR_STEP OR1K_UNSIGNED(0x001) |
---|
| 2133 | #define OR1K_SPR_DEBUG_DCWR_INDEX(N) (OR1K_SPR_DEBUG_DCWR_BASE + ((N) * OR1K_SPR_DEBUG_DCWR_STEP)) |
---|
| 2134 | #define OR1K_SPR_DEBUG_DCWR_ADDR(N) ((OR1K_SPR_DEBUG_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_DEBUG_DCWR_INDEX(N)) |
---|
| 2135 | |
---|
| 2136 | |
---|
| 2137 | /* Debug Stop Register */ |
---|
| 2138 | #define OR1K_SPR_DEBUG_DSR_INDEX OR1K_UNSIGNED(0x014) |
---|
| 2139 | #define OR1K_SPR_DEBUG_DSR_ADDR OR1K_UNSIGNED(0x3014) |
---|
| 2140 | |
---|
| 2141 | /* Reset Exception */ |
---|
| 2142 | #define OR1K_SPR_DEBUG_DSR_RSTE_OFFSET 0 |
---|
| 2143 | #define OR1K_SPR_DEBUG_DSR_RSTE_MASK 0x00000001 |
---|
| 2144 | #define OR1K_SPR_DEBUG_DSR_RSTE_GET(X) (((X) >> 0) & 0x1) |
---|
| 2145 | #define OR1K_SPR_DEBUG_DSR_RSTE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 2146 | |
---|
| 2147 | /* Bus Error Exception */ |
---|
| 2148 | #define OR1K_SPR_DEBUG_DSR_BUSEE_OFFSET 1 |
---|
| 2149 | #define OR1K_SPR_DEBUG_DSR_BUSEE_MASK 0x00000002 |
---|
| 2150 | #define OR1K_SPR_DEBUG_DSR_BUSEE_GET(X) (((X) >> 1) & 0x1) |
---|
| 2151 | #define OR1K_SPR_DEBUG_DSR_BUSEE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffd)) | ((!!(Y)) << 1)) |
---|
| 2152 | |
---|
| 2153 | /* Data Page Fault Exception */ |
---|
| 2154 | #define OR1K_SPR_DEBUG_DSR_DPFE_OFFSET 2 |
---|
| 2155 | #define OR1K_SPR_DEBUG_DSR_DPFE_MASK 0x00000004 |
---|
| 2156 | #define OR1K_SPR_DEBUG_DSR_DPFE_GET(X) (((X) >> 2) & 0x1) |
---|
| 2157 | #define OR1K_SPR_DEBUG_DSR_DPFE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffb)) | ((!!(Y)) << 2)) |
---|
| 2158 | |
---|
| 2159 | /* Instruction Page Fault Exception */ |
---|
| 2160 | #define OR1K_SPR_DEBUG_DSR_IPFE_OFFSET 3 |
---|
| 2161 | #define OR1K_SPR_DEBUG_DSR_IPFE_MASK 0x00000008 |
---|
| 2162 | #define OR1K_SPR_DEBUG_DSR_IPFE_GET(X) (((X) >> 3) & 0x1) |
---|
| 2163 | #define OR1K_SPR_DEBUG_DSR_IPFE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff7)) | ((!!(Y)) << 3)) |
---|
| 2164 | |
---|
| 2165 | /* Tick Timer Exception */ |
---|
| 2166 | #define OR1K_SPR_DEBUG_DSR_TTE_OFFSET 4 |
---|
| 2167 | #define OR1K_SPR_DEBUG_DSR_TTE_MASK 0x00000010 |
---|
| 2168 | #define OR1K_SPR_DEBUG_DSR_TTE_GET(X) (((X) >> 4) & 0x1) |
---|
| 2169 | #define OR1K_SPR_DEBUG_DSR_TTE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffef)) | ((!!(Y)) << 4)) |
---|
| 2170 | |
---|
| 2171 | /* Alignment Exception */ |
---|
| 2172 | #define OR1K_SPR_DEBUG_DSR_AE_OFFSET 5 |
---|
| 2173 | #define OR1K_SPR_DEBUG_DSR_AE_MASK 0x00000020 |
---|
| 2174 | #define OR1K_SPR_DEBUG_DSR_AE_GET(X) (((X) >> 5) & 0x1) |
---|
| 2175 | #define OR1K_SPR_DEBUG_DSR_AE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 2176 | |
---|
| 2177 | /* Illegal Instruction Exception */ |
---|
| 2178 | #define OR1K_SPR_DEBUG_DSR_IIE_OFFSET 6 |
---|
| 2179 | #define OR1K_SPR_DEBUG_DSR_IIE_MASK 0x00000040 |
---|
| 2180 | #define OR1K_SPR_DEBUG_DSR_IIE_GET(X) (((X) >> 6) & 0x1) |
---|
| 2181 | #define OR1K_SPR_DEBUG_DSR_IIE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6)) |
---|
| 2182 | |
---|
| 2183 | /* Interrupt Exception */ |
---|
| 2184 | #define OR1K_SPR_DEBUG_DSR_INTE_OFFSET 7 |
---|
| 2185 | #define OR1K_SPR_DEBUG_DSR_INTE_MASK 0x00000080 |
---|
| 2186 | #define OR1K_SPR_DEBUG_DSR_INTE_GET(X) (((X) >> 7) & 0x1) |
---|
| 2187 | #define OR1K_SPR_DEBUG_DSR_INTE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7)) |
---|
| 2188 | |
---|
| 2189 | /* DTLB Miss Exception */ |
---|
| 2190 | #define OR1K_SPR_DEBUG_DSR_DME_OFFSET 8 |
---|
| 2191 | #define OR1K_SPR_DEBUG_DSR_DME_MASK 0x00000100 |
---|
| 2192 | #define OR1K_SPR_DEBUG_DSR_DME_GET(X) (((X) >> 8) & 0x1) |
---|
| 2193 | #define OR1K_SPR_DEBUG_DSR_DME_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffeff)) | ((!!(Y)) << 8)) |
---|
| 2194 | |
---|
| 2195 | /* ITLB Miss Exception */ |
---|
| 2196 | #define OR1K_SPR_DEBUG_DSR_IME_OFFSET 9 |
---|
| 2197 | #define OR1K_SPR_DEBUG_DSR_IME_MASK 0x00000200 |
---|
| 2198 | #define OR1K_SPR_DEBUG_DSR_IME_GET(X) (((X) >> 9) & 0x1) |
---|
| 2199 | #define OR1K_SPR_DEBUG_DSR_IME_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffdff)) | ((!!(Y)) << 9)) |
---|
| 2200 | |
---|
| 2201 | /* Range Exception */ |
---|
| 2202 | #define OR1K_SPR_DEBUG_DSR_RE_OFFSET 10 |
---|
| 2203 | #define OR1K_SPR_DEBUG_DSR_RE_MASK 0x00000400 |
---|
| 2204 | #define OR1K_SPR_DEBUG_DSR_RE_GET(X) (((X) >> 10) & 0x1) |
---|
| 2205 | #define OR1K_SPR_DEBUG_DSR_RE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffbff)) | ((!!(Y)) << 10)) |
---|
| 2206 | |
---|
| 2207 | /* System Call Exception */ |
---|
| 2208 | #define OR1K_SPR_DEBUG_DSR_SCE_OFFSET 11 |
---|
| 2209 | #define OR1K_SPR_DEBUG_DSR_SCE_MASK 0x00000800 |
---|
| 2210 | #define OR1K_SPR_DEBUG_DSR_SCE_GET(X) (((X) >> 11) & 0x1) |
---|
| 2211 | #define OR1K_SPR_DEBUG_DSR_SCE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffff7ff)) | ((!!(Y)) << 11)) |
---|
| 2212 | |
---|
| 2213 | /* Floating Point Exception */ |
---|
| 2214 | #define OR1K_SPR_DEBUG_DSR_FPE_OFFSET 12 |
---|
| 2215 | #define OR1K_SPR_DEBUG_DSR_FPE_MASK 0x00001000 |
---|
| 2216 | #define OR1K_SPR_DEBUG_DSR_FPE_GET(X) (((X) >> 12) & 0x1) |
---|
| 2217 | #define OR1K_SPR_DEBUG_DSR_FPE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffefff)) | ((!!(Y)) << 12)) |
---|
| 2218 | |
---|
| 2219 | /* Trap Exception */ |
---|
| 2220 | #define OR1K_SPR_DEBUG_DSR_TE_OFFSET 13 |
---|
| 2221 | #define OR1K_SPR_DEBUG_DSR_TE_MASK 0x00002000 |
---|
| 2222 | #define OR1K_SPR_DEBUG_DSR_TE_GET(X) (((X) >> 13) & 0x1) |
---|
| 2223 | #define OR1K_SPR_DEBUG_DSR_TE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffdfff)) | ((!!(Y)) << 13)) |
---|
| 2224 | |
---|
| 2225 | |
---|
| 2226 | /* Debug Reason Register */ |
---|
| 2227 | #define OR1K_SPR_DEBUG_DRR_INDEX OR1K_UNSIGNED(0x015) |
---|
| 2228 | #define OR1K_SPR_DEBUG_DRR_ADDR OR1K_UNSIGNED(0x3015) |
---|
| 2229 | |
---|
| 2230 | /* Reset Exception */ |
---|
| 2231 | #define OR1K_SPR_DEBUG_DRR_RSTE_OFFSET 0 |
---|
| 2232 | #define OR1K_SPR_DEBUG_DRR_RSTE_MASK 0x00000001 |
---|
| 2233 | #define OR1K_SPR_DEBUG_DRR_RSTE_GET(X) (((X) >> 0) & 0x1) |
---|
| 2234 | #define OR1K_SPR_DEBUG_DRR_RSTE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffe)) | ((!!(Y)) << 0)) |
---|
| 2235 | |
---|
| 2236 | /* Bus Error Exception */ |
---|
| 2237 | #define OR1K_SPR_DEBUG_DRR_BUSEE_OFFSET 1 |
---|
| 2238 | #define OR1K_SPR_DEBUG_DRR_BUSEE_MASK 0x00000002 |
---|
| 2239 | #define OR1K_SPR_DEBUG_DRR_BUSEE_GET(X) (((X) >> 1) & 0x1) |
---|
| 2240 | #define OR1K_SPR_DEBUG_DRR_BUSEE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffd)) | ((!!(Y)) << 1)) |
---|
| 2241 | |
---|
| 2242 | /* Data Page Fault Exception */ |
---|
| 2243 | #define OR1K_SPR_DEBUG_DRR_DPFE_OFFSET 2 |
---|
| 2244 | #define OR1K_SPR_DEBUG_DRR_DPFE_MASK 0x00000004 |
---|
| 2245 | #define OR1K_SPR_DEBUG_DRR_DPFE_GET(X) (((X) >> 2) & 0x1) |
---|
| 2246 | #define OR1K_SPR_DEBUG_DRR_DPFE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffffb)) | ((!!(Y)) << 2)) |
---|
| 2247 | |
---|
| 2248 | /* Instruction Page Fault Exception */ |
---|
| 2249 | #define OR1K_SPR_DEBUG_DRR_IPFE_OFFSET 3 |
---|
| 2250 | #define OR1K_SPR_DEBUG_DRR_IPFE_MASK 0x00000008 |
---|
| 2251 | #define OR1K_SPR_DEBUG_DRR_IPFE_GET(X) (((X) >> 3) & 0x1) |
---|
| 2252 | #define OR1K_SPR_DEBUG_DRR_IPFE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffff7)) | ((!!(Y)) << 3)) |
---|
| 2253 | |
---|
| 2254 | /* Tick Timer Exception */ |
---|
| 2255 | #define OR1K_SPR_DEBUG_DRR_TTE_OFFSET 4 |
---|
| 2256 | #define OR1K_SPR_DEBUG_DRR_TTE_MASK 0x00000010 |
---|
| 2257 | #define OR1K_SPR_DEBUG_DRR_TTE_GET(X) (((X) >> 4) & 0x1) |
---|
| 2258 | #define OR1K_SPR_DEBUG_DRR_TTE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffef)) | ((!!(Y)) << 4)) |
---|
| 2259 | |
---|
| 2260 | /* Alignment Exception */ |
---|
| 2261 | #define OR1K_SPR_DEBUG_DRR_AE_OFFSET 5 |
---|
| 2262 | #define OR1K_SPR_DEBUG_DRR_AE_MASK 0x00000020 |
---|
| 2263 | #define OR1K_SPR_DEBUG_DRR_AE_GET(X) (((X) >> 5) & 0x1) |
---|
| 2264 | #define OR1K_SPR_DEBUG_DRR_AE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5)) |
---|
| 2265 | |
---|
| 2266 | /* Illegal Instruction Exception */ |
---|
| 2267 | #define OR1K_SPR_DEBUG_DRR_IIE_OFFSET 6 |
---|
| 2268 | #define OR1K_SPR_DEBUG_DRR_IIE_MASK 0x00000040 |
---|
| 2269 | #define OR1K_SPR_DEBUG_DRR_IIE_GET(X) (((X) >> 6) & 0x1) |
---|
| 2270 | #define OR1K_SPR_DEBUG_DRR_IIE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6)) |
---|
| 2271 | |
---|
| 2272 | /* Interrupt Exception */ |
---|
| 2273 | #define OR1K_SPR_DEBUG_DRR_INTE_OFFSET 7 |
---|
| 2274 | #define OR1K_SPR_DEBUG_DRR_INTE_MASK 0x00000080 |
---|
| 2275 | #define OR1K_SPR_DEBUG_DRR_INTE_GET(X) (((X) >> 7) & 0x1) |
---|
| 2276 | #define OR1K_SPR_DEBUG_DRR_INTE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7)) |
---|
| 2277 | |
---|
| 2278 | /* DTLB Miss Exception */ |
---|
| 2279 | #define OR1K_SPR_DEBUG_DRR_DME_OFFSET 8 |
---|
| 2280 | #define OR1K_SPR_DEBUG_DRR_DME_MASK 0x00000100 |
---|
| 2281 | #define OR1K_SPR_DEBUG_DRR_DME_GET(X) (((X) >> 8) & 0x1) |
---|
| 2282 | #define OR1K_SPR_DEBUG_DRR_DME_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffeff)) | ((!!(Y)) << 8)) |
---|
| 2283 | |
---|
| 2284 | /* ITLB Miss Exception */ |
---|
| 2285 | #define OR1K_SPR_DEBUG_DRR_IME_OFFSET 9 |
---|
| 2286 | #define OR1K_SPR_DEBUG_DRR_IME_MASK 0x00000200 |
---|
| 2287 | #define OR1K_SPR_DEBUG_DRR_IME_GET(X) (((X) >> 9) & 0x1) |
---|
| 2288 | #define OR1K_SPR_DEBUG_DRR_IME_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffdff)) | ((!!(Y)) << 9)) |
---|
| 2289 | |
---|
| 2290 | /* Range Exception */ |
---|
| 2291 | #define OR1K_SPR_DEBUG_DRR_RE_OFFSET 10 |
---|
| 2292 | #define OR1K_SPR_DEBUG_DRR_RE_MASK 0x00000400 |
---|
| 2293 | #define OR1K_SPR_DEBUG_DRR_RE_GET(X) (((X) >> 10) & 0x1) |
---|
| 2294 | #define OR1K_SPR_DEBUG_DRR_RE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffffbff)) | ((!!(Y)) << 10)) |
---|
| 2295 | |
---|
| 2296 | /* System Call Exception */ |
---|
| 2297 | #define OR1K_SPR_DEBUG_DRR_SCE_OFFSET 11 |
---|
| 2298 | #define OR1K_SPR_DEBUG_DRR_SCE_MASK 0x00000800 |
---|
| 2299 | #define OR1K_SPR_DEBUG_DRR_SCE_GET(X) (((X) >> 11) & 0x1) |
---|
| 2300 | #define OR1K_SPR_DEBUG_DRR_SCE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xfffff7ff)) | ((!!(Y)) << 11)) |
---|
| 2301 | |
---|
| 2302 | /* Floating Point Exception */ |
---|
| 2303 | #define OR1K_SPR_DEBUG_DRR_FPE_OFFSET 12 |
---|
| 2304 | #define OR1K_SPR_DEBUG_DRR_FPE_MASK 0x00001000 |
---|
| 2305 | #define OR1K_SPR_DEBUG_DRR_FPE_GET(X) (((X) >> 12) & 0x1) |
---|
| 2306 | #define OR1K_SPR_DEBUG_DRR_FPE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffefff)) | ((!!(Y)) << 12)) |
---|
| 2307 | |
---|
| 2308 | /* Trap Exception */ |
---|
| 2309 | #define OR1K_SPR_DEBUG_DRR_TE_OFFSET 13 |
---|
| 2310 | #define OR1K_SPR_DEBUG_DRR_TE_MASK 0x00002000 |
---|
| 2311 | #define OR1K_SPR_DEBUG_DRR_TE_GET(X) (((X) >> 13) & 0x1) |
---|
| 2312 | #define OR1K_SPR_DEBUG_DRR_TE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffdfff)) | ((!!(Y)) << 13)) |
---|
| 2313 | |
---|
| 2314 | |
---|
| 2315 | /******************************/ |
---|
| 2316 | /* Performance Counters Group */ |
---|
| 2317 | /******************************/ |
---|
| 2318 | #define OR1K_SPR_PERF_GROUP 0x07 |
---|
| 2319 | |
---|
| 2320 | /* Performance Counters Count Registers */ |
---|
| 2321 | #define OR1K_SPR_PERF_PCCR_BASE OR1K_UNSIGNED(0x000) |
---|
| 2322 | #define OR1K_SPR_PERF_PCCR_COUNT OR1K_UNSIGNED(0x008) |
---|
| 2323 | #define OR1K_SPR_PERF_PCCR_STEP OR1K_UNSIGNED(0x001) |
---|
| 2324 | #define OR1K_SPR_PERF_PCCR_INDEX(N) (OR1K_SPR_PERF_PCCR_BASE + ((N) * OR1K_SPR_PERF_PCCR_STEP)) |
---|
| 2325 | #define OR1K_SPR_PERF_PCCR_ADDR(N) ((OR1K_SPR_PERF_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_PERF_PCCR_INDEX(N)) |
---|
| 2326 | |
---|
| 2327 | |
---|
| 2328 | /* Performance Counters Mode Registers */ |
---|
| 2329 | #define OR1K_SPR_PERF_PCMR_BASE OR1K_UNSIGNED(0x008) |
---|
| 2330 | #define OR1K_SPR_PERF_PCMR_COUNT OR1K_UNSIGNED(0x008) |
---|
| 2331 | #define OR1K_SPR_PERF_PCMR_STEP OR1K_UNSIGNED(0x001) |
---|
| 2332 | #define OR1K_SPR_PERF_PCMR_INDEX(N) (OR1K_SPR_PERF_PCMR_BASE + ((N) * OR1K_SPR_PERF_PCMR_STEP)) |
---|
| 2333 | #define OR1K_SPR_PERF_PCMR_ADDR(N) ((OR1K_SPR_PERF_GROUP << OR1K_SPR_GROUP_LSB) | OR1K_SPR_PERF_PCMR_INDEX(N)) |
---|
| 2334 | |
---|
| 2335 | |
---|
| 2336 | /**************************/ |
---|
| 2337 | /* Power Management Group */ |
---|
| 2338 | /**************************/ |
---|
| 2339 | #define OR1K_SPR_POWER_GROUP 0x08 |
---|
| 2340 | |
---|
| 2341 | /* Power Management Register */ |
---|
| 2342 | #define OR1K_SPR_POWER_PMR_INDEX OR1K_UNSIGNED(0x000) |
---|
| 2343 | #define OR1K_SPR_POWER_PMR_ADDR OR1K_UNSIGNED(0x4000) |
---|
| 2344 | |
---|
| 2345 | |
---|
| 2346 | /*******************************************/ |
---|
| 2347 | /* Programmable Interrupt Controller Group */ |
---|
| 2348 | /*******************************************/ |
---|
| 2349 | #define OR1K_SPR_PIC_GROUP 0x09 |
---|
| 2350 | |
---|
| 2351 | /* PIC Mask Register */ |
---|
| 2352 | #define OR1K_SPR_PIC_PICMR_INDEX OR1K_UNSIGNED(0x000) |
---|
| 2353 | #define OR1K_SPR_PIC_PICMR_ADDR OR1K_UNSIGNED(0x4800) |
---|
| 2354 | |
---|
| 2355 | |
---|
| 2356 | /* PIC Status Register */ |
---|
| 2357 | #define OR1K_SPR_PIC_PICSR_INDEX OR1K_UNSIGNED(0x002) |
---|
| 2358 | #define OR1K_SPR_PIC_PICSR_ADDR OR1K_UNSIGNED(0x4802) |
---|
| 2359 | |
---|
| 2360 | |
---|
| 2361 | /********************/ |
---|
| 2362 | /* Tick Timer Group */ |
---|
| 2363 | /********************/ |
---|
| 2364 | #define OR1K_SPR_TICK_GROUP 0x0a |
---|
| 2365 | |
---|
| 2366 | /* Tick Timer Mode Register */ |
---|
| 2367 | #define OR1K_SPR_TICK_TTMR_INDEX OR1K_UNSIGNED(0x000) |
---|
| 2368 | #define OR1K_SPR_TICK_TTMR_ADDR OR1K_UNSIGNED(0x5000) |
---|
| 2369 | |
---|
| 2370 | /* Time Period */ |
---|
| 2371 | #define OR1K_SPR_TICK_TTMR_TP_LSB 0 |
---|
| 2372 | #define OR1K_SPR_TICK_TTMR_TP_MSB 27 |
---|
| 2373 | #define OR1K_SPR_TICK_TTMR_TP_BITS 28 |
---|
| 2374 | #define OR1K_SPR_TICK_TTMR_TP_MASK OR1K_UNSIGNED(0x0fffffff) |
---|
| 2375 | #define OR1K_SPR_TICK_TTMR_TP_GET(X) (((X) >> 0) & OR1K_UNSIGNED(0x0fffffff)) |
---|
| 2376 | #define OR1K_SPR_TICK_TTMR_TP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xf0000000)) | ((Y) << 0)) |
---|
| 2377 | |
---|
| 2378 | /* Interrupt Pending */ |
---|
| 2379 | #define OR1K_SPR_TICK_TTMR_IP_OFFSET 28 |
---|
| 2380 | #define OR1K_SPR_TICK_TTMR_IP_MASK 0x10000000 |
---|
| 2381 | #define OR1K_SPR_TICK_TTMR_IP_GET(X) (((X) >> 28) & 0x1) |
---|
| 2382 | #define OR1K_SPR_TICK_TTMR_IP_SET(X, Y) (((X) & OR1K_UNSIGNED(0xefffffff)) | ((!!(Y)) << 28)) |
---|
| 2383 | |
---|
| 2384 | /* Interrupt Enable */ |
---|
| 2385 | #define OR1K_SPR_TICK_TTMR_IE_OFFSET 29 |
---|
| 2386 | #define OR1K_SPR_TICK_TTMR_IE_MASK 0x20000000 |
---|
| 2387 | #define OR1K_SPR_TICK_TTMR_IE_GET(X) (((X) >> 29) & 0x1) |
---|
| 2388 | #define OR1K_SPR_TICK_TTMR_IE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xdfffffff)) | ((!!(Y)) << 29)) |
---|
| 2389 | |
---|
| 2390 | /* Mode */ |
---|
| 2391 | #define OR1K_SPR_TICK_TTMR_MODE_LSB 30 |
---|
| 2392 | #define OR1K_SPR_TICK_TTMR_MODE_MSB 31 |
---|
| 2393 | #define OR1K_SPR_TICK_TTMR_MODE_BITS 2 |
---|
| 2394 | #define OR1K_SPR_TICK_TTMR_MODE_MASK OR1K_UNSIGNED(0xc0000000) |
---|
| 2395 | #define OR1K_SPR_TICK_TTMR_MODE_GET(X) (((X) >> 30) & OR1K_UNSIGNED(0x00000003)) |
---|
| 2396 | #define OR1K_SPR_TICK_TTMR_MODE_SET(X, Y) (((X) & OR1K_UNSIGNED(0x3fffffff)) | ((Y) << 30)) |
---|
| 2397 | |
---|
| 2398 | /* Disabled */ |
---|
| 2399 | #define OR1K_SPR_TICK_TTMR_MODE_DISABLE 0 |
---|
| 2400 | /* Restart counting when TTMR[TP]==TTCR */ |
---|
| 2401 | #define OR1K_SPR_TICK_TTMR_MODE_RESTART 1 |
---|
| 2402 | /* Stop counting when TTMR[TP]==TTCR */ |
---|
| 2403 | #define OR1K_SPR_TICK_TTMR_MODE_STOP 2 |
---|
| 2404 | /* Continue counting when TTMR[TP]==TTCR */ |
---|
| 2405 | #define OR1K_SPR_TICK_TTMR_MODE_CONTINUE 3 |
---|
| 2406 | |
---|
| 2407 | /* Tick Timer Count Register */ |
---|
| 2408 | #define OR1K_SPR_TICK_TTCR_INDEX OR1K_UNSIGNED(0x001) |
---|
| 2409 | #define OR1K_SPR_TICK_TTCR_ADDR OR1K_UNSIGNED(0x5001) |
---|
| 2410 | |
---|
| 2411 | |
---|
| 2412 | /*****************************/ |
---|
| 2413 | /* Floating Point Unit Group */ |
---|
| 2414 | /*****************************/ |
---|
| 2415 | #define OR1K_SPR_FPU_GROUP 0x0b |
---|
| 2416 | |
---|
| 2417 | #endif |
---|