1 | /* Copyright (c) 2014 Authors |
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2 | * |
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3 | * Contributor Julius Baxter <julius.baxter@orsoc.se> |
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4 | * Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de> |
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5 | * |
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6 | * The authors hereby grant permission to use, copy, modify, distribute, |
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7 | * and license this software and its documentation for any purpose, provided |
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8 | * that existing copyright notices are retained in all copies and that this |
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9 | * notice is included verbatim in any distributions. No written agreement, |
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10 | * license, or royalty fee is required for any of the authorized uses. |
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11 | * Modifications to this software may be copyrighted by their authors |
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12 | * and need not follow the licensing terms described here, provided that |
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13 | * the new terms are clearly indicated on the first page of each file where |
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14 | * they apply. |
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15 | */ |
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16 | |
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17 | /* -------------------------------------------------------------------------- */ |
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18 | /* This program is commented throughout in a fashion suitable for processing |
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19 | with Doxygen. */ |
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20 | /* -------------------------------------------------------------------------- */ |
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21 | |
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22 | #include <stdint.h> |
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23 | |
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24 | #ifndef __OR1K_SUPPORT_H__ |
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25 | #define __OR1K_SUPPORT_H__ |
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26 | |
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27 | /*! |
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28 | * \defgroup or1k_macros OR1K macros |
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29 | * @{ |
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30 | */ |
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31 | |
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32 | /*! |
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33 | * Access byte-sized memory mapped register |
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34 | * |
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35 | * Used to access a byte-sized memory mapped register. It avoids usage errors |
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36 | * when not defining register addresses volatile and handles casting correctly. |
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37 | * |
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38 | * Example for both read and write: |
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39 | * |
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40 | * \code |
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41 | * uint8_t status = REG8(IPBLOCK_STATUS_REG_ADDR); |
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42 | * REG8(IPBLOCK_ENABLE) = 1; |
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43 | * \endcode |
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44 | * |
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45 | * \param add Register address |
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46 | */ |
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47 | #define REG8(add) *((volatile unsigned char *) (add)) |
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48 | |
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49 | /*! |
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50 | * Access halfword-sized memory mapped register |
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51 | * |
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52 | * Used to access a 16 byte-sized memory mapped register. It avoids usage errors |
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53 | * when not defining register addresses volatile and handles casting correctly. |
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54 | * |
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55 | * See REG8() for an example. |
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56 | * |
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57 | * \param add Register address |
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58 | */ |
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59 | #define REG16(add) *((volatile unsigned short *) (add)) |
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60 | |
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61 | /*! |
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62 | * Access word-sized memory mapped register |
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63 | * |
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64 | * Used to access a word-sized memory mapped register. It avoids usage errors |
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65 | * when not defining register addresses volatile and handles casting correctly. |
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66 | * |
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67 | * See REG8() for an example. |
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68 | * |
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69 | * \param add Register address |
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70 | */ |
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71 | #define REG32(add) *((volatile unsigned long *) (add)) |
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72 | /*! |
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73 | * @} |
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74 | */ |
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75 | |
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76 | /*! |
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77 | * \defgroup or1k_interrupts OR1K interrupt control |
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78 | * |
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79 | * Interrupt control function prototypes |
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80 | * |
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81 | * @{ |
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82 | */ |
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83 | |
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84 | /*! Function pointer to interrupt handler functions */ |
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85 | typedef void (*or1k_interrupt_handler_fptr)(void* data); |
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86 | |
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87 | /*! |
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88 | * Add interrupt handler for interrupt line |
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89 | * |
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90 | * Registers a callback function for a certain interrupt line. |
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91 | * |
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92 | * \param line Interrupt line/id to register a handler for |
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93 | * \param handler Handler to register |
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94 | * \param data Data value passed to the handler |
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95 | */ |
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96 | void or1k_interrupt_handler_add(uint32_t line, |
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97 | or1k_interrupt_handler_fptr handler, |
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98 | void* data); |
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99 | |
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100 | /*! |
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101 | * Enable interrupts from a given line |
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102 | * |
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103 | * Unmask the given interrupt line. It is also important to enable interrupts |
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104 | * in general, e.g., using or1k_interrupts_enable(). |
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105 | * |
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106 | * \param line Interrupt line to enable |
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107 | */ |
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108 | void or1k_interrupt_enable(int line); |
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109 | |
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110 | /*! |
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111 | * Disable interrupts from a given line |
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112 | * |
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113 | * Mask given interrupt line. It can be unmasked using or1k_interrupt_enable(). |
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114 | * |
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115 | * \param line Interrupt line to disable |
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116 | */ |
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117 | void or1k_interrupt_disable(int line); |
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118 | |
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119 | /*! |
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120 | * Disable interrupts |
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121 | * |
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122 | * This disables the interrupt exception. This is sufficient to disable all |
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123 | * interrupts. It does not change the mask register (which is modified using |
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124 | * or1k_interrupt_enable() and or1k_interrupt_disable()). |
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125 | * |
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126 | * The interrupt exception can be enabled using or1k_interrupts_enable(). |
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127 | * |
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128 | * Finally, the status of the interrupt exception enable flag is returned by |
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129 | * this function. That allows to call this function even if interrupts are |
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130 | * already disabled. To restore the value of the interrupt exception enable |
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131 | * flag, use the or1k_interrupts_restore() function. That way you avoid to |
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132 | * accidentally enable interrupts. Example: |
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133 | * |
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134 | * \code |
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135 | * void f() { |
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136 | * uint32_t interrupt_status = or1k_interrupts_disable(); |
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137 | * // do something |
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138 | * or1k_interrupts_restore(status); |
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139 | * } |
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140 | * \endcode |
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141 | * |
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142 | * This code will preserve the original status of the interrupt enable flag. |
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143 | * |
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144 | * \return Interrupt exception enable flag before call |
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145 | */ |
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146 | uint32_t or1k_interrupts_disable(void); |
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147 | |
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148 | /*! |
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149 | * Enable interrupt exception |
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150 | * |
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151 | * Enable the interrupt exception. Beside the interrupt exception, it is also |
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152 | * necessary to enable the individual interrupt lines using |
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153 | * or1k_interrupt_enable(). |
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154 | * |
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155 | * You should avoid using this function together with or1k_interrupts_disable() |
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156 | * to guard atomic blocks as it unconditionally enables the interrupt |
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157 | * exception (see documentation of or1k_interrupts_disable()). |
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158 | */ |
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159 | void or1k_interrupts_enable(void); |
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160 | |
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161 | /*! |
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162 | * Restore interrupt exception enable flag |
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163 | * |
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164 | * This function restores the given status to the processor. |
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165 | * or1k_interrupts_restore(0) is identical to or1k_interrupts_disable() and |
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166 | * or1k_interrupts_restore(SPR_SR_IEE) is identical to or1k_interrupts_enable(). |
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167 | * |
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168 | * It is for example used to guard an atomic block and restore the original |
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169 | * status of the interrupt exception enable flag as returned by |
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170 | * or1k_interrupts_disable(). See the documentation of or1k_interrupts_disable() |
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171 | * for a usage example. |
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172 | * |
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173 | * \param status Status of the flag to restore |
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174 | */ |
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175 | void or1k_interrupts_restore(uint32_t status); |
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176 | |
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177 | /*! |
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178 | * Disable timer and interrupt exception |
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179 | * |
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180 | * This function disables the timer and interrupt exception to guard critical |
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181 | * sections. It returns the status of the enable bits before the critical |
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182 | * section, that is restored with or1k_critical_end(). |
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183 | * |
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184 | * Example: |
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185 | * \code |
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186 | * ... |
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187 | * uint32_t status = or1k_critical_start(); |
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188 | * // critical part |
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189 | * or1k_critical_end(status); |
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190 | * ... |
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191 | * \endcode |
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192 | * |
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193 | * \return Status of timer and interrupt exception at time of call |
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194 | */ |
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195 | uint32_t or1k_critical_begin(); |
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196 | |
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197 | /*! |
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198 | * Enable timer and interrupt exception |
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199 | * |
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200 | * Restore the timer and interrupt exception enable. The restore value is the |
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201 | * return value from or1k_critical_start(). |
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202 | * |
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203 | * \param restore Interrupt and timer exception enable restore value |
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204 | */ |
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205 | void or1k_critical_end(uint32_t restore); |
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206 | /*! |
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207 | * @} |
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208 | */ |
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209 | |
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210 | /*! |
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211 | * \defgroup or1k_exception Exception handling |
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212 | * @{ |
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213 | */ |
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214 | /*! Function pointer to an exception handler function */ |
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215 | typedef void (*or1k_exception_handler_fptr)(void); |
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216 | |
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217 | /*! |
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218 | * Register exception handler |
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219 | * |
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220 | * Register an exception handler for the given exception id. This handler is |
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221 | * in the following then called when the exception occurs. You can thereby |
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222 | * individually handle those exceptions. |
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223 | * |
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224 | * \param id Exception id |
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225 | * \param handler Handler callback |
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226 | */ |
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227 | void or1k_exception_handler_add(int id, or1k_exception_handler_fptr handler); |
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228 | /*! |
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229 | * @} |
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230 | */ |
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231 | |
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232 | /*! |
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233 | * \defgroup or1k_spr SPR access |
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234 | * @{ |
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235 | */ |
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236 | |
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237 | /*! |
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238 | * Move value to special purpose register |
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239 | * |
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240 | * Move data value to a special purpose register |
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241 | * |
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242 | * \param spr SPR identifier, see spr-defs.h for macros |
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243 | * \param value value to move to SPR |
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244 | */ |
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245 | static inline void or1k_mtspr (uint32_t spr, uint32_t value) |
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246 | { |
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247 | __asm__ __volatile__ ("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value)); |
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248 | } |
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249 | |
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250 | /*! |
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251 | * Copy value from special purpose register |
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252 | * |
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253 | * Copy a data value from the given special purpose register. |
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254 | * |
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255 | * \param spr SPR identifier, see spr-defs.h for macros |
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256 | * \return SPR data value |
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257 | */ |
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258 | static inline uint32_t or1k_mfspr (uint32_t spr) { |
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259 | uint32_t value; |
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260 | __asm__ __volatile__ ("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr)); |
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261 | return value; |
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262 | } |
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263 | /*! |
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264 | * @} |
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265 | */ |
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266 | |
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267 | /*! |
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268 | * \defgroup or1k_util Miscellaneous utility functions |
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269 | * |
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270 | * @{ |
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271 | */ |
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272 | |
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273 | /*! |
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274 | * Report value to simulator |
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275 | * |
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276 | * Uses the built-in simulator functionality. |
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277 | * |
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278 | * \param value Value to report |
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279 | */ |
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280 | void or1k_report (unsigned long int value); |
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281 | |
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282 | /*! |
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283 | * Get (pseudo) random number |
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284 | * |
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285 | * This should return pseudo-random numbers, based on a Galois LFSR. |
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286 | * |
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287 | * \return (Pseudo) Random number |
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288 | */ |
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289 | unsigned long int or1k_rand(void); |
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290 | |
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291 | /*! |
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292 | * Register UART callback |
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293 | * |
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294 | * This function sets a callback function that is called when a character is |
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295 | * received via UART. The callback function has no return and a gets the |
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296 | * character as parameter. When a character is received, the function is called. |
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297 | * |
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298 | * Example (UART echo): |
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299 | * \code |
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300 | * void uart_in(char c) { |
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301 | * printf("%c", c); // Echo |
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302 | * } |
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303 | * |
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304 | * int main() { |
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305 | * or1k_uart_set_read_cb(&uart_in); |
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306 | * or1k_interrupts_enable(); |
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307 | * |
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308 | * while (1) {} |
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309 | * } |
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310 | * \endcode |
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311 | */ |
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312 | void or1k_uart_set_read_cb(void (*cb)(char c)); |
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313 | /*! |
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314 | * @} |
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315 | */ |
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316 | |
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317 | /*! |
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318 | * \defgroup or1k_cache Cache control |
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319 | * |
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320 | * @{ |
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321 | */ |
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322 | |
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323 | /*! |
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324 | * Enable instruction cache |
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325 | */ |
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326 | void or1k_icache_enable(void); |
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327 | |
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328 | /*! |
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329 | * Disable instruction cache |
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330 | */ |
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331 | void or1k_icache_disable(void); |
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332 | |
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333 | /*! |
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334 | * Flush instruction cache |
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335 | * |
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336 | * Invalidate instruction cache entry |
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337 | * |
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338 | * \param entry Entry to invalidate |
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339 | */ |
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340 | void or1k_icache_flush(uint32_t entry); |
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341 | |
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342 | /*! |
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343 | * Enable data cache |
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344 | */ |
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345 | void or1k_dcache_enable(void); |
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346 | |
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347 | /*! |
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348 | * Disable data cache |
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349 | */ |
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350 | void or1k_dcache_disable(void); |
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351 | |
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352 | /*! |
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353 | * Flush data cache |
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354 | * |
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355 | * Invalidate data cache entry |
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356 | * |
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357 | * \param entry Entry to invalidate |
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358 | */ |
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359 | void or1k_dcache_flush(unsigned long entry); |
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360 | /*! |
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361 | * @} |
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362 | */ |
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363 | |
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364 | /*! |
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365 | * \defgroup or1k_mmu MMU control |
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366 | * @{ |
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367 | */ |
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368 | |
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369 | /*! |
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370 | * Enable instruction MMU |
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371 | */ |
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372 | void or1k_immu_enable(void); |
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373 | |
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374 | /*! |
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375 | * Disable instruction MMU |
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376 | */ |
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377 | void or1k_immu_disable(void); |
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378 | |
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379 | /*! |
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380 | * Enable data MMU |
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381 | */ |
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382 | void or1k_dmmu_enable(void); |
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383 | |
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384 | /*! |
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385 | * Disable data MMU |
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386 | */ |
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387 | void or1k_dmmu_disable(void); |
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388 | /*! |
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389 | * @} |
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390 | */ |
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391 | |
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392 | /*! |
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393 | * \defgroup or1k_timer Timer control |
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394 | * |
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395 | * The tick timer can be used for time measurement, operating system scheduling |
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396 | * etc. By default it is initialized to continuously count the ticks of a |
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397 | * certain period after calling or1k_timer_init(). The period can later be |
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398 | * changed using or1k_timer_set_period(). |
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399 | * |
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400 | * The timer is controlled using or1k_timer_enable(), or1k_timer_disable(), |
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401 | * or1k_timer_restore(), or1k_timer_pause(). After initialization it is required |
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402 | * to enable the timer the first time using or1k_timer_enable(). |
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403 | * or1k_timer_disable() only disables the tick timer interrupts, it does not |
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404 | * disable the timer counting. If you plan to use a pair of or1k_timer_disable() |
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405 | * and or1k_timer_enable() to protect sections of your code against interrupts |
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406 | * you should use or1k_timer_disable() and or1k_timer_restore(), as it may be |
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407 | * possible that the timer interrupt was not enabled before disabling it, |
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408 | * enable would then start it unconditionally. or1k_timer_pause() pauses the |
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409 | * counting. |
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410 | * |
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411 | * In the default mode you can get the tick value using or1k_timer_get_ticks() |
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412 | * and reset this value using or1k_timer_reset_ticks(). |
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413 | * |
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414 | * Example for using the default mode: |
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415 | * |
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416 | * \code |
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417 | * int main() { |
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418 | * uint32_t ticks = 0; |
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419 | * uint32_t timerstate; |
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420 | * or1k_timer_init(100); |
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421 | * or1k_timer_enable(); |
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422 | * while (1) { |
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423 | * while (ticks == or1k_timer_get_ticks()) { } |
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424 | * timerstate = or1k_timer_disable(); |
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425 | * // do something atomar |
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426 | * or1k_timer_restore(timerstate); |
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427 | * if (ticks == 100) { |
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428 | * printf("A second elapsed\n"); |
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429 | * or1k_timer_reset_ticks(); |
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430 | * ticks = 0; |
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431 | * } |
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432 | * } |
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433 | * } |
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434 | * \endcode |
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435 | * |
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436 | * It is possible to change the mode of the tick timer using |
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437 | * or1k_timer_set_mode(). Allowed values are the correct bit pattern (including |
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438 | * the bit positions) for the TTMR register, it is recommended to use the macros |
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439 | * defined in spr-defs.h. For example, implementing an operating system with |
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440 | * scheduling decisions of varying duration favors the implementation of single |
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441 | * run tick timer. Here, each quantum is started before leaving the operating |
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442 | * system kernel. The counter can be restarted with or1k_timer_reset(). |
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443 | * Example: |
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444 | * |
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445 | * \code |
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446 | * void tick_handler(void) { |
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447 | * // Make schedule decision |
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448 | * // and set new thread |
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449 | * or1k_timer_reset(); |
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450 | * // End of exception, new thread will run |
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451 | * } |
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452 | * |
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453 | * int main() { |
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454 | * // Configure operating system and start threads.. |
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455 | * |
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456 | * // Configure timer |
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457 | * or1k_timer_init(50); |
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458 | * or1k_timer_set_handler(&tick_handler); |
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459 | * or1k_timer_set_mode(SPR_TTMR_SR); |
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460 | * or1k_timer_enable(); |
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461 | * |
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462 | * // Schedule first thread and die.. |
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463 | * } |
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464 | * \endcode |
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465 | * |
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466 | * @{ |
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467 | */ |
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468 | |
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469 | /*! |
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470 | * Initialize tick timer |
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471 | * |
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472 | * This initializes the tick timer in default mode (see \ref or1k_timer for |
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473 | * details). |
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474 | * |
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475 | * \param hz Initial period of the tick timer |
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476 | * \return 0 if successful, -1 if timer not present |
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477 | */ |
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478 | int or1k_timer_init(unsigned int hz); |
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479 | |
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480 | /*! |
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481 | * Set period of timer |
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482 | * |
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483 | * Set the period of the timer to a value in Hz. The frequency from the board |
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484 | * support package is used to determine the match value. |
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485 | */ |
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486 | void or1k_timer_set_period(uint32_t hz); |
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487 | |
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488 | /*! |
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489 | * Replace the timer interrupt handler |
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490 | * |
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491 | * By default the tick timer is used to handle timer ticks. The user can replace |
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492 | * this with an own handler for example when implementing an operating system. |
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493 | * |
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494 | * \param handler The callback function pointer to the handler |
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495 | */ |
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496 | void or1k_timer_set_handler(void (*handler)(void)); |
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497 | |
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498 | /*! |
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499 | * Set timer mode |
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500 | * |
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501 | * The timer has different modes (see architecture manual). The default is to |
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502 | * automatically restart counting (SPR_TTMR_RT), others are single run |
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503 | * (SPR_TTMR_SR) and continuous run (SPR_TTMR_CR). |
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504 | * |
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505 | * \param mode a valid mode (use definitions from spr-defs.h as it is important |
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506 | * that those are also at the correct position in the bit field!) |
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507 | */ |
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508 | void or1k_timer_set_mode(uint32_t mode); |
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509 | |
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510 | /*! |
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511 | * Enable timer interrupt |
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512 | * |
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513 | * Enable the timer interrupt exception, independent of the status before. |
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514 | * If you want to enable the timer conditionally, for example to implement a |
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515 | * non-interruptible sequence of code, you should use or1k_timer_restore(). See |
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516 | * the description of or1k_timer_disable() for more details. |
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517 | * |
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518 | * The enable will also restore the mode if the timer was paused previously. |
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519 | */ |
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520 | void or1k_timer_enable(void); |
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521 | |
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522 | /*! |
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523 | * Disable timer interrupt |
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524 | * |
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525 | * This disables the timer interrupt exception and returns the state of the |
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526 | * interrupt exception enable flag before the call. This can be used with |
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527 | * or1k_timer_restore() to implement sequences of code that are not allowed to |
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528 | * be interrupted. Using or1k_timer_enable() will unconditionally enable the |
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529 | * interrupt independent of the state before calling or1k_timer_disable(). |
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530 | * For an example see \ref or1k_timer. |
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531 | * |
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532 | * \return Status of timer interrupt before call |
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533 | */ |
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534 | uint32_t or1k_timer_disable(void); |
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535 | |
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536 | /*! |
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537 | * Restore timer interrupt exception flag |
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538 | * |
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539 | * Restores the timer interrupt exception flag as returned by |
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540 | * or1k_timer_disable(). See the description of or1k_timer_disable() and \ref |
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541 | * or1k_timer for details and an example. |
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542 | * |
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543 | * \param sr_tee Status of timer interrupt |
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544 | */ |
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545 | void or1k_timer_restore(uint32_t sr_tee); |
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546 | |
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547 | /*! |
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548 | * Pause timer counter |
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549 | * |
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550 | * Pauses the counter of the tick timer. The counter will hold its current value |
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551 | * and it can be started again with or1k_timer_enable() which will restore the |
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552 | * configured mode. |
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553 | */ |
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554 | void or1k_timer_pause(void); |
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555 | |
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556 | /*! |
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557 | * Reset timer counter |
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558 | */ |
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559 | void or1k_timer_reset(void); |
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560 | |
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561 | /*! |
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562 | * Get timer ticks |
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563 | * |
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564 | * Get the global ticks of the default configuration. This will increment the |
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565 | * tick counter according to the preconfigured period. |
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566 | * |
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567 | * \return Current value of ticks |
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568 | */ |
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569 | unsigned long or1k_timer_get_ticks(void); |
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570 | |
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571 | /*! |
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572 | * Reset timer ticks |
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573 | * |
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574 | * Resets the timer ticks in default configuration to 0. |
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575 | */ |
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576 | void or1k_timer_reset_ticks(void); |
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577 | /*! |
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578 | * @} |
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579 | */ |
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580 | |
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581 | /*! |
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582 | * \defgroup or1k_multicore Multicore and Synchronization Support |
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583 | * |
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584 | * @{ |
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585 | */ |
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586 | |
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587 | /*! |
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588 | * Compiled with multicore support |
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589 | * |
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590 | * \return 1 if compiled with multicore support, 0 otherwise |
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591 | */ |
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592 | uint32_t or1k_has_multicore_support(void); |
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593 | |
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594 | /*! |
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595 | * Read core identifier |
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596 | * |
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597 | * \return Core identifier |
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598 | */ |
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599 | uint32_t or1k_coreid(void); |
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600 | |
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601 | /*! |
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602 | * Read number of cores |
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603 | * |
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604 | * \return Total number of cores |
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605 | */ |
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606 | uint32_t or1k_numcores(void); |
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607 | |
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608 | /*! |
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609 | * Load linked |
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610 | * |
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611 | * Load a value from the given address and link it. If the following |
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612 | * or1k_sync_sc() goes to the same address and there was no conflicting access |
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613 | * between loading and storing, the value is written back, else the write fails. |
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614 | * |
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615 | * \param address Address to load value from |
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616 | * \return Value read from the address |
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617 | */ |
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618 | uint32_t or1k_sync_ll(void *address); |
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619 | |
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620 | /** |
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621 | * Store conditional |
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622 | * |
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623 | * Conditionally store a value to the address. The address must have been read |
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624 | * before using or1k_sync_ll() and there must be no other load link after that, |
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625 | * otherwise this will always fail. In case there was no other write to the same |
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626 | * address in between the load link and the store conditional, the store is |
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627 | * successful, otherwise it will also fail. |
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628 | * |
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629 | * \param address Address to conditionally store to |
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630 | * \param value Value to write to address |
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631 | * \return 1 if success, 0 if fail |
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632 | */ |
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633 | int or1k_sync_sc(void *address, uint32_t value); |
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634 | |
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635 | /*! |
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636 | * Compare and Swap |
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637 | * |
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638 | * Loads a data item from the memory and compares a given value to it. If the |
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639 | * values match, a new value is written to the memory, if they mismatch, the |
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640 | * operation is aborted. The whole operation is atomic, i.e., it is guaranteed |
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641 | * that no other core changes the value between the read and the write. |
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642 | * |
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643 | * \param address Address to operate on |
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644 | * \param compare Compare value |
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645 | * \param swap New value to write |
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646 | * \return The value read from memory (can be used to check for success) |
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647 | */ |
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648 | uint32_t or1k_sync_cas(void *address, uint32_t compare, uint32_t swap); |
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649 | |
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650 | /*! |
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651 | * Test and Set Lock |
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652 | * |
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653 | * Check for a lock on an address. This means, if there is 0 at an address it |
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654 | * will overwrite it with 1 and return 0. If the lock was already set (value |
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655 | * 1 read from address), the function returns 1. The operation is atomic. |
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656 | * |
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657 | * \param address Address of the lock |
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658 | * \return 0 if success, 1 if failed |
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659 | */ |
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660 | int or1k_sync_tsl(void *address); |
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661 | /*! |
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662 | * @} |
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663 | */ |
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664 | |
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665 | #endif /* __NEWLIB_OR1K_SUPPORT_H__ */ |
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