| 1 | /* mmu-asm.S -- MMU handling for OpenRISC 1000. |
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| 2 | * |
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| 3 | * Copyright (c) 2011, 2014 Authors |
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| 4 | * |
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| 5 | * Contributor Julius Baxter <juliusbaxter@gmail.com> |
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| 6 | * Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de> |
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| 7 | * |
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| 8 | * The authors hereby grant permission to use, copy, modify, distribute, |
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| 9 | * and license this software and its documentation for any purpose, provided |
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| 10 | * that existing copyright notices are retained in all copies and that this |
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| 11 | * notice is included verbatim in any distributions. No written agreement, |
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| 12 | * license, or royalty fee is required for any of the authorized uses. |
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| 13 | * Modifications to this software may be copyrighted by their authors |
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| 14 | * and need not follow the licensing terms described here, provided that |
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| 15 | * the new terms are clearly indicated on the first page of each file where |
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| 16 | * they apply. |
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| 17 | */ |
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| 18 | |
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| 19 | /* -------------------------------------------------------------------------- */ |
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| 20 | /*!Function to control MMU |
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| 21 | */ |
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| 22 | /* -------------------------------------------------------------------------- */ |
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| 23 | |
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| 24 | #include "include/or1k-asm.h" |
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| 25 | #include "include/or1k-sprs.h" |
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| 26 | |
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| 27 | /* MMU control functions always switch MMU control with a l.rfe to return |
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| 28 | from function */ |
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| 29 | .section .text |
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| 30 | |
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| 31 | .global or1k_dmmu_enable |
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| 32 | or1k_dmmu_enable: |
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| 33 | l.mfspr r3,r0,OR1K_SPR_SYS_SR_ADDR |
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| 34 | l.ori r3,r3,OR1K_SPR_SYS_SR_DME_MASK |
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| 35 | l.mtspr r0,r3,OR1K_SPR_SYS_ESR_BASE |
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| 36 | l.mtspr r0,r9,OR1K_SPR_SYS_EPCR_BASE |
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| 37 | OR1K_DELAYED_NOP(OR1K_INST(l.rfe)) |
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| 38 | |
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| 39 | |
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| 40 | .global or1k_dmmu_disable |
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| 41 | or1k_dmmu_disable: |
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| 42 | l.ori r3,r0,OR1K_SPR_SYS_SR_DME_MASK |
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| 43 | l.xori r4,r3,0xffff |
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| 44 | l.mfspr r3,r0,OR1K_SPR_SYS_SR_ADDR |
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| 45 | l.and r3,r4,r3 |
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| 46 | l.mtspr r0,r3,OR1K_SPR_SYS_ESR_BASE |
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| 47 | l.mtspr r0,r9,OR1K_SPR_SYS_EPCR_BASE |
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| 48 | OR1K_DELAYED_NOP(OR1K_INST(l.rfe)) |
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| 49 | |
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| 50 | |
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| 51 | .global or1k_immu_enable |
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| 52 | or1k_immu_enable: |
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| 53 | l.mfspr r3,r0,OR1K_SPR_SYS_SR_ADDR |
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| 54 | l.ori r3,r3,OR1K_SPR_SYS_SR_IME_MASK |
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| 55 | l.mtspr r0,r3,OR1K_SPR_SYS_ESR_BASE |
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| 56 | l.mtspr r0,r9,OR1K_SPR_SYS_EPCR_BASE |
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| 57 | OR1K_DELAYED_NOP(OR1K_INST(l.rfe)) |
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| 58 | |
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| 59 | .global or1k_immu_disable |
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| 60 | or1k_immu_disable: |
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| 61 | l.ori r3,r0,OR1K_SPR_SYS_SR_IME_MASK |
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| 62 | l.xori r4,r3,0xffff |
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| 63 | l.mfspr r3,r0,OR1K_SPR_SYS_SR_ADDR |
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| 64 | l.and r3,r4,r3 |
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| 65 | l.mtspr r0,r3,OR1K_SPR_SYS_ESR_BASE |
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| 66 | l.mtspr r0,r9,OR1K_SPR_SYS_EPCR_BASE |
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| 67 | OR1K_DELAYED_NOP(OR1K_INST(l.rfe)) |
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