1 | /* or1k_uart.c -- UART implementation for OpenRISC 1000. |
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2 | * |
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3 | *Copyright (c) 2014 Authors |
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4 | * |
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5 | * Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de> |
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6 | * Contributor Olof Kindgren <olof.kindgren@gmail.com> |
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7 | * |
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8 | * The authors hereby grant permission to use, copy, modify, distribute, |
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9 | * and license this software and its documentation for any purpose, provided |
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10 | * that existing copyright notices are retained in all copies and that this |
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11 | * notice is included verbatim in any distributions. No written agreement, |
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12 | * license, or royalty fee is required for any of the authorized uses. |
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13 | * Modifications to this software may be copyrighted by their authors |
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14 | * and need not follow the licensing terms described here, provided that |
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15 | * the new terms are clearly indicated on the first page of each file where |
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16 | * they apply. |
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17 | */ |
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18 | |
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19 | #include "include/or1k-support.h" |
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20 | #include "or1k_uart.h" |
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21 | |
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22 | #include <stdint.h> |
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23 | |
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24 | // Register interface |
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25 | #define RB _or1k_board_uart_base + 0 // Receiver Buffer (R) |
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26 | #define THR _or1k_board_uart_base + 0 // Transmitter Holding Register (W) |
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27 | #define IER _or1k_board_uart_base + 1 // Interrupt Enable Register (RW) |
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28 | #define IIR _or1k_board_uart_base + 2 // Interrupt Identification Register (R) |
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29 | #define FCR _or1k_board_uart_base + 2 // FIFO Control Register (W) |
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30 | #define LCR _or1k_board_uart_base + 3 // Line Control Register (RW) |
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31 | #define MCR _or1k_board_uart_base + 4 // Modem Control Register (W) |
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32 | #define LSR _or1k_board_uart_base + 5 // Line Status Register (R) |
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33 | #define MSR _or1k_board_uart_base + 6 // Modem Status Register (R) |
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34 | |
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35 | // Divisor Register (Accessed when DLAB bit in LCR is set) |
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36 | #define DLB1 _or1k_board_uart_base + 0 // Divisor Latch LSB (RW) |
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37 | #define DLB2 _or1k_board_uart_base + 1 // Divisor Latch MSB (RW) |
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38 | |
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39 | // Interrupt Enable Register bits |
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40 | #define IER_RDAI 0 // Receiver Data Available Interrupt |
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41 | #define IER_TEI 1 // Transmitter Holding Register Empty Interrupt |
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42 | #define IER_RLSI 2 // Receiver Line Status Interrupt |
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43 | #define IER_MSI 3 // Modem Status Interrupt |
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44 | |
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45 | // Interrupt Identification Register Values |
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46 | #define IIR_RLS 0xC6 // Receiver Line Status |
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47 | #define IIR_RDA 0xC4 // Receiver Data Available |
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48 | #define IIR_TO 0xCC // Timeout |
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49 | #define IIR_THRE 0xC2 // Transmitter Holding Register Empty |
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50 | #define IIT_MS 0xC0 // Modem Status |
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51 | |
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52 | // FIFO Control Register bits |
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53 | #define FCR_CLRRECV 0x1 // Clear receiver FIFO |
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54 | #define FCR_CLRTMIT 0x2 // Clear transmitter FIFO |
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55 | |
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56 | // FIFO Control Register bit 7-6 values |
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57 | #define FCR_TRIG_1 0x0 // Trigger level 1 byte |
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58 | #define FCR_TRIG_4 0x40 // Trigger level 4 bytes |
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59 | #define FCR_TRIG_8 0x80 // Trigger level 8 bytes |
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60 | #define FCR_TRIG_14 0xC0 // Trigger level 14 bytes |
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61 | |
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62 | // Line Control Reigster values and bits |
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63 | #define LCR_BPC_5 0x0 // 5 bits per character |
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64 | #define LCR_BPC_6 0x1 // 6 bits per character |
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65 | #define LCR_BPC_7 0x2 // 7 bits per character |
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66 | #define LCR_BPC_8 0x3 // 8 bits per character |
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67 | #define LCR_SB_1 0x0 // 1 stop bit |
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68 | #define LCR_SB_2 0x4 // 1.5 stop bits (LCR_BPC_5) or 2 stop bits (else) |
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69 | #define LCR_PE 0x8 // Parity Enabled |
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70 | #define LCR_EPS 0x10 // Even Parity Select |
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71 | #define LCR_SP 0x20 // Stick Parity |
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72 | #define LCR_BC 0x40 // Break Control |
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73 | #define LCR_DLA 0x80 // Divisor Latch Access |
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74 | |
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75 | // Line Status Register |
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76 | #define LSR_DR 0x0 // Data Ready |
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77 | #define LSR_OE 0x2 // Overrun Error |
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78 | #define LSR_PE 0x4 // Parity Error |
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79 | #define LSR_FE 0x8 // Framing Error |
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80 | #define LSR_BI 0x10 // Break Interrupt |
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81 | #define LSR_TFE 0x20 // Transmitter FIFO Empty |
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82 | #define LSR_TEI 0x40 // Transmitter Empty Indicator |
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83 | |
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84 | /** |
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85 | * The registered callback function |
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86 | */ |
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87 | void (*_or1k_uart_read_cb)(char c); |
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88 | |
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89 | /** |
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90 | * This is the interrupt handler that is registered for the callback |
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91 | * function. |
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92 | */ |
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93 | void _or1k_uart_interrupt_handler(uint32_t data) |
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94 | { |
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95 | uint8_t iir = REG8(IIR); |
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96 | |
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97 | // Check if this is a read fifo or timeout interrupt, bit 0 |
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98 | // indicates pending interrupt and the other bits are IIR_RDA |
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99 | // or IIR_TO |
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100 | if (!(iir & 0x1) || ((iir & 0xfe) != IIR_RDA) || |
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101 | ((iir & 0xfe) != IIR_TO)) { |
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102 | return; |
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103 | } |
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104 | |
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105 | // Read character and call callback function |
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106 | _or1k_uart_read_cb(REG8(RB)); |
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107 | } |
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108 | |
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109 | int _or1k_uart_init(void) |
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110 | { |
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111 | uint16_t divisor; |
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112 | |
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113 | // Is uart present? |
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114 | if (!_or1k_board_uart_base) { |
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115 | return -1; |
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116 | } |
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117 | |
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118 | // Reset the callback function |
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119 | _or1k_uart_read_cb = 0; |
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120 | |
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121 | // Calculate and set divisor |
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122 | divisor = _or1k_board_clk_freq / (_or1k_board_uart_baud * 16); |
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123 | REG8(LCR) = LCR_DLA; |
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124 | REG8(DLB1) = divisor & 0xff; |
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125 | REG8(DLB2) = divisor >> 8; |
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126 | |
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127 | // Set line control register: |
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128 | // - 8 bits per character |
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129 | // - 1 stop bit |
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130 | // - No parity |
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131 | // - Break disabled |
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132 | // - Disallow access to divisor latch |
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133 | REG8(LCR) = LCR_BPC_8; |
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134 | |
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135 | // Reset FIFOs and set trigger level to 14 bytes |
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136 | REG8(FCR) = FCR_CLRRECV | FCR_CLRTMIT | FCR_TRIG_14; |
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137 | |
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138 | // Disable all interrupts |
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139 | REG8(IER) = 0; |
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140 | |
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141 | return 0; |
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142 | } |
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143 | |
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144 | void _or1k_uart_write(char c) |
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145 | { |
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146 | // Wait until FIFO is empty |
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147 | while (!(REG8(LSR) & LSR_TFE)) {} |
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148 | |
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149 | // Write character to device |
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150 | REG8(THR) = c; |
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151 | } |
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152 | |
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153 | void or1k_uart_set_read_cb(void (*cb)(char c)) |
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154 | { |
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155 | // Set callback function |
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156 | _or1k_uart_read_cb = cb; |
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157 | |
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158 | // Enable interrupt |
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159 | REG8(IER) = 1 << IER_RDAI; |
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160 | |
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161 | // Add the interrupt handler that calls the callback function |
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162 | or1k_interrupt_handler_add(_or1k_board_uart_IRQ, |
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163 | _or1k_uart_interrupt_handler, 0); |
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164 | |
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165 | // Enable UART interrupt |
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166 | or1k_interrupt_enable(_or1k_board_uart_IRQ); |
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167 | } |
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