[444] | 1 | #include "include/or1k-asm.h" |
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| 2 | #include "include/or1k-sprs.h" |
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| 3 | |
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| 4 | .section .text |
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| 5 | |
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| 6 | |
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| 7 | .global or1k_has_multicore_support |
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| 8 | .type or1k_has_multicore_support,@function |
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| 9 | or1k_has_multicore_support: |
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| 10 | #ifdef __OR1K_MULTICORE__ |
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| 11 | // Return 1 |
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| 12 | OR1K_DELAYED( |
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| 13 | OR1K_INST(l.ori r11,r0,1), |
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| 14 | OR1K_INST(l.jr r9) |
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| 15 | ) |
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| 16 | #else |
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| 17 | // Return 0 |
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| 18 | OR1K_DELAYED( |
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| 19 | OR1K_INST(l.or r11,r0,r0), |
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| 20 | OR1K_INST(l.jr r9) |
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| 21 | ) |
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| 22 | #endif |
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| 23 | |
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| 24 | .global or1k_coreid |
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| 25 | .type or1k_coreid,@function |
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| 26 | or1k_coreid: |
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| 27 | #ifdef __OR1K_MULTICORE__ |
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| 28 | // Return SPR with core identifier |
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| 29 | OR1K_DELAYED( |
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| 30 | OR1K_INST(l.mfspr r11,r0,OR1K_SPR_SYS_COREID_ADDR), |
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| 31 | OR1K_INST(l.jr r9) |
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| 32 | ) |
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| 33 | #else |
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| 34 | // Return 0 |
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| 35 | OR1K_DELAYED( |
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| 36 | OR1K_INST(l.or r11,r0,r0), |
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| 37 | OR1K_INST(l.jr r9) |
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| 38 | ) |
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| 39 | #endif |
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| 40 | |
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| 41 | .global or1k_numcores |
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| 42 | .type or1k_numcores,@function |
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| 43 | or1k_numcores: |
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| 44 | #ifdef __OR1K_MULTICORE__ |
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| 45 | // Return SPR with number of cores |
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| 46 | OR1K_DELAYED( |
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| 47 | OR1K_INST(l.mfspr r11,r0,OR1K_SPR_SYS_NUMCORES_ADDR), |
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| 48 | OR1K_INST(l.jr r9) |
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| 49 | ) |
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| 50 | #else |
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| 51 | // Return 1 |
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| 52 | OR1K_DELAYED( |
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| 53 | OR1K_INST(l.ori r11,r0,1), |
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| 54 | OR1K_INST(l.jr r9) |
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| 55 | ) |
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| 56 | #endif |
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| 57 | |
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| 58 | .global or1k_sync_ll |
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| 59 | .type or1k_sync_ll,@function |
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| 60 | or1k_sync_ll: |
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| 61 | #ifdef __OR1K_MULTICORE__ |
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| 62 | // Load word atomic |
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| 63 | OR1K_DELAYED( |
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| 64 | OR1K_INST(l.lwa r11, 0(r3)), |
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| 65 | OR1K_INST(l.jr r9) |
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| 66 | ) |
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| 67 | #else |
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| 68 | // Simply load word, TODO: throw exception? which? |
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| 69 | OR1K_DELAYED( |
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| 70 | OR1K_INST(l.lwz r11, 0(r3)), |
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| 71 | OR1K_INST(l.jr r9) |
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| 72 | ) |
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| 73 | #endif |
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| 74 | |
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| 75 | .global or1k_sync_sc |
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| 76 | .type or1k_sync_sc,@function |
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| 77 | or1k_sync_sc: |
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| 78 | #ifdef __OR1K_MULTICORE__ |
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| 79 | // swa sets the flag if it was succesfull |
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| 80 | // Store the value to address and set flag |
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| 81 | l.swa 0(r3),r4 |
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| 82 | OR1K_DELAYED( |
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| 83 | // Set return to success speculatively (may go to delay slot) |
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| 84 | OR1K_INST(l.ori r11,r0,1), |
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| 85 | // If the swa was successfull, jump to end |
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| 86 | OR1K_INST(l.bf .or1k_sync_sc_done) |
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| 87 | ) |
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| 88 | // If the swa was not successfull, set |
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| 89 | l.or r11,r0,r0 |
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| 90 | .or1k_sync_sc_done: |
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| 91 | OR1K_DELAYED_NOP(OR1K_INST(l.jr r9)) |
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| 92 | #else |
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| 93 | // Simply store word, TODO: throw exception? which? |
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| 94 | OR1K_DELAYED( |
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| 95 | OR1K_INST(l.sw 0(r3),r4), |
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| 96 | OR1K_INST(l.jr r9) |
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| 97 | ) |
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| 98 | #endif |
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| 99 | |
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| 100 | |
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| 101 | .global or1k_sync_cas |
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| 102 | .type or1k_sync_sc,@function |
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| 103 | or1k_sync_cas: |
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| 104 | #ifdef __OR1K_MULTICORE__ |
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| 105 | /* Load linked address value to return register */ |
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| 106 | l.lwa r11,0(r3) |
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| 107 | /* Compare value to parameter */ |
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| 108 | l.sfeq r11,r4 |
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| 109 | /* If not equal: abort and return the read value */ |
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| 110 | OR1K_DELAYED_NOP(OR1K_INST(l.bnf .or1k_sync_cas_done)) |
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| 111 | /* If compare was successfull: try writing */ |
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| 112 | l.swa 0(r3),r5 |
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| 113 | /* If writing was not successful: restart */ |
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| 114 | OR1K_DELAYED_NOP(OR1K_INST(l.bnf or1k_sync_cas)) |
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| 115 | .or1k_sync_cas_done: |
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| 116 | /* Return value is the original read value */ |
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| 117 | OR1K_DELAYED_NOP(OR1K_INST(l.jr r9)) |
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| 118 | #else |
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| 119 | // Non-atomic CAS, TODO: throw exception? which? |
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| 120 | l.lwz r11,0(r3) |
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| 121 | l.sfeq r11,r4 |
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| 122 | OR1K_DELAYED_NOP(OR1K_INST(l.bnf .or1k_sync_cas_done)) |
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| 123 | l.sw 0(r3),r5 |
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| 124 | .or1k_sync_cas_done: |
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| 125 | OR1K_DELAYED_NOP(OR1K_INST(l.jr r9)) |
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| 126 | #endif |
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| 127 | |
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| 128 | .global or1k_sync_tsl |
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| 129 | .type or1k_sync_tsl,@function |
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| 130 | or1k_sync_tsl: |
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| 131 | l.or r4,r0,r0 |
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| 132 | OR1K_DELAYED( |
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| 133 | OR1K_INST(l.addi r5,r0,1), |
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| 134 | OR1K_INST(l.j or1k_sync_cas) |
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| 135 | ) |
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