[444] | 1 | /* timer.c -- tick timer functions for OpenRISC 1000. |
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| 2 | * |
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| 3 | * Copyright (c) 2011, 2014 Authors |
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| 4 | * |
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| 5 | * Contributor Julius Baxter <juliusbaxter@gmail.com> |
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| 6 | * Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de> |
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| 7 | * |
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| 8 | * The authors hereby grant permission to use, copy, modify, distribute, |
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| 9 | * and license this software and its documentation for any purpose, provided |
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| 10 | * that existing copyright notices are retained in all copies and that this |
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| 11 | * notice is included verbatim in any distributions. No written agreement, |
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| 12 | * license, or royalty fee is required for any of the authorized uses. |
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| 13 | * Modifications to this software may be copyrighted by their authors |
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| 14 | * and need not follow the licensing terms described here, provided that |
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| 15 | * the new terms are clearly indicated on the first page of each file where |
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| 16 | * they apply. |
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| 17 | */ |
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| 18 | |
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| 19 | #include "include/or1k-support.h" |
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| 20 | #include "include/or1k-sprs.h" |
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| 21 | |
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| 22 | #include "or1k-internals.h" |
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| 23 | #include "board.h" |
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| 24 | |
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| 25 | /* --------------------------------------------------------------------------*/ |
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| 26 | /*!Tick timer interrupt handler |
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| 27 | |
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| 28 | Increment timer ticks counter, reload TTMR |
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| 29 | */ |
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| 30 | /* --------------------------------------------------------------------------*/ |
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| 31 | void |
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| 32 | _or1k_timer_interrupt_handler(void) |
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| 33 | { |
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| 34 | OR1K_REENT.or1k_timer_ticks++; |
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| 35 | uint32_t ttmr = or1k_mfspr(OR1K_SPR_TICK_TTMR_ADDR); |
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| 36 | ttmr = OR1K_SPR_TICK_TTMR_IE_SET(ttmr, 1); |
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| 37 | ttmr = OR1K_SPR_TICK_TTMR_MODE_SET(ttmr, OR1K_SPR_TICK_TTMR_MODE_RESTART); |
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| 38 | ttmr = OR1K_SPR_TICK_TTMR_IP_SET(ttmr, 0); |
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| 39 | or1k_mtspr(OR1K_SPR_TICK_TTMR_ADDR, ttmr); |
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| 40 | } |
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| 41 | |
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| 42 | /* --------------------------------------------------------------------------*/ |
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| 43 | /*!Enable tick timer |
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| 44 | |
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| 45 | Install handler, calculate TTMR period, reset tick counter |
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| 46 | |
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| 47 | @param[in] hz Rate at which to trigger timer ticks */ |
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| 48 | /* --------------------------------------------------------------------------*/ |
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| 49 | int |
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| 50 | or1k_timer_init(unsigned int hz) |
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| 51 | { |
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| 52 | uint32_t upr = or1k_mfspr(OR1K_SPR_SYS_UPR_ADDR); |
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| 53 | if (OR1K_SPR_SYS_UPR_TTP_GET(upr) == 0) { |
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| 54 | return -1; |
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| 55 | } |
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| 56 | |
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| 57 | /* Set this, for easy access when reloading */ |
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| 58 | uint32_t period = (_or1k_board_clk_freq/hz) & OR1K_SPR_TICK_TTMR_TP_MASK; |
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| 59 | OR1K_REENT.or1k_timer_period = period; |
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| 60 | or1k_mtspr(OR1K_SPR_TICK_TTMR_ADDR, period); |
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| 61 | |
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| 62 | /* Reset timer tick counter */ |
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| 63 | OR1K_REENT.or1k_timer_ticks = 0; |
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| 64 | |
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| 65 | /* Install handler */ |
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| 66 | or1k_exception_handler_add(0x5, _or1k_timer_interrupt_handler); |
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| 67 | OR1K_REENT.or1k_timer_mode = OR1K_SPR_TICK_TTMR_MODE_RESTART; |
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| 68 | |
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| 69 | /* Reset counter register */ |
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| 70 | or1k_mtspr(OR1K_SPR_TICK_TTCR_ADDR, 0); |
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| 71 | |
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| 72 | return 0; |
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| 73 | } |
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| 74 | |
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| 75 | void |
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| 76 | or1k_timer_set_period(uint32_t hz) |
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| 77 | { |
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| 78 | uint32_t period = (_or1k_board_clk_freq/hz) & OR1K_SPR_TICK_TTMR_TP_MASK; |
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| 79 | uint32_t ttmr = or1k_mfspr(OR1K_SPR_TICK_TTMR_ADDR); |
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| 80 | ttmr = OR1K_SPR_TICK_TTMR_TP_SET(ttmr, period); |
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| 81 | or1k_mtspr(OR1K_SPR_TICK_TTMR_ADDR, ttmr); |
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| 82 | OR1K_REENT.or1k_timer_period = period; |
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| 83 | } |
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| 84 | |
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| 85 | void |
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| 86 | or1k_timer_set_handler(void (*handler)(void)) |
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| 87 | { |
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| 88 | or1k_exception_handler_add(0x5, handler); |
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| 89 | } |
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| 90 | |
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| 91 | void |
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| 92 | or1k_timer_set_mode(uint32_t mode) |
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| 93 | { |
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| 94 | // Store mode in variable |
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| 95 | OR1K_REENT.or1k_timer_mode = mode; |
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| 96 | |
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| 97 | uint32_t ttmr = or1k_mfspr(OR1K_SPR_TICK_TTMR_ADDR); |
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| 98 | // If the timer is currently running, we also change the mode |
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| 99 | if (OR1K_SPR_TICK_TTMR_MODE_GET(ttmr) != 0) { |
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| 100 | ttmr = OR1K_SPR_TICK_TTMR_MODE_SET(ttmr, mode); |
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| 101 | or1k_mtspr(OR1K_SPR_TICK_TTMR_ADDR, ttmr); |
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| 102 | } |
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| 103 | } |
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| 104 | |
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| 105 | /* --------------------------------------------------------------------------*/ |
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| 106 | /*!Enable tick timer |
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| 107 | |
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| 108 | Enable timer interrupt, install handler, load TTMR |
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| 109 | */ |
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| 110 | /* --------------------------------------------------------------------------*/ |
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| 111 | void |
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| 112 | or1k_timer_enable(void) |
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| 113 | { |
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| 114 | uint32_t ttmr = or1k_mfspr(OR1K_SPR_TICK_TTMR_ADDR); |
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| 115 | ttmr = OR1K_SPR_TICK_TTMR_IE_SET(ttmr, 1); |
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| 116 | ttmr = OR1K_SPR_TICK_TTMR_MODE_SET(ttmr, OR1K_REENT.or1k_timer_mode); |
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| 117 | or1k_mtspr(OR1K_SPR_TICK_TTMR_ADDR, ttmr); |
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| 118 | |
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| 119 | uint32_t sr = or1k_mfspr(OR1K_SPR_SYS_SR_ADDR); |
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| 120 | sr = OR1K_SPR_SYS_SR_TEE_SET(sr, 1); |
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| 121 | or1k_mtspr(OR1K_SPR_SYS_SR_ADDR, sr); |
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| 122 | } |
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| 123 | |
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| 124 | /* --------------------------------------------------------------------------*/ |
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| 125 | /*!Disable tick timer |
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| 126 | |
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| 127 | Disable timer interrupt in SR |
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| 128 | */ |
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| 129 | /* --------------------------------------------------------------------------*/ |
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| 130 | uint32_t |
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| 131 | or1k_timer_disable(void) |
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| 132 | { |
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| 133 | uint32_t oldsr = or1k_mfspr(OR1K_SPR_SYS_SR_ADDR); |
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| 134 | uint32_t sr = OR1K_SPR_SYS_SR_TEE_SET(oldsr, 0); |
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| 135 | or1k_mtspr(OR1K_SPR_SYS_SR_ADDR, sr); |
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| 136 | return OR1K_SPR_SYS_SR_TEE_GET(oldsr); |
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| 137 | } |
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| 138 | |
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| 139 | void |
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| 140 | or1k_timer_restore(uint32_t sr_tee) |
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| 141 | { |
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| 142 | uint32_t sr = or1k_mfspr(OR1K_SPR_SYS_SR_ADDR); |
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| 143 | sr = OR1K_SPR_SYS_SR_TEE_SET(sr, sr_tee); |
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| 144 | or1k_mtspr(OR1K_SPR_SYS_SR_ADDR, sr); |
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| 145 | } |
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| 146 | |
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| 147 | void |
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| 148 | or1k_timer_pause(void) |
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| 149 | { |
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| 150 | uint32_t ttmr = or1k_mfspr(OR1K_SPR_TICK_TTMR_ADDR); |
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| 151 | ttmr = OR1K_SPR_TICK_TTMR_MODE_SET(ttmr, OR1K_SPR_TICK_TTMR_MODE_DISABLE); |
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| 152 | or1k_mtspr(OR1K_SPR_TICK_TTMR_ADDR, ttmr); |
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| 153 | } |
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| 154 | |
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| 155 | void |
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| 156 | or1k_timer_reset(void) |
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| 157 | { |
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| 158 | uint32_t ttmr = or1k_mfspr(OR1K_SPR_TICK_TTMR_ADDR); |
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| 159 | ttmr = OR1K_SPR_TICK_TTMR_IP_SET(ttmr, 0); |
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| 160 | or1k_mtspr(OR1K_SPR_TICK_TTMR_ADDR, ttmr); |
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| 161 | or1k_mtspr(OR1K_SPR_TICK_TTCR_ADDR, 0); |
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| 162 | } |
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| 163 | |
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| 164 | /* --------------------------------------------------------------------------*/ |
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| 165 | /*!Get tick timer |
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| 166 | |
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| 167 | Return value of tick timer |
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| 168 | */ |
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| 169 | /* --------------------------------------------------------------------------*/ |
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| 170 | unsigned long |
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| 171 | or1k_timer_get_ticks(void) |
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| 172 | { |
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| 173 | return OR1K_REENT.or1k_timer_ticks; |
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| 174 | } |
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| 175 | |
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| 176 | /* --------------------------------------------------------------------------*/ |
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| 177 | /*!Reset tick timer |
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| 178 | |
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| 179 | Clear value of tick timer |
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| 180 | */ |
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| 181 | /* --------------------------------------------------------------------------*/ |
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| 182 | void |
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| 183 | or1k_timer_reset_ticks(void) |
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| 184 | { |
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| 185 | OR1K_REENT.or1k_timer_ticks = 0; |
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| 186 | } |
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