| 1 | /* Cache code for SPARClite |
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| 2 | * |
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| 3 | * Copyright (c) 1998 Cygnus Support |
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| 4 | * |
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| 5 | * The authors hereby grant permission to use, copy, modify, distribute, |
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| 6 | * and license this software and its documentation for any purpose, provided |
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| 7 | * that existing copyright notices are retained in all copies and that this |
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| 8 | * notice is included verbatim in any distributions. No written agreement, |
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| 9 | * license, or royalty fee is required for any of the authorized uses. |
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| 10 | * Modifications to this software may be copyrighted by their authors |
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| 11 | * and need not follow the licensing terms described here, provided that |
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| 12 | * the new terms are clearly indicated on the first page of each file where |
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| 13 | * they apply. |
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| 14 | */ |
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| 15 | |
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| 16 | #include "sparclite.h" |
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| 17 | |
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| 18 | /* Ancillary registers on the DANlite */ |
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| 19 | |
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| 20 | #define DIAG 30 |
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| 21 | #define ICCR 31 |
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| 22 | |
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| 23 | /* Bits in the DIAG register */ |
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| 24 | |
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| 25 | #define ICD 0x40000000 /* ICACHE disable */ |
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| 26 | #define DCD 0x20000000 /* DCACHE disable */ |
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| 27 | |
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| 28 | /* Bits in the ICCR register */ |
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| 29 | |
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| 30 | #define CE 1 /* cache enable*/ |
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| 31 | |
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| 32 | |
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| 33 | /* Forward declarations. */ |
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| 34 | |
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| 35 | void flush_i_cache (); |
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| 36 | |
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| 37 | |
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| 38 | /* Determine if this is a DANlite (MB8686x), as opposed to an earlier |
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| 39 | SPARClite (MB8683x). This is done by examining the impl and ver |
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| 40 | fields in the PSR: |
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| 41 | |
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| 42 | MB8683x: impl(bit31-28)=0x0; ver(bit27-24)=0xf; |
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| 43 | MB8686x: impl(bit31-28)=0x1; ver(bit27-24)=0xe; |
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| 44 | */ |
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| 45 | |
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| 46 | static int |
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| 47 | is_danlite () |
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| 48 | { |
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| 49 | static int checked = 0; |
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| 50 | static int danlite = 0; |
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| 51 | |
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| 52 | if (!checked) |
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| 53 | { |
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| 54 | int psr = read_psr (); |
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| 55 | danlite = (psr & 0xff000000) == 0x1e000000; |
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| 56 | checked = 1; |
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| 57 | } |
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| 58 | return danlite; |
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| 59 | } |
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| 60 | |
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| 61 | /* This cache code is known to work on both the 930 & 932 processors. It just |
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| 62 | cheats and clears the all of the address space that could contain tags, as |
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| 63 | opposed to striding the tags at 8 or 16 word intervals, or using the cache |
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| 64 | flush registers, which don't exist on all processors. */ |
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| 65 | |
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| 66 | void |
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| 67 | cache_off () |
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| 68 | { |
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| 69 | if (is_danlite ()) |
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| 70 | { |
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| 71 | /* Disable the ICACHE. Disabling the DCACHE crashes the machine. */ |
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| 72 | unsigned int diag = read_asr (DIAG); |
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| 73 | write_asr (DIAG, diag | ICD); |
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| 74 | } |
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| 75 | else |
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| 76 | { |
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| 77 | write_asi (1, 0, 0); |
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| 78 | } |
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| 79 | } |
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| 80 | |
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| 81 | void |
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| 82 | cache_on () |
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| 83 | { |
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| 84 | if (is_danlite ()) |
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| 85 | { |
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| 86 | unsigned int diag; |
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| 87 | |
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| 88 | /* Flush the caches. */ |
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| 89 | flush_i_cache (); |
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| 90 | |
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| 91 | /* Enable the ICACHE and DCACHE */ |
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| 92 | diag = read_asr (DIAG); |
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| 93 | write_asr (DIAG, diag & ~ (ICD | DCD)); |
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| 94 | } |
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| 95 | else |
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| 96 | { |
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| 97 | unsigned long addr; |
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| 98 | |
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| 99 | cache_off (); /* Make sure the cache is off */ |
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| 100 | |
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| 101 | /* Reset all of the cache line valid bits */ |
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| 102 | |
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| 103 | for (addr = 0; addr < 0x1000; addr += 8) |
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| 104 | { |
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| 105 | write_asi (0xc, addr, 0); /* Clear bank 1, icache */ |
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| 106 | write_asi (0xc, addr + 0x80000000, 0); /* Clear bank 2, icache */ |
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| 107 | |
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| 108 | write_asi (0xe, addr, 0); /* Clear bank 1, dcache */ |
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| 109 | write_asi (0xe, addr + 0x80000000, 0); /* Clear bank 2, dcache */ |
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| 110 | } |
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| 111 | |
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| 112 | /* turn on the cache */ |
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| 113 | |
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| 114 | write_asi (1, 0, 0x35); /* Write buf ena, prefetch buf ena, data |
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| 115 | & inst caches enab */ |
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| 116 | } |
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| 117 | } |
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| 118 | |
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| 119 | /* Flush the instruction cache. We need to do this for the debugger stub so |
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| 120 | that breakpoints, et. al. become visible to the instruction stream after |
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| 121 | storing them in memory. |
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| 122 | */ |
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| 123 | |
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| 124 | void |
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| 125 | flush_i_cache () |
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| 126 | { |
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| 127 | if (is_danlite ()) |
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| 128 | { |
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| 129 | write_asi (0x31, 0, 0); /* Flush entire i/d caches */ |
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| 130 | } |
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| 131 | else |
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| 132 | { |
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| 133 | int cache_reg; |
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| 134 | unsigned long addr; |
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| 135 | |
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| 136 | cache_reg = read_asi (1, 0); /* Read cache/bus interface reg */ |
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| 137 | |
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| 138 | if (!(cache_reg & 1)) |
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| 139 | return; /* Just return if cache is already off */ |
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| 140 | |
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| 141 | for (addr = 0; addr < 0x1000; addr += 8) |
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| 142 | { |
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| 143 | write_asi (0xc, addr, 0); /* Clear bank 1, icache */ |
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| 144 | write_asi (0xc, addr + 0x80000000, 0); /* Clear bank 2, icache */ |
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| 145 | } |
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| 146 | } |
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| 147 | } |
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