source: trunk/libs/newlib/src/libgloss/sparc/salib-701.c @ 688

Last change on this file since 688 was 444, checked in by satin@…, 6 years ago

add newlib,libalmos-mkh, restructure shared_syscalls.h and mini-libc

File size: 7.4 KB
Line 
1/* Stand-alone library for Sparclet 701 board
2 *
3 * Copyright (c) 1996 Cygnus Support
4 *
5 * The authors hereby grant permission to use, copy, modify, distribute,
6 * and license this software and its documentation for any purpose, provided
7 * that existing copyright notices are retained in all copies and that this
8 * notice is included verbatim in any distributions. No written agreement,
9 * license, or royalty fee is required for any of the authorized uses.
10 * Modifications to this software may be copyrighted by their authors
11 * and need not follow the licensing terms described here, provided that
12 * the new terms are clearly indicated on the first page of each file where
13 * they apply.
14 */
15
16#define RAM_BASE                ((unsigned char *)0x12000000) /* Start of cacheable dram */
17#define DCACHE_LINES            128        /* Number of lines in data cache */
18#define DCACHE_LINE_SIZE        16         /* Bytes per data cache line */
19#define DCACHE_BANKS            4          /* 4-way associative */
20#define CACHE_INST_TAG_ADDR     ((unsigned char *)0xc0020000) /* I-Cache tag base address */
21#define ALL_BANKS               0x0000f000 /* Selects all 4 cache banks */
22#define ICACHE_LINES            128        /* Number of lines in inst cache */
23#define ICACHE_LINE_SIZE        32         /* Bytes per inst cache line */
24
25/* I/O Base addresses */
26#define CACHE_INST_BASE_ADD     0xc0000000
27#define CACHE_DATA_BASE_ADD     0xc8000000
28#define _InstrCacheCtlBase      0xc0000000
29#define _DataCacheCtlBase       0xc8000000
30
31#define USART_BASE_ADD          0x92000000
32#define USART_BASE_ADRS(n)      (USART_BASE_ADD + ((n)<<21))    /*0..3*/
33
34/* Serial receiver definitions */
35#define USART_RX_CHAR(n) (*(unsigned char *) (USART_BASE_ADRS(n)  +(2<<19)))
36#define USART_RX_CTRL_BASE_ADRS(n)       (USART_BASE_ADRS(n)+(3<<19))
37#define URSTR(n)        (*(unsigned int *) (USART_RX_CTRL_BASE_ADRS(n)+(2<<15)))
38#define URSTR_CHAR_NUM                  0x1f00  /* Bits 8-12 */
39
40/* Serial receiver definitions */
41#define USART_TX_CHAR(n)        (*(unsigned char *) (USART_BASE_ADRS(n)+3))
42#define USART_TX_CTRL_BASE_ADRS(n)       (USART_BASE_ADRS(n)+(1<<19))
43#define UTSTR(n)        (*(unsigned int *) (USART_TX_CTRL_BASE_ADRS(n)+(2<<15)))
44#define UTSTR_CHAR_FREE                 0x1f0   /* Bits 4-8 */
45
46/* Cache definitions */
47#define DCCA_NB_LINES       128         /* Nb of lines of the cache */
48/* Bank number, used for Cache Memory and Cache Tag */
49#define ICCA_B3         0x000008000     /* Bit 15 - 1:Bank3 selected       */
50#define ICCA_B2         0x000004000     /* Bit 14 - 1:Bank2 selected       */
51#define ICCA_B1         0x000002000     /* Bit 13 - 1:Bank1 selected       */
52#define ICCA_B0         0x000001000     /* Bit 12 - 1:Bank0 selected       */
53/* Register address, show which register is to be checked/updated */
54#define ICCACR          0x00000000      /* Bits 17 - 16 - Control register */
55#define ICCAMEM         0x00010000      /* Bits 17 - 16 - Cache memory     */
56#define DCCACR          0x00000000      /* Bits 16 - 15 - Control register */
57/* Instruction Cache Controller Register */
58#define ICCR_DISABLE  0xfffffffe        /* Reset enable bit                 */
59
60/* Serial I/O routines */
61
62#define STUB_PORT 1             /* 0 = serial port A;  1 = serial port B */
63
64static volatile unsigned char *rx_fifo = &USART_RX_CHAR(STUB_PORT);
65static volatile unsigned int *rx_status = &URSTR(STUB_PORT);
66
67static volatile unsigned char *tx_fifo = &USART_TX_CHAR(STUB_PORT);
68static volatile unsigned int *tx_status = &UTSTR(STUB_PORT);
69
70/* library-free debug reoutines */
71#ifdef XDEBUG
72#define XDBG_MSG(x) pmsg(x)
73#define XDBG_HEX(x) phex(x)
74#else
75#define XDBG_MSG(x)
76#define XDBG_HEX(x)
77#endif
78
79static int
80rx_rdy()
81{
82  return (*rx_status & URSTR_CHAR_NUM);
83}
84
85static unsigned char
86rx_char()
87{
88  return *rx_fifo;
89}
90
91void
92tx_char(char c)
93{
94  *tx_fifo = c;
95}
96
97static int
98tx_rdy()
99{
100  return (*tx_status & UTSTR_CHAR_FREE);
101}
102
103int
104getDebugChar()
105{
106  while (!rx_rdy())
107    ;
108  return rx_char();
109}
110
111void
112putDebugChar(int c)
113{
114  while (!tx_rdy())
115    ;
116  tx_char(c);
117}
118
119#ifdef XDEBUG
120/* library-free debug reoutines */
121/* print a string */
122void pmsg(char *p)
123{
124    while (*p)
125    {
126        if (*p == '\n')
127            putDebugChar('\r');
128        putDebugChar(*p++);
129    }
130}
131
132/* print a hex number */
133void phex(long x)
134{
135    char buf[9];
136    int i;
137
138    buf[8] = '\0';
139    for (i = 7; i >= 0; i--)
140    {
141        char c = x & 0x0f;
142        buf[i] = c < 10 ? c + '0' : c - 10 + 'A';
143        x >>= 4;
144    }
145    pmsg(buf);
146}
147#endif
148
149/* rdtbr() - read the trap base register */
150
151unsigned long rdtbr();
152
153asm("
154        .text
155        .align 4
156        .globl _rdtbr
157_rdtbr:
158        retl
159        mov     %tbr, %o0
160");
161
162/* wrtbr() - write the trap base register */
163
164void wrtbr(unsigned long);
165
166asm("
167        .text
168        .align 4
169        .globl _wrtbr
170_wrtbr:
171        retl
172        mov     %o0, %tbr
173");
174
175/* Each entry in the trap vector occupies four words. */
176
177struct trap_entry
178{
179  unsigned sethi_filler:10;
180  unsigned sethi_imm22:22;
181  unsigned jmpl_filler:19;
182  unsigned jmpl_simm13:13;
183  unsigned long filler[2];
184};
185
186extern struct trap_entry fltr_proto;
187asm ("
188        .data
189        .globl _fltr_proto
190        .align 4
191_fltr_proto:                    ! First level trap routine prototype
192        sethi 0, %l0
193        jmpl 0+%l0, %g0
194        nop
195        nop
196
197        .text
198        .align 4
199");
200
201/* copy_vectors - Copy the trap vectors from ROM to RAM, set the TBR register
202   to point to the RAM vectors, and return the address of the RAM vectors.  */
203
204extern struct trap_entry __trap_vectors[256];   /* defined in matra.ld */
205
206struct trap_entry *copy_vectors()
207{
208  int i;
209  struct trap_entry *old = (struct trap_entry *) (rdtbr() & ~0xfff);
210
211  XDBG_MSG("Copying vectors...\n");
212  for (i = 0; i < 256; i++)
213    __trap_vectors[i] = old[i];
214  wrtbr ((unsigned long)__trap_vectors);
215  XDBG_MSG("Done\n");
216  return __trap_vectors;
217}
218
219
220void
221disable_cache()
222{
223  unsigned long *ptr;
224  static unsigned long CACHE_shadow_iccr = 0;   /* Because CR cannot be read */
225  static unsigned long CACHE_shadow_dccr = 0;   /* Because CR cannot be read */
226
227  XDBG_MSG("Disabling cache...\n");
228  ptr = (unsigned long*)(CACHE_INST_BASE_ADD | ICCACR);
229  CACHE_shadow_iccr = CACHE_shadow_iccr & ICCR_DISABLE;
230  *ptr = CACHE_shadow_iccr;
231
232  ptr = (unsigned long*)(CACHE_DATA_BASE_ADD | DCCACR);
233  CACHE_shadow_dccr = CACHE_shadow_dccr & ICCR_DISABLE;
234  *ptr = CACHE_shadow_dccr;
235  XDBG_MSG("Done\n");
236}
237
238/* Flush the instruction cache.  We need to do this for the debugger stub so
239   that breakpoints, et. al. become visible to the instruction stream after
240   storing them in memory.  FIXME!!
241 */
242
243void
244flush_i_cache ()
245{
246  volatile unsigned char *addr;
247
248  /* First, force all dirty items in the data cache to be moved out to real
249     memory.  This is done by making read refs to alternate addresses that will
250     fill up all four banks for each line.  Note that we actually have to
251     reference 8 locs per line just in case the region of memory we use is one
252     of the areas that needs to be flushed.  */
253
254  for (addr = RAM_BASE;
255       addr < RAM_BASE + (DCACHE_LINES * DCACHE_LINE_SIZE * DCACHE_BANKS) * 2;
256       addr += DCACHE_LINE_SIZE)
257    *addr;                      /* Read the loc */
258
259  /* Now, flush the instruction cache.  */
260
261  for (addr = CACHE_INST_TAG_ADDR + ALL_BANKS;
262       addr <= CACHE_INST_TAG_ADDR + ALL_BANKS + ICACHE_LINES * ICACHE_LINE_SIZE;
263       addr += ICACHE_LINE_SIZE)
264    *(unsigned long *)addr = 0; /* Clr tag entry for all banks on this line */
265}
266
267/* Setup trap TT to go to ROUTINE. */
268
269void
270exceptionHandler (int tt, unsigned long routine)
271{
272  static struct trap_entry *tb;         /* Trap vector base address */
273
274  if (!tb)
275    {
276      tb = copy_vectors();              /* Copy trap vectors to RAM */
277      disable_cache();                  /* Disable cache  FIXME!! */
278    }
279
280  XDBG_MSG("Setting exception handler for trap...\n");
281
282  tb[tt] = fltr_proto;
283
284  tb[tt].sethi_imm22 = routine >> 10;
285  tb[tt].jmpl_simm13 = routine & 0x3ff;
286
287  XDBG_MSG("Done\n");
288}
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