| 1 | /* |
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| 2 | * Copyright (c) 1995, 1996 Cygnus Support |
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| 3 | * |
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| 4 | * The authors hereby grant permission to use, copy, modify, distribute, |
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| 5 | * and license this software and its documentation for any purpose, provided |
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| 6 | * that existing copyright notices are retained in all copies and that this |
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| 7 | * notice is included verbatim in any distributions. No written agreement, |
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| 8 | * license, or royalty fee is required for any of the authorized uses. |
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| 9 | * Modifications to this software may be copyrighted by their authors |
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| 10 | * and need not follow the licensing terms described here, provided that |
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| 11 | * the new terms are clearly indicated on the first page of each file where |
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| 12 | * they apply. |
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| 13 | */ |
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| 14 | |
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| 15 | #define STACK_SIZE 16 * 1024 |
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| 16 | #define TRAP_STACK_SIZE 4 * 1024 |
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| 17 | #define NUM_REGS 20 |
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| 18 | |
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| 19 | #ifdef SL933 |
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| 20 | #define NUMBER_OF_REGISTER_WINDOWS 6 |
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| 21 | #else |
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| 22 | #define NUMBER_OF_REGISTER_WINDOWS 8 |
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| 23 | #endif |
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| 24 | |
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| 25 | #if (NUMBER_OF_REGISTER_WINDOWS == 8) |
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| 26 | #define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */ |
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| 27 | #elif (NUMBER_OF_REGISTER_WINDOWS == 16) |
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| 28 | #define SPARC_PSR_CWP_MASK 0x0F /* bits 0 - 4 */ |
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| 29 | #elif (NUMBER_OF_REGISTER_WINDOWS == 32) |
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| 30 | #define SPARC_PSR_CWP_MASK 0x1F /* bits 0 - 4 */ |
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| 31 | #else |
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| 32 | #error "Unsupported number of register windows for this cpu" |
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| 33 | #endif |
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| 34 | |
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| 35 | /* The traptable has to be the first code in a boot PROM. */ |
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| 36 | |
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| 37 | /* |
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| 38 | * Entry for traps which jump to a programmer-specified trap handler. |
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| 39 | */ |
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| 40 | |
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| 41 | #define TRAP(_handler) \ |
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| 42 | sethi %hi(_handler), %l3 ; \ |
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| 43 | jmpl %l3+%lo(_handler), %g0 ; \ |
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| 44 | mov %wim, %l0 ; \ |
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| 45 | nop |
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| 46 | |
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| 47 | /* Unexcpected trap will halt the processor by forcing it to error state */ |
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| 48 | #if 1 |
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| 49 | #define BAD_TRAP ta 0; nop; nop; nop; |
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| 50 | #else |
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| 51 | #define BAD_TRAP \ |
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| 52 | mov %psr, l0 ; \ |
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| 53 | mov 0x0, %o0 ; \ |
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| 54 | sethi %hi(SYM(bad_trap)), l4 ; \ |
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| 55 | jmp l4+%lo(SYM(bad_trap)); |
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| 56 | #endif |
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| 57 | |
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| 58 | /* Software trap. Treat as BAD_TRAP for the time being... */ |
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| 59 | #if 1 |
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| 60 | #define SOFT_TRAP BAD_TRAP |
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| 61 | #else |
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| 62 | #define SOFT_TRAP \ |
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| 63 | mov $psr, $l0 ; \ |
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| 64 | mov 0x0, $o0 ; \ |
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| 65 | sethi $hi(SYM(soft_trap)), l4 ; \ |
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| 66 | jmp l4+$lo(SYM(soft_trap)); |
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| 67 | #endif |
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| 68 | |
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| 69 | #define PSR_INIT 0x10c0 /* Disable traps, set s and ps */ |
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| 70 | #define TBR_INIT 0 |
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| 71 | #define WIM_INIT 2 |
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| 72 | #define SP_INIT 0x023ffff0 |
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| 73 | |
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| 74 | /* Macros for reading and writing to arbitrary address spaces. Note that ASI |
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| 75 | must be a constant (sorry, but the SPARC can only specify ASIs as part of an |
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| 76 | instruction. */ |
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| 77 | |
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| 78 | #define read_asi(ASI, LOC) \ |
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| 79 | ({ \ |
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| 80 | unsigned int val; \ |
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| 81 | __asm__ volatile ("lda [%r1]%2,%0" : "=r" (val) : "rJ" (LOC), "I" (ASI)); \ |
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| 82 | val; \ |
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| 83 | }) |
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| 84 | |
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| 85 | #define write_asi(ASI, LOC, VAL) \ |
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| 86 | __asm__ volatile ("sta %0,[%r1]%2" : : "r" (VAL), "rJ" (LOC), "I" (ASI)); |
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| 87 | |
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| 88 | /* |
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| 89 | * Use this when modifying registers that cause memory to be modified. This |
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| 90 | * will cause GCC to reload all values after this point. |
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| 91 | */ |
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| 92 | #define write_asi_volatile(ASI, LOC, VAL) \ |
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| 93 | __asm__ volatile ("sta %0,[%r1]%2" : : "r" (VAL), "rJ" (LOC), "I" (ASI) \ |
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| 94 | : "memory"); |
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| 95 | |
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| 96 | #define WRITE_PC(x) registers[PC] = x; registers[NPC] = x + 4; |
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| 97 | |
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| 98 | /* |
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| 99 | * Processor Status Register (psr) |
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| 100 | * |
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| 101 | * 31 28|27 24|23 20|19 12|11 9|7|6|5|4 0 |
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| 102 | * +------+-------+-------+-------+------+-+-+-+--------+ |
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| 103 | * | impl | ver | icc | res. | pil | | | | cwp | |
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| 104 | * +------+-------+-------+-------+------+-+-+-+--------+ |
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| 105 | * S P E |
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| 106 | * S T |
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| 107 | * if ET = 1, traps are enabled, 0 means disabled. |
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| 108 | * if S = 1, you're in supervisor mode, 0 means user mode. |
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| 109 | * cwp points to the current window. |
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| 110 | * |
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| 111 | * Trap Base Register (tbr) |
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| 112 | * |
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| 113 | * 31 12|11 4|3 0 |
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| 114 | * +--------------+--------------+------+ |
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| 115 | * | tba | tt | null | |
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| 116 | * +--------------+--------------+------+ |
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| 117 | * |
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| 118 | * tba contains the most sig. 20 bits of the tbr base address |
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| 119 | * tt is the trap number. |
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| 120 | * |
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| 121 | * Window Invalid Register (wim) |
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| 122 | * 31 8| 7| 6| 5| 4| 3| 2| 1| 0 |
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| 123 | * +-------------+--+--+--+--+--+--+--+--+ |
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| 124 | * | res. |w7|w6|w5|w4|w3|w2|w1|w0| |
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| 125 | * +-------------+--+--+--+--+--+--+--+--+ |
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| 126 | */ |
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| 127 | |
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