| 1 | /* SPARClite defs |
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| 2 | * |
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| 3 | * Copyright (c) 1995 Cygnus Support |
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| 4 | * |
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| 5 | * The authors hereby grant permission to use, copy, modify, distribute, |
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| 6 | * and license this software and its documentation for any purpose, provided |
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| 7 | * that existing copyright notices are retained in all copies and that this |
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| 8 | * notice is included verbatim in any distributions. No written agreement, |
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| 9 | * license, or royalty fee is required for any of the authorized uses. |
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| 10 | * Modifications to this software may be copyrighted by their authors |
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| 11 | * and need not follow the licensing terms described here, provided that |
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| 12 | * the new terms are clearly indicated on the first page of each file where |
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| 13 | * they apply. |
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| 14 | */ |
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| 15 | |
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| 16 | /* Macros for reading and writing to arbitrary address spaces. Note that ASI |
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| 17 | must be a constant (sorry, but the SPARC can only specify ASIs as part of an |
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| 18 | instruction. */ |
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| 19 | |
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| 20 | #define read_asi(ASI, LOC) \ |
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| 21 | ({ \ |
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| 22 | unsigned int val; \ |
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| 23 | __asm__ volatile ("lda [%r1]%2,%0" : "=r" (val) : "rJ" (LOC), "I" (ASI)); \ |
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| 24 | val; \ |
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| 25 | }) |
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| 26 | |
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| 27 | #define write_asi(ASI, LOC, VAL) \ |
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| 28 | __asm__ volatile ("sta %0,[%r1]%2" : : "r" (VAL), "rJ" (LOC), "I" (ASI)) |
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| 29 | |
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| 30 | /* Use this when modifying registers that cause memory to be modified. This |
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| 31 | will cause GCC to reload all values after this point. */ |
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| 32 | |
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| 33 | #define write_asi_volatile(ASI, LOC, VAL) \ |
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| 34 | __asm__ volatile ("sta %0,[%r1]%2" : : "r" (VAL), "rJ" (LOC), "I" (ASI) \ |
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| 35 | : "memory") |
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| 36 | |
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| 37 | /* Read the PSR (processor state register). */ |
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| 38 | |
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| 39 | #define read_psr() \ |
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| 40 | ({ \ |
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| 41 | unsigned int psr; \ |
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| 42 | __asm__ ("mov %%psr, %0" : "=r" (psr)); \ |
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| 43 | psr; \ |
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| 44 | }) |
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| 45 | |
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| 46 | /* Write the PSR. */ |
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| 47 | |
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| 48 | #define write_psr(VAL) \ |
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| 49 | __asm__ ("mov %0, %%psr \n nop \n nop \n nop" : : "r" (VAL)) |
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| 50 | |
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| 51 | /* Read the specified Ancillary State Register. */ |
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| 52 | |
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| 53 | #define read_asr(REG) read_asr1(REG) |
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| 54 | #define read_asr1(REG) \ |
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| 55 | ({ \ |
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| 56 | unsigned int val; \ |
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| 57 | __asm__ ("rd %%asr" #REG ",%0" : "=r" (val)); \ |
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| 58 | val; \ |
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| 59 | }) |
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| 60 | |
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| 61 | /* Write the specified Ancillary State Register. */ |
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| 62 | |
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| 63 | #define write_asr(REG, VAL) write_asr1(REG, VAL) |
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| 64 | #define write_asr1(REG, VAL) \ |
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| 65 | __asm__ ("wr %0, 0, %%asr" #REG : : "r" (VAL)) |
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| 66 | |
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| 67 | /* Set window size for window overflow and underflow trap handlers. Better to |
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| 68 | do this at at compile time than to calculate them at compile time each time |
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| 69 | we get a window overflow/underflow trap. */ |
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| 70 | |
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| 71 | #ifdef SL933 |
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| 72 | asm ("__WINSIZE=6"); |
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| 73 | #else |
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| 74 | asm ("__WINSIZE=8"); |
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| 75 | #endif |
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| 76 | |
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| 77 | #define PSR_INIT 0x10c0 /* Disable traps, set s and ps */ |
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| 78 | #define TBR_INIT 0 |
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| 79 | #define WIM_INIT 2 |
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| 80 | #define STACK_SIZE 16 * 1024 |
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| 81 | |
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