| 1 | /* |
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| 2 | * Copyright (c) 2011 Aeroflex Gaisler |
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| 3 | * |
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| 4 | * BSD license: |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
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| 7 | * of this software and associated documentation files (the "Software"), to deal |
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| 8 | * in the Software without restriction, including without limitation the rights |
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| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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| 10 | * copies of the Software, and to permit persons to whom the Software is |
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| 11 | * furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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| 22 | * THE SOFTWARE. |
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| 23 | */ |
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| 24 | |
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| 25 | |
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| 26 | #include <asm-leon/leon.h> |
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| 27 | #include <asm-leon/leonstack.h> |
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| 28 | #include <asm-leon/asmmacro.h> |
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| 29 | |
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| 30 | /* Store the register window onto the 8-byte aligned area starting |
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| 31 | * at %reg. It might be %sp, it might not, we don't care. |
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| 32 | */ |
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| 33 | #define RW_STORE(reg) \ |
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| 34 | std %l0, [%reg + RW_L0]; \ |
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| 35 | std %l2, [%reg + RW_L2]; \ |
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| 36 | std %l4, [%reg + RW_L4]; \ |
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| 37 | std %l6, [%reg + RW_L6]; \ |
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| 38 | std %i0, [%reg + RW_I0]; \ |
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| 39 | std %i2, [%reg + RW_I2]; \ |
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| 40 | std %i4, [%reg + RW_I4]; \ |
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| 41 | std %i6, [%reg + RW_I6]; |
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| 42 | |
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| 43 | /* Load a register window from the area beginning at %reg. */ |
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| 44 | #define RW_LOAD(reg) \ |
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| 45 | ldd [%reg + RW_L0], %l0; \ |
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| 46 | ldd [%reg + RW_L2], %l2; \ |
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| 47 | ldd [%reg + RW_L4], %l4; \ |
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| 48 | ldd [%reg + RW_L6], %l6; \ |
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| 49 | ldd [%reg + RW_I0], %i0; \ |
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| 50 | ldd [%reg + RW_I2], %i2; \ |
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| 51 | ldd [%reg + RW_I4], %i4; \ |
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| 52 | ldd [%reg + RW_I6], %i6; |
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| 53 | |
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| 54 | /* Loading and storing struct pt_reg trap frames. */ |
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| 55 | #define PT_LOAD_INS(base_reg) \ |
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| 56 | ldd [%base_reg + SF_REGS_SZ + PT_I0], %i0; \ |
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| 57 | ldd [%base_reg + SF_REGS_SZ + PT_I2], %i2; \ |
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| 58 | ldd [%base_reg + SF_REGS_SZ + PT_I4], %i4; \ |
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| 59 | ldd [%base_reg + SF_REGS_SZ + PT_I6], %i6; |
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| 60 | |
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| 61 | #define PT_LOAD_GLOBALS(base_reg) \ |
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| 62 | ld [%base_reg + SF_REGS_SZ + PT_G1], %g1; \ |
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| 63 | ldd [%base_reg + SF_REGS_SZ + PT_G2], %g2; \ |
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| 64 | ldd [%base_reg + SF_REGS_SZ + PT_G4], %g4; \ |
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| 65 | ldd [%base_reg + SF_REGS_SZ + PT_G6], %g6; |
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| 66 | |
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| 67 | #define PT_LOAD_GLOBALS_23(base_reg) \ |
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| 68 | ldd [%base_reg + SF_REGS_SZ + PT_G2], %g2; |
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| 69 | |
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| 70 | #define PT_LOAD_YREG(base_reg, scratch) \ |
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| 71 | ld [%base_reg + SF_REGS_SZ + PT_Y], %scratch; \ |
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| 72 | wr %scratch, 0x0, %y; |
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| 73 | |
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| 74 | #define PT_LOAD_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \ |
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| 75 | ld [%base_reg + SF_REGS_SZ + PT_PSR], %pt_psr; \ |
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| 76 | ld [%base_reg + SF_REGS_SZ + PT_PC], %pt_pc; \ |
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| 77 | ld [%base_reg + SF_REGS_SZ + PT_NPC], %pt_npc; |
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| 78 | |
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| 79 | #define PT_LOAD_ALL(base_reg, pt_psr, pt_pc, pt_npc, scratch) \ |
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| 80 | PT_LOAD_YREG(base_reg, scratch) \ |
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| 81 | PT_LOAD_INS(base_reg) \ |
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| 82 | PT_LOAD_GLOBALS(base_reg) \ |
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| 83 | PT_LOAD_PRIV(base_reg, pt_psr, pt_pc, pt_npc) |
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| 84 | |
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| 85 | #define PT_LOAD_ALL_FAST(base_reg, pt_psr, pt_pc, pt_npc, scratch) \ |
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| 86 | PT_LOAD_YREG(base_reg, scratch) \ |
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| 87 | PT_LOAD_GLOBALS(base_reg) |
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| 88 | |
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| 89 | #define PT_STORE_INS(base_reg) \ |
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| 90 | std %i0, [%base_reg + SF_REGS_SZ + PT_I0]; \ |
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| 91 | std %i2, [%base_reg + SF_REGS_SZ + PT_I2]; \ |
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| 92 | std %i4, [%base_reg + SF_REGS_SZ + PT_I4]; \ |
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| 93 | std %i6, [%base_reg + SF_REGS_SZ + PT_I6]; |
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| 94 | |
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| 95 | #define PT_STORE_GLOBALS(base_reg) \ |
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| 96 | st %g1, [%base_reg + SF_REGS_SZ + PT_G1]; \ |
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| 97 | std %g2, [%base_reg + SF_REGS_SZ + PT_G2]; \ |
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| 98 | std %g4, [%base_reg + SF_REGS_SZ + PT_G4]; \ |
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| 99 | std %g6, [%base_reg + SF_REGS_SZ + PT_G6]; |
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| 100 | |
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| 101 | #define PT_STORE_GLOBALS_23(base_reg) \ |
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| 102 | std %g2, [%base_reg + SF_REGS_SZ + PT_G2]; |
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| 103 | |
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| 104 | #define PT_STORE_YREG(base_reg, scratch) \ |
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| 105 | rd %y, %scratch; \ |
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| 106 | st %scratch, [%base_reg + SF_REGS_SZ + PT_Y]; |
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| 107 | |
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| 108 | #define PT_STORE_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \ |
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| 109 | st %pt_psr, [%base_reg + SF_REGS_SZ + PT_PSR]; \ |
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| 110 | st %pt_pc, [%base_reg + SF_REGS_SZ + PT_PC]; \ |
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| 111 | st %pt_npc, [%base_reg + SF_REGS_SZ + PT_NPC]; |
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| 112 | |
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| 113 | #define PT_STORE_ALL(base_reg, reg_psr, reg_pc, reg_npc, g_scratch) \ |
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| 114 | PT_STORE_PRIV(base_reg, reg_psr, reg_pc, reg_npc) \ |
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| 115 | PT_STORE_GLOBALS(base_reg) \ |
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| 116 | PT_STORE_YREG(base_reg, g_scratch) \ |
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| 117 | PT_STORE_INS(base_reg) |
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| 118 | |
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| 119 | #define PT_STORE_ALL_FAST(base_reg, reg_psr, reg_pc, reg_npc, g_scratch) \ |
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| 120 | PT_STORE_GLOBALS(base_reg) \ |
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| 121 | PT_STORE_YREG(base_reg, g_scratch) |
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| 122 | |
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| 123 | /* Store the fpu register window*/ |
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| 124 | #define FW_STORE(reg) \ |
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| 125 | std %f0, [reg + FW_F0]; \ |
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| 126 | std %f2, [reg + FW_F2]; \ |
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| 127 | std %f4, [reg + FW_F4]; \ |
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| 128 | std %f6, [reg + FW_F6]; \ |
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| 129 | std %f8, [reg + FW_F8]; \ |
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| 130 | std %f10, [reg + FW_F10]; \ |
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| 131 | std %f12, [reg + FW_F12]; \ |
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| 132 | std %f14, [reg + FW_F14]; \ |
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| 133 | std %f16, [reg + FW_F16]; \ |
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| 134 | std %f18, [reg + FW_F18]; \ |
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| 135 | std %f20, [reg + FW_F20]; \ |
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| 136 | std %f22, [reg + FW_F22]; \ |
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| 137 | std %f24, [reg + FW_F24]; \ |
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| 138 | std %f26, [reg + FW_F26]; \ |
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| 139 | std %f28, [reg + FW_F28]; \ |
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| 140 | std %f30, [reg + FW_F30]; \ |
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| 141 | st %fsr, [reg + FW_FSR]; |
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| 142 | |
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| 143 | /* Load a fpu register window from the area beginning at reg. */ |
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| 144 | #define FW_LOAD(reg) \ |
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| 145 | ldd [reg + FW_F0], %f0; \ |
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| 146 | ldd [reg + FW_F2], %f2; \ |
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| 147 | ldd [reg + FW_F4], %f4; \ |
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| 148 | ldd [reg + FW_F6], %f6; \ |
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| 149 | ldd [reg + FW_F8], %f8; \ |
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| 150 | ldd [reg + FW_F10], %f10; \ |
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| 151 | ldd [reg + FW_F12], %f12; \ |
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| 152 | ldd [reg + FW_F14], %f14; \ |
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| 153 | ldd [reg + FW_F16], %f16; \ |
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| 154 | ldd [reg + FW_F18], %f18; \ |
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| 155 | ldd [reg + FW_F20], %f20; \ |
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| 156 | ldd [reg + FW_F22], %f22; \ |
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| 157 | ldd [reg + FW_F24], %f24; \ |
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| 158 | ldd [reg + FW_F26], %f26; \ |
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| 159 | ldd [reg + FW_F28], %f28; \ |
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| 160 | ldd [reg + FW_F30], %f30; \ |
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| 161 | ld [reg + FW_FSR], %fsr; |
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| 162 | |
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| 163 | #define SET_WIM_CWPMIN2(psr_reg,tmp1,tmp2,tmp3,tmp4) \ |
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| 164 | sethi %hi(_nwindows_min2), %##tmp1; \ |
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| 165 | and %##psr_reg, SPARC_PSR_WIN_MASK, %##tmp3; \ |
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| 166 | mov 1, %##tmp2; \ |
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| 167 | ld [ %##tmp1 + %lo(_nwindows_min2)], %##tmp1; \ |
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| 168 | sll %##tmp2, %##tmp3, %##tmp3; \ |
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| 169 | sll %##tmp3, 2, %##tmp4; \ |
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| 170 | srl %##tmp3, %##tmp1, %##tmp1; \ |
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| 171 | or %##tmp4, %##tmp1, %##tmp3; \ |
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| 172 | wr %##tmp3, 0x0, %wim; \ |
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| 173 | nop; nop; nop; |
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| 174 | |
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| 175 | #define SET_WIM_CWPMIN1(psr_reg,tmp1,tmp2,tmp3,tmp4) \ |
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| 176 | sethi %hi(_nwindows_min1), %##tmp1; \ |
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| 177 | and %##psr_reg, SPARC_PSR_WIN_MASK, %##tmp3; \ |
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| 178 | mov 1, %##tmp2; \ |
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| 179 | ld [ %##tmp1 + %lo(_nwindows_min1)], %##tmp1; \ |
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| 180 | sll %##tmp2, %##tmp3, %##tmp3; \ |
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| 181 | sll %##tmp3, 1, %##tmp4; \ |
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| 182 | srl %##tmp3, %##tmp1, %##tmp1; \ |
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| 183 | or %##tmp4, %##tmp1, %##tmp3; \ |
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| 184 | wr %##tmp3, 0x0, %wim; \ |
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| 185 | nop; nop; nop; |
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