| 1 | /*
|
|---|
| 2 | Copyright (c) 2015, Synopsys, Inc. All rights reserved.
|
|---|
| 3 |
|
|---|
| 4 | Redistribution and use in source and binary forms, with or without
|
|---|
| 5 | modification, are permitted provided that the following conditions are met:
|
|---|
| 6 |
|
|---|
| 7 | 1) Redistributions of source code must retain the above copyright notice,
|
|---|
| 8 | this list of conditions and the following disclaimer.
|
|---|
| 9 |
|
|---|
| 10 | 2) Redistributions in binary form must reproduce the above copyright notice,
|
|---|
| 11 | this list of conditions and the following disclaimer in the documentation
|
|---|
| 12 | and/or other materials provided with the distribution.
|
|---|
| 13 |
|
|---|
| 14 | 3) Neither the name of the Synopsys, Inc., nor the names of its contributors
|
|---|
| 15 | may be used to endorse or promote products derived from this software
|
|---|
| 16 | without specific prior written permission.
|
|---|
| 17 |
|
|---|
| 18 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|---|
| 19 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|---|
| 20 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|---|
| 21 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
|---|
| 22 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|---|
| 23 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|---|
| 24 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|---|
| 25 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|---|
| 26 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|---|
| 27 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|---|
| 28 | POSSIBILITY OF SUCH DAMAGE.
|
|---|
| 29 | */
|
|---|
| 30 |
|
|---|
| 31 | /* ABI interface file
|
|---|
| 32 | these are the stack mappings for the registers
|
|---|
| 33 | as stored in the ABI for ARC */
|
|---|
| 34 |
|
|---|
| 35 | .file "setjmp.S"
|
|---|
| 36 |
|
|---|
| 37 | ABIr13 = 0
|
|---|
| 38 | ABIr14 = ABIr13 + 4
|
|---|
| 39 | ABIr15 = ABIr14 + 4
|
|---|
| 40 | ABIr16 = ABIr15 + 4
|
|---|
| 41 | ABIr17 = ABIr16 + 4
|
|---|
| 42 | ABIr18 = ABIr17 + 4
|
|---|
| 43 | ABIr19 = ABIr18 + 4
|
|---|
| 44 | ABIr20 = ABIr19 + 4
|
|---|
| 45 | ABIr21 = ABIr20 + 4
|
|---|
| 46 | ABIr22 = ABIr21 + 4
|
|---|
| 47 | ABIr23 = ABIr22 + 4
|
|---|
| 48 | ABIr24 = ABIr23 + 4
|
|---|
| 49 | ABIr25 = ABIr24 + 4
|
|---|
| 50 | ABIr26 = ABIr25 + 4
|
|---|
| 51 | ABIr27 = ABIr26 + 4
|
|---|
| 52 | ABIr28 = ABIr27 + 4
|
|---|
| 53 | ABIr29 = ABIr28 + 4
|
|---|
| 54 | ABIr30 = ABIr29 + 4
|
|---|
| 55 | ABIr31 = ABIr30 + 4
|
|---|
| 56 | ABIlpc = ABIr31 + 4
|
|---|
| 57 | ABIlps = ABIlpc + 4
|
|---|
| 58 | ABIlpe = ABIlps + 4
|
|---|
| 59 |
|
|---|
| 60 | ABIflg = ABIlpe + 4
|
|---|
| 61 | ABImlo = ABIflg + 4
|
|---|
| 62 | ABImhi = ABImlo + 4
|
|---|
| 63 |
|
|---|
| 64 | .text
|
|---|
| 65 | .align 4
|
|---|
| 66 | .global setjmp
|
|---|
| 67 | .type setjmp,@function
|
|---|
| 68 | setjmp:
|
|---|
| 69 | st r13, [r0, ABIr13]
|
|---|
| 70 | st r14, [r0, ABIr14]
|
|---|
| 71 | st r15, [r0, ABIr15]
|
|---|
| 72 | st r16, [r0, ABIr16]
|
|---|
| 73 | st r17, [r0, ABIr17]
|
|---|
| 74 | st r18, [r0, ABIr18]
|
|---|
| 75 | st r19, [r0, ABIr19]
|
|---|
| 76 | st r20, [r0, ABIr20]
|
|---|
| 77 | st r21, [r0, ABIr21]
|
|---|
| 78 | st r22, [r0, ABIr22]
|
|---|
| 79 | st r23, [r0, ABIr23]
|
|---|
| 80 | st r24, [r0, ABIr24]
|
|---|
| 81 | st r25, [r0, ABIr25]
|
|---|
| 82 | st r26, [r0, ABIr26]
|
|---|
| 83 | st r27, [r0, ABIr27]
|
|---|
| 84 | st r28, [r0, ABIr28]
|
|---|
| 85 | st r29, [r0, ABIr29]
|
|---|
| 86 | st r30, [r0, ABIr30]
|
|---|
| 87 | st blink, [r0, ABIr31]
|
|---|
| 88 | st lp_count, [r0, ABIlpc]
|
|---|
| 89 |
|
|---|
| 90 | lr r2, [lp_start]
|
|---|
| 91 | lr r3, [lp_end]
|
|---|
| 92 | st r2, [r0, ABIlps]
|
|---|
| 93 | st r3, [r0, ABIlpe]
|
|---|
| 94 |
|
|---|
| 95 | #if (!defined (__ARC700__) && !defined (__ARCEM__) && !defined (__ARCHS__))
|
|---|
| 96 | ; Till the configure changes are decided, and implemented, the code working on
|
|---|
| 97 | ; mlo/mhi and using mul64 should be disabled.
|
|---|
| 98 | ; st mlo, [r0, ABImlo]
|
|---|
| 99 | ; st mhi, [r0, ABImhi]
|
|---|
| 100 | lr r2, [status32]
|
|---|
| 101 | st r2, [r0, ABIflg]
|
|---|
| 102 | #endif
|
|---|
| 103 |
|
|---|
| 104 | j.d [blink]
|
|---|
| 105 | mov r0,0
|
|---|
| 106 | .Lfe1:
|
|---|
| 107 | .size setjmp,.Lfe1-setjmp
|
|---|
| 108 |
|
|---|
| 109 | .align 4
|
|---|
| 110 | .global longjmp
|
|---|
| 111 | .type longjmp,@function
|
|---|
| 112 | longjmp:
|
|---|
| 113 |
|
|---|
| 114 | ; load registers
|
|---|
| 115 | ld r13, [r0, ABIr13]
|
|---|
| 116 | ld r14, [r0, ABIr14]
|
|---|
| 117 | ld r15, [r0, ABIr15]
|
|---|
| 118 | ld r16, [r0, ABIr16]
|
|---|
| 119 | ld r17, [r0, ABIr17]
|
|---|
| 120 | ld r18, [r0, ABIr18]
|
|---|
| 121 | ld r19, [r0, ABIr19]
|
|---|
| 122 | ld r20, [r0, ABIr20]
|
|---|
| 123 | ld r21, [r0, ABIr21]
|
|---|
| 124 | ld r22, [r0, ABIr22]
|
|---|
| 125 | ld r23, [r0, ABIr23]
|
|---|
| 126 | ld r24, [r0, ABIr24]
|
|---|
| 127 | ld r25, [r0, ABIr25]
|
|---|
| 128 | ld r26, [r0, ABIr26]
|
|---|
| 129 | ld r27, [r0, ABIr27]
|
|---|
| 130 | ld r28, [r0, ABIr28]
|
|---|
| 131 |
|
|---|
| 132 | ld r3, [r0, ABIr29]
|
|---|
| 133 | mov r29, r3
|
|---|
| 134 |
|
|---|
| 135 | ld r3, [r0, ABIr30]
|
|---|
| 136 | mov r30, r3
|
|---|
| 137 |
|
|---|
| 138 | ld blink, [r0, ABIr31]
|
|---|
| 139 |
|
|---|
| 140 | ld r3, [r0, ABIlpc]
|
|---|
| 141 | mov lp_count, r3
|
|---|
| 142 |
|
|---|
| 143 | ld r2, [r0, ABIlps]
|
|---|
| 144 | ld r3, [r0, ABIlpe]
|
|---|
| 145 | sr r2, [lp_start]
|
|---|
| 146 | sr r3, [lp_end]
|
|---|
| 147 |
|
|---|
| 148 | #if (!defined (__ARC700__) && !defined (__ARCEM__) && !defined (__ARCHS__))
|
|---|
| 149 | ld r2, [r0, ABImlo]
|
|---|
| 150 | ld r3, [r0, ABImhi]
|
|---|
| 151 | ; We do not support restoring of mulhi and mlo registers, yet.
|
|---|
| 152 |
|
|---|
| 153 | ; mulu64 0,r2,1 ; restores mlo
|
|---|
| 154 | ; mov 0,mlo ; force multiply to finish
|
|---|
| 155 | ; sr r3, [mulhi]
|
|---|
| 156 | ld r2, [r0, ABIflg]
|
|---|
| 157 | flag r2 ; restore "status32" register
|
|---|
| 158 | #endif
|
|---|
| 159 |
|
|---|
| 160 | mov.f r1, r1 ; to avoid return 0 from longjmp
|
|---|
| 161 | mov.eq r1, 1
|
|---|
| 162 | j.d [blink]
|
|---|
| 163 | mov r0,r1
|
|---|
| 164 | .Lfe2:
|
|---|
| 165 | .size longjmp,.Lfe2-longjmp
|
|---|
