[444] | 1 | /* |
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| 2 | * Copyright (c) 2015 ARM Ltd |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * 1. Redistributions of source code must retain the above copyright |
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| 9 | * notice, this list of conditions and the following disclaimer. |
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| 10 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 11 | * notice, this list of conditions and the following disclaimer in the |
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| 12 | * documentation and/or other materials provided with the distribution. |
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| 13 | * 3. The name of the company may not be used to endorse or promote |
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| 14 | * products derived from this software without specific prior written |
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| 15 | * permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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| 18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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| 19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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| 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED |
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| 22 | * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
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| 23 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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| 24 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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| 25 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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| 26 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |
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| 29 | .arm |
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| 30 | .syntax unified |
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| 31 | .global __aeabi_memset |
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| 32 | .type __aeabi_memset, %function |
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| 33 | ASM_ALIAS __aeabi_memset4 __aeabi_memset |
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| 34 | ASM_ALIAS __aeabi_memset8 __aeabi_memset |
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| 35 | __aeabi_memset: |
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| 36 | tst r0, #3 |
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| 37 | stmfd sp!, {r4, lr} |
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| 38 | beq 10f |
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| 39 | cmp r1, #0 |
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| 40 | sub r1, r1, #1 |
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| 41 | beq 9f |
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| 42 | and ip, r2, #255 |
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| 43 | mov r3, r0 |
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| 44 | b 2f |
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| 45 | 1: |
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| 46 | cmp r1, #0 |
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| 47 | sub r1, r1, #1 |
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| 48 | beq 9f |
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| 49 | 2: |
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| 50 | strb ip, [r3], #1 |
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| 51 | tst r3, #3 |
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| 52 | bne 1b |
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| 53 | 3: |
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| 54 | cmp r1, #3 |
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| 55 | bls 7f |
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| 56 | and lr, r2, #255 |
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| 57 | orr lr, lr, lr, asl #8 |
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| 58 | cmp r1, #15 |
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| 59 | orr lr, lr, lr, asl #16 |
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| 60 | bls 5f |
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| 61 | mov r4, r1 |
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| 62 | add ip, r3, #16 |
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| 63 | 4: |
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| 64 | sub r4, r4, #16 |
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| 65 | cmp r4, #15 |
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| 66 | str lr, [ip, #-16] |
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| 67 | str lr, [ip, #-12] |
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| 68 | str lr, [ip, #-8] |
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| 69 | str lr, [ip, #-4] |
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| 70 | add ip, ip, #16 |
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| 71 | bhi 4b |
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| 72 | sub ip, r1, #16 |
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| 73 | bic ip, ip, #15 |
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| 74 | and r1, r1, #15 |
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| 75 | add ip, ip, #16 |
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| 76 | cmp r1, #3 |
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| 77 | add r3, r3, ip |
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| 78 | bls 7f |
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| 79 | 5: |
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| 80 | mov r4, r3 |
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| 81 | mov ip, r1 |
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| 82 | 6: |
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| 83 | sub ip, ip, #4 |
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| 84 | cmp ip, #3 |
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| 85 | str lr, [r4], #4 |
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| 86 | bhi 6b |
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| 87 | sub ip, r1, #4 |
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| 88 | bic ip, ip, #3 |
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| 89 | add ip, ip, #4 |
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| 90 | add r3, r3, ip |
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| 91 | and r1, r1, #3 |
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| 92 | 7: |
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| 93 | cmp r1, #0 |
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| 94 | andne r2, r2, #255 |
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| 95 | addne r1, r3, r1 |
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| 96 | beq 9f |
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| 97 | 8: |
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| 98 | strb r2, [r3], #1 |
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| 99 | cmp r3, r1 |
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| 100 | bne 8b |
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| 101 | 9: |
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| 102 | ldmfd sp!, {r4, lr} |
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| 103 | bx lr |
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| 104 | 10: |
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| 105 | mov r3, r0 |
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| 106 | b 3b |
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| 107 | .size __aeabi_memset, . - __aeabi_memset |
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