1 | /* |
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2 | * Copyright (c) 2015 ARM Ltd |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * 1. Redistributions of source code must retain the above copyright |
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9 | * notice, this list of conditions and the following disclaimer. |
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10 | * 2. Redistributions in binary form must reproduce the above copyright |
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11 | * notice, this list of conditions and the following disclaimer in the |
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12 | * documentation and/or other materials provided with the distribution. |
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13 | * 3. The name of the company may not be used to endorse or promote |
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14 | * products derived from this software without specific prior written |
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15 | * permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED |
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22 | * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
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23 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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24 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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25 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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26 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |
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29 | .thumb |
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30 | .syntax unified |
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31 | .global __aeabi_memset |
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32 | .type __aeabi_memset, %function |
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33 | ASM_ALIAS __aeabi_memset4 __aeabi_memset |
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34 | ASM_ALIAS __aeabi_memset8 __aeabi_memset |
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35 | __aeabi_memset: |
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36 | push {r4, r5, r6, lr} |
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37 | lsls r3, r0, #30 |
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38 | beq 10f |
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39 | subs r4, r1, #1 |
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40 | cmp r1, #0 |
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41 | beq 9f |
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42 | lsls r5, r2, #24 |
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43 | lsrs r5, r5, #24 |
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44 | movs r3, r0 |
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45 | movs r6, #3 |
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46 | b 2f |
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47 | 1: |
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48 | subs r1, r4, #1 |
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49 | cmp r4, #0 |
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50 | beq 9f |
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51 | movs r4, r1 |
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52 | 2: |
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53 | adds r3, r3, #1 |
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54 | subs r1, r3, #1 |
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55 | strb r5, [r1] |
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56 | tst r3, r6 |
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57 | bne 1b |
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58 | 3: |
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59 | cmp r4, #3 |
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60 | bls 7f |
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61 | movs r5, #255 |
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62 | ands r5, r2 |
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63 | lsls r1, r5, #8 |
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64 | orrs r5, r1 |
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65 | lsls r1, r5, #16 |
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66 | orrs r5, r1 |
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67 | cmp r4, #15 |
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68 | bls 5f |
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69 | movs r6, r4 |
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70 | subs r6, r6, #16 |
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71 | lsrs r6, r6, #4 |
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72 | adds r6, r6, #1 |
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73 | lsls r6, r6, #4 |
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74 | movs r1, r3 |
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75 | adds r3, r3, r6 |
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76 | 4: |
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77 | str r5, [r1] |
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78 | str r5, [r1, #4] |
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79 | str r5, [r1, #8] |
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80 | str r5, [r1, #12] |
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81 | adds r1, r1, #16 |
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82 | cmp r3, r1 |
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83 | bne 4b |
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84 | movs r1, #15 |
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85 | ands r4, r1 |
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86 | cmp r4, #3 |
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87 | bls 7f |
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88 | 5: |
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89 | subs r6, r4, #4 |
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90 | lsrs r6, r6, #2 |
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91 | adds r6, r6, #1 |
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92 | lsls r6, r6, #2 |
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93 | movs r1, r3 |
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94 | adds r3, r3, r6 |
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95 | 6: |
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96 | stmia r1!, {r5} |
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97 | cmp r3, r1 |
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98 | bne 6b |
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99 | movs r1, #3 |
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100 | ands r4, r1 |
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101 | 7: |
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102 | cmp r4, #0 |
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103 | beq 9f |
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104 | lsls r2, r2, #24 |
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105 | lsrs r2, r2, #24 |
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106 | adds r4, r3, r4 |
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107 | 8: |
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108 | strb r2, [r3] |
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109 | adds r3, r3, #1 |
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110 | cmp r4, r3 |
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111 | bne 8b |
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112 | 9: |
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113 | pop {r4, r5, r6} |
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114 | pop {r1} |
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115 | bx r1 |
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116 | 10: |
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117 | movs r3, r0 |
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118 | movs r4, r1 |
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119 | b 3b |
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120 | .size __aeabi_memset, . - __aeabi_memset |
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