[444] | 1 | /* |
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| 2 | * Copyright (c) 2012-2014 ARM Ltd |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * 1. Redistributions of source code must retain the above copyright |
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| 9 | * notice, this list of conditions and the following disclaimer. |
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| 10 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 11 | * notice, this list of conditions and the following disclaimer in the |
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| 12 | * documentation and/or other materials provided with the distribution. |
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| 13 | * 3. The name of the company may not be used to endorse or promote |
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| 14 | * products derived from this software without specific prior written |
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| 15 | * permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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| 18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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| 19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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| 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED |
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| 22 | * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
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| 23 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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| 24 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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| 25 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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| 26 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |
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| 29 | /* Implementation of strcmp for ARMv6. Use ldrd to support wider |
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| 30 | loads, provided the data is sufficiently aligned. Use |
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| 31 | saturating arithmetic to optimize the compares. */ |
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| 32 | |
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| 33 | /* Build Options: |
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| 34 | STRCMP_NO_PRECHECK: Don't run a quick pre-check of the first |
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| 35 | byte in the string. If comparing completely random strings |
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| 36 | the pre-check will save time, since there is a very high |
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| 37 | probability of a mismatch in the first character: we save |
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| 38 | significant overhead if this is the common case. However, |
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| 39 | if strings are likely to be identical (eg because we're |
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| 40 | verifying a hit in a hash table), then this check is largely |
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| 41 | redundant. */ |
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| 42 | |
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| 43 | .arm |
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| 44 | |
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| 45 | /* Parameters and result. */ |
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| 46 | #define src1 r0 |
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| 47 | #define src2 r1 |
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| 48 | #define result r0 /* Overlaps src1. */ |
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| 49 | |
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| 50 | /* Internal variables. */ |
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| 51 | #define tmp1 r4 |
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| 52 | #define tmp2 r5 |
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| 53 | #define const_m1 r12 |
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| 54 | |
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| 55 | /* Additional internal variables for 64-bit aligned data. */ |
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| 56 | #define data1a r2 |
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| 57 | #define data1b r3 |
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| 58 | #define data2a r6 |
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| 59 | #define data2b r7 |
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| 60 | #define syndrome_a tmp1 |
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| 61 | #define syndrome_b tmp2 |
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| 62 | |
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| 63 | /* Additional internal variables for 32-bit aligned data. */ |
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| 64 | #define data1 r2 |
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| 65 | #define data2 r3 |
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| 66 | #define syndrome tmp2 |
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| 67 | |
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| 68 | |
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| 69 | /* Macro to compute and return the result value for word-aligned |
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| 70 | cases. */ |
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| 71 | .macro strcmp_epilogue_aligned synd d1 d2 restore_r6 |
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| 72 | #ifdef __ARM_BIG_ENDIAN |
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| 73 | /* If data1 contains a zero byte, then syndrome will contain a 1 in |
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| 74 | bit 7 of that byte. Otherwise, the highest set bit in the |
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| 75 | syndrome will highlight the first different bit. It is therefore |
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| 76 | sufficient to extract the eight bits starting with the syndrome |
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| 77 | bit. */ |
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| 78 | clz tmp1, \synd |
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| 79 | lsl r1, \d2, tmp1 |
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| 80 | .if \restore_r6 |
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| 81 | ldrd r6, r7, [sp, #8] |
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| 82 | .endif |
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| 83 | .cfi_restore 6 |
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| 84 | .cfi_restore 7 |
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| 85 | lsl \d1, \d1, tmp1 |
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| 86 | .cfi_remember_state |
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| 87 | lsr result, \d1, #24 |
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| 88 | ldrd r4, r5, [sp], #16 |
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| 89 | .cfi_restore 4 |
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| 90 | .cfi_restore 5 |
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| 91 | sub result, result, r1, lsr #24 |
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| 92 | bx lr |
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| 93 | #else |
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| 94 | /* To use the big-endian trick we'd have to reverse all three words. |
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| 95 | that's slower than this approach. */ |
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| 96 | rev \synd, \synd |
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| 97 | clz tmp1, \synd |
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| 98 | bic tmp1, tmp1, #7 |
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| 99 | lsr r1, \d2, tmp1 |
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| 100 | .cfi_remember_state |
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| 101 | .if \restore_r6 |
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| 102 | ldrd r6, r7, [sp, #8] |
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| 103 | .endif |
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| 104 | .cfi_restore 6 |
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| 105 | .cfi_restore 7 |
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| 106 | lsr \d1, \d1, tmp1 |
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| 107 | and result, \d1, #255 |
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| 108 | and r1, r1, #255 |
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| 109 | ldrd r4, r5, [sp], #16 |
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| 110 | .cfi_restore 4 |
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| 111 | .cfi_restore 5 |
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| 112 | sub result, result, r1 |
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| 113 | |
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| 114 | bx lr |
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| 115 | #endif |
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| 116 | .endm |
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| 117 | |
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| 118 | .text |
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| 119 | .p2align 5 |
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| 120 | .Lstrcmp_start_addr: |
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| 121 | #ifndef STRCMP_NO_PRECHECK |
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| 122 | .Lfastpath_exit: |
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| 123 | sub r0, r2, r3 |
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| 124 | bx lr |
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| 125 | #endif |
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| 126 | def_fn strcmp |
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| 127 | #ifndef STRCMP_NO_PRECHECK |
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| 128 | ldrb r2, [src1] |
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| 129 | ldrb r3, [src2] |
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| 130 | cmp r2, #1 |
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| 131 | cmpcs r2, r3 |
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| 132 | bne .Lfastpath_exit |
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| 133 | #endif |
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| 134 | .cfi_sections .debug_frame |
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| 135 | .cfi_startproc |
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| 136 | strd r4, r5, [sp, #-16]! |
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| 137 | .cfi_def_cfa_offset 16 |
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| 138 | .cfi_offset 4, -16 |
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| 139 | .cfi_offset 5, -12 |
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| 140 | orr tmp1, src1, src2 |
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| 141 | strd r6, r7, [sp, #8] |
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| 142 | .cfi_offset 6, -8 |
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| 143 | .cfi_offset 7, -4 |
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| 144 | mvn const_m1, #0 |
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| 145 | tst tmp1, #7 |
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| 146 | beq .Lloop_aligned8 |
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| 147 | |
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| 148 | .Lnot_aligned: |
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| 149 | eor tmp1, src1, src2 |
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| 150 | tst tmp1, #7 |
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| 151 | bne .Lmisaligned8 |
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| 152 | |
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| 153 | /* Deal with mutual misalignment by aligning downwards and then |
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| 154 | masking off the unwanted loaded data to prevent a difference. */ |
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| 155 | and tmp1, src1, #7 |
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| 156 | bic src1, src1, #7 |
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| 157 | and tmp2, tmp1, #3 |
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| 158 | bic src2, src2, #7 |
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| 159 | lsl tmp2, tmp2, #3 /* Bytes -> bits. */ |
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| 160 | ldrd data1a, data1b, [src1], #16 |
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| 161 | tst tmp1, #4 |
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| 162 | ldrd data2a, data2b, [src2], #16 |
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| 163 | /* In ARM code we can't use ORN, but with do have MVN with a |
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| 164 | register shift. */ |
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| 165 | mvn tmp1, const_m1, S2HI tmp2 |
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| 166 | orr data1a, data1a, tmp1 |
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| 167 | orr data2a, data2a, tmp1 |
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| 168 | beq .Lstart_realigned8 |
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| 169 | orr data1b, data1b, tmp1 |
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| 170 | mov data1a, const_m1 |
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| 171 | orr data2b, data2b, tmp1 |
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| 172 | mov data2a, const_m1 |
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| 173 | b .Lstart_realigned8 |
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| 174 | |
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| 175 | /* Unwind the inner loop by a factor of 2, giving 16 bytes per |
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| 176 | pass. */ |
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| 177 | .p2align 5,,12 /* Don't start in the tail bytes of a cache line. */ |
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| 178 | .p2align 2 /* Always word aligned. */ |
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| 179 | .Lloop_aligned8: |
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| 180 | ldrd data1a, data1b, [src1], #16 |
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| 181 | ldrd data2a, data2b, [src2], #16 |
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| 182 | .Lstart_realigned8: |
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| 183 | uadd8 syndrome_b, data1a, const_m1 /* Only want GE bits, */ |
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| 184 | eor syndrome_a, data1a, data2a |
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| 185 | sel syndrome_a, syndrome_a, const_m1 |
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| 186 | uadd8 syndrome_b, data1b, const_m1 /* Only want GE bits. */ |
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| 187 | eor syndrome_b, data1b, data2b |
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| 188 | sel syndrome_b, syndrome_b, const_m1 |
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| 189 | orrs syndrome_b, syndrome_b, syndrome_a /* Only need if s_a == 0 */ |
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| 190 | bne .Ldiff_found |
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| 191 | |
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| 192 | ldrd data1a, data1b, [src1, #-8] |
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| 193 | ldrd data2a, data2b, [src2, #-8] |
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| 194 | uadd8 syndrome_b, data1a, const_m1 /* Only want GE bits, */ |
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| 195 | eor syndrome_a, data1a, data2a |
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| 196 | sel syndrome_a, syndrome_a, const_m1 |
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| 197 | uadd8 syndrome_b, data1b, const_m1 /* Only want GE bits. */ |
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| 198 | eor syndrome_b, data1b, data2b |
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| 199 | sel syndrome_b, syndrome_b, const_m1 |
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| 200 | orrs syndrome_b, syndrome_b, syndrome_a /* Only need if s_a == 0 */ |
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| 201 | beq .Lloop_aligned8 |
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| 202 | |
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| 203 | .Ldiff_found: |
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| 204 | cmp syndrome_a, #0 |
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| 205 | bne .Ldiff_in_a |
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| 206 | |
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| 207 | .Ldiff_in_b: |
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| 208 | strcmp_epilogue_aligned syndrome_b, data1b, data2b 1 |
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| 209 | |
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| 210 | .Ldiff_in_a: |
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| 211 | .cfi_restore_state |
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| 212 | strcmp_epilogue_aligned syndrome_a, data1a, data2a 1 |
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| 213 | |
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| 214 | .cfi_restore_state |
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| 215 | .Lmisaligned8: |
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| 216 | tst tmp1, #3 |
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| 217 | bne .Lmisaligned4 |
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| 218 | ands tmp1, src1, #3 |
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| 219 | bne .Lmutual_align4 |
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| 220 | |
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| 221 | /* Unrolled by a factor of 2, to reduce the number of post-increment |
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| 222 | operations. */ |
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| 223 | .Lloop_aligned4: |
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| 224 | ldr data1, [src1], #8 |
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| 225 | ldr data2, [src2], #8 |
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| 226 | .Lstart_realigned4: |
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| 227 | uadd8 syndrome, data1, const_m1 /* Only need GE bits. */ |
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| 228 | eor syndrome, data1, data2 |
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| 229 | sel syndrome, syndrome, const_m1 |
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| 230 | cmp syndrome, #0 |
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| 231 | bne .Laligned4_done |
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| 232 | |
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| 233 | ldr data1, [src1, #-4] |
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| 234 | ldr data2, [src2, #-4] |
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| 235 | uadd8 syndrome, data1, const_m1 |
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| 236 | eor syndrome, data1, data2 |
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| 237 | sel syndrome, syndrome, const_m1 |
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| 238 | cmp syndrome, #0 |
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| 239 | beq .Lloop_aligned4 |
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| 240 | |
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| 241 | .Laligned4_done: |
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| 242 | strcmp_epilogue_aligned syndrome, data1, data2, 0 |
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| 243 | |
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| 244 | .Lmutual_align4: |
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| 245 | .cfi_restore_state |
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| 246 | /* Deal with mutual misalignment by aligning downwards and then |
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| 247 | masking off the unwanted loaded data to prevent a difference. */ |
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| 248 | lsl tmp1, tmp1, #3 /* Bytes -> bits. */ |
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| 249 | bic src1, src1, #3 |
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| 250 | ldr data1, [src1], #8 |
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| 251 | bic src2, src2, #3 |
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| 252 | ldr data2, [src2], #8 |
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| 253 | |
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| 254 | /* In ARM code we can't use ORN, but with do have MVN with a |
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| 255 | register shift. */ |
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| 256 | mvn tmp1, const_m1, S2HI tmp1 |
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| 257 | orr data1, data1, tmp1 |
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| 258 | orr data2, data2, tmp1 |
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| 259 | b .Lstart_realigned4 |
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| 260 | |
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| 261 | .Lmisaligned4: |
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| 262 | ands tmp1, src1, #3 |
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| 263 | beq .Lsrc1_aligned |
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| 264 | sub src2, src2, tmp1 |
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| 265 | bic src1, src1, #3 |
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| 266 | lsls tmp1, tmp1, #31 |
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| 267 | ldr data1, [src1], #4 |
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| 268 | beq .Laligned_m2 |
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| 269 | bcs .Laligned_m1 |
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| 270 | |
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| 271 | #ifdef STRCMP_NO_PRECHECK |
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| 272 | ldrb data2, [src2, #1] |
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| 273 | uxtb tmp1, data1, ror #BYTE1_OFFSET |
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| 274 | cmp tmp1, #1 |
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| 275 | cmpcs tmp1, data2 |
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| 276 | bne .Lmisaligned_exit |
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| 277 | |
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| 278 | .Laligned_m2: |
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| 279 | ldrb data2, [src2, #2] |
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| 280 | uxtb tmp1, data1, ror #BYTE2_OFFSET |
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| 281 | cmp tmp1, #1 |
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| 282 | cmpcs tmp1, data2 |
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| 283 | bne .Lmisaligned_exit |
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| 284 | |
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| 285 | .Laligned_m1: |
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| 286 | ldrb data2, [src2, #3] |
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| 287 | uxtb tmp1, data1, ror #BYTE3_OFFSET |
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| 288 | cmp tmp1, #1 |
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| 289 | cmpcs tmp1, data2 |
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| 290 | beq .Lsrc1_aligned |
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| 291 | |
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| 292 | #else /* STRCMP_NO_PRECHECK */ |
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| 293 | /* If we've done the pre-check, then we don't need to check the |
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| 294 | first byte again here. */ |
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| 295 | ldrb data2, [src2, #2] |
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| 296 | uxtb tmp1, data1, ror #BYTE2_OFFSET |
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| 297 | cmp tmp1, #1 |
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| 298 | cmpcs tmp1, data2 |
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| 299 | bne .Lmisaligned_exit |
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| 300 | |
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| 301 | .Laligned_m2: |
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| 302 | ldrb data2, [src2, #3] |
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| 303 | uxtb tmp1, data1, ror #BYTE3_OFFSET |
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| 304 | cmp tmp1, #1 |
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| 305 | cmpcs tmp1, data2 |
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| 306 | beq .Laligned_m1 |
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| 307 | #endif |
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| 308 | |
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| 309 | .Lmisaligned_exit: |
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| 310 | .cfi_remember_state |
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| 311 | sub result, tmp1, data2 |
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| 312 | ldr r4, [sp], #16 |
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| 313 | .cfi_restore 4 |
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| 314 | bx lr |
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| 315 | |
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| 316 | #ifndef STRCMP_NO_PRECHECK |
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| 317 | .Laligned_m1: |
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| 318 | add src2, src2, #4 |
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| 319 | #endif |
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| 320 | .Lsrc1_aligned: |
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| 321 | .cfi_restore_state |
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| 322 | /* src1 is word aligned, but src2 has no common alignment |
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| 323 | with it. */ |
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| 324 | ldr data1, [src1], #4 |
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| 325 | lsls tmp1, src2, #31 /* C=src2[1], Z=src2[0]. */ |
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| 326 | |
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| 327 | bic src2, src2, #3 |
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| 328 | ldr data2, [src2], #4 |
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| 329 | bhi .Loverlap1 /* C=1, Z=0 => src2[1:0] = 0b11. */ |
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| 330 | bcs .Loverlap2 /* C=1, Z=1 => src2[1:0] = 0b10. */ |
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| 331 | |
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| 332 | /* (overlap3) C=0, Z=0 => src2[1:0] = 0b01. */ |
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| 333 | .Loverlap3: |
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| 334 | bic tmp1, data1, #MSB |
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| 335 | uadd8 syndrome, data1, const_m1 |
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| 336 | eors syndrome, tmp1, data2, S2LO #8 |
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| 337 | sel syndrome, syndrome, const_m1 |
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| 338 | bne 4f |
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| 339 | cmp syndrome, #0 |
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| 340 | ldreq data2, [src2], #4 |
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| 341 | bne 5f |
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| 342 | |
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| 343 | eor tmp1, tmp1, data1 |
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| 344 | cmp tmp1, data2, S2HI #24 |
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| 345 | bne 6f |
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| 346 | ldr data1, [src1], #4 |
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| 347 | b .Loverlap3 |
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| 348 | 4: |
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| 349 | S2LO data2, data2, #8 |
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| 350 | b .Lstrcmp_tail |
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| 351 | |
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| 352 | 5: |
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| 353 | bics syndrome, syndrome, #MSB |
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| 354 | bne .Lstrcmp_done_equal |
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| 355 | |
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| 356 | /* We can only get here if the MSB of data1 contains 0, so |
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| 357 | fast-path the exit. */ |
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| 358 | ldrb result, [src2] |
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| 359 | .cfi_remember_state |
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| 360 | ldrd r4, r5, [sp], #16 |
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| 361 | .cfi_restore 4 |
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| 362 | .cfi_restore 5 |
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| 363 | /* R6/7 Not used in this sequence. */ |
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| 364 | .cfi_restore 6 |
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| 365 | .cfi_restore 7 |
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| 366 | neg result, result |
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| 367 | bx lr |
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| 368 | |
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| 369 | 6: |
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| 370 | .cfi_restore_state |
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| 371 | S2LO data1, data1, #24 |
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| 372 | and data2, data2, #LSB |
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| 373 | b .Lstrcmp_tail |
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| 374 | |
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| 375 | .p2align 5,,12 /* Ensure at least 3 instructions in cache line. */ |
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| 376 | .Loverlap2: |
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| 377 | and tmp1, data1, const_m1, S2LO #16 |
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| 378 | uadd8 syndrome, data1, const_m1 |
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| 379 | eors syndrome, tmp1, data2, S2LO #16 |
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| 380 | sel syndrome, syndrome, const_m1 |
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| 381 | bne 4f |
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| 382 | cmp syndrome, #0 |
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| 383 | ldreq data2, [src2], #4 |
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| 384 | bne 5f |
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| 385 | eor tmp1, tmp1, data1 |
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| 386 | cmp tmp1, data2, S2HI #16 |
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| 387 | bne 6f |
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| 388 | ldr data1, [src1], #4 |
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| 389 | b .Loverlap2 |
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| 390 | 4: |
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| 391 | S2LO data2, data2, #16 |
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| 392 | b .Lstrcmp_tail |
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| 393 | 5: |
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| 394 | ands syndrome, syndrome, const_m1, S2LO #16 |
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| 395 | bne .Lstrcmp_done_equal |
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| 396 | |
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| 397 | ldrh data2, [src2] |
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| 398 | S2LO data1, data1, #16 |
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| 399 | #ifdef __ARM_BIG_ENDIAN |
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| 400 | lsl data2, data2, #16 |
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| 401 | #endif |
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| 402 | b .Lstrcmp_tail |
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| 403 | |
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| 404 | 6: |
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| 405 | S2LO data1, data1, #16 |
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| 406 | and data2, data2, const_m1, S2LO #16 |
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| 407 | b .Lstrcmp_tail |
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| 408 | |
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| 409 | .p2align 5,,12 /* Ensure at least 3 instructions in cache line. */ |
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| 410 | .Loverlap1: |
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| 411 | and tmp1, data1, #LSB |
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| 412 | uadd8 syndrome, data1, const_m1 |
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| 413 | eors syndrome, tmp1, data2, S2LO #24 |
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| 414 | sel syndrome, syndrome, const_m1 |
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| 415 | bne 4f |
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| 416 | cmp syndrome, #0 |
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| 417 | ldreq data2, [src2], #4 |
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| 418 | bne 5f |
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| 419 | eor tmp1, tmp1, data1 |
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| 420 | cmp tmp1, data2, S2HI #8 |
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| 421 | bne 6f |
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| 422 | ldr data1, [src1], #4 |
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| 423 | b .Loverlap1 |
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| 424 | 4: |
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| 425 | S2LO data2, data2, #24 |
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| 426 | b .Lstrcmp_tail |
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| 427 | 5: |
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| 428 | tst syndrome, #LSB |
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| 429 | bne .Lstrcmp_done_equal |
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| 430 | ldr data2, [src2] |
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| 431 | 6: |
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| 432 | S2LO data1, data1, #8 |
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| 433 | bic data2, data2, #MSB |
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| 434 | b .Lstrcmp_tail |
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| 435 | |
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| 436 | .Lstrcmp_done_equal: |
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| 437 | mov result, #0 |
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| 438 | .cfi_remember_state |
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| 439 | ldrd r4, r5, [sp], #16 |
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| 440 | .cfi_restore 4 |
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| 441 | .cfi_restore 5 |
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| 442 | /* R6/7 not used in this sequence. */ |
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| 443 | .cfi_restore 6 |
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| 444 | .cfi_restore 7 |
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| 445 | bx lr |
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| 446 | |
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| 447 | .Lstrcmp_tail: |
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| 448 | .cfi_restore_state |
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| 449 | #ifndef __ARM_BIG_ENDIAN |
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| 450 | rev data1, data1 |
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| 451 | rev data2, data2 |
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| 452 | /* Now everything looks big-endian... */ |
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| 453 | #endif |
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| 454 | uadd8 tmp1, data1, const_m1 |
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| 455 | eor tmp1, data1, data2 |
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| 456 | sel syndrome, tmp1, const_m1 |
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| 457 | clz tmp1, syndrome |
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| 458 | lsl data1, data1, tmp1 |
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| 459 | lsl data2, data2, tmp1 |
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| 460 | lsr result, data1, #24 |
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| 461 | ldrd r4, r5, [sp], #16 |
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| 462 | .cfi_restore 4 |
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| 463 | .cfi_restore 5 |
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| 464 | /* R6/7 not used in this sequence. */ |
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| 465 | .cfi_restore 6 |
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| 466 | .cfi_restore 7 |
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| 467 | sub result, result, data2, lsr #24 |
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| 468 | bx lr |
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| 469 | .cfi_endproc |
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| 470 | .size strcmp, . - .Lstrcmp_start_addr |
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