1 | /* |
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2 | * Copyright (c) 2008 ARM Ltd |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * 1. Redistributions of source code must retain the above copyright |
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9 | * notice, this list of conditions and the following disclaimer. |
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10 | * 2. Redistributions in binary form must reproduce the above copyright |
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11 | * notice, this list of conditions and the following disclaimer in the |
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12 | * documentation and/or other materials provided with the distribution. |
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13 | * 3. The name of the company may not be used to endorse or promote |
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14 | * products derived from this software without specific prior written |
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15 | * permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED |
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22 | * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
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23 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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24 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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25 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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26 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |
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29 | #include "arm_asm.h" |
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30 | #include <_ansi.h> |
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31 | #include <string.h> |
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32 | |
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33 | #ifdef __thumb2__ |
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34 | #define magic1(REG) "#0x01010101" |
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35 | #define magic2(REG) "#0x80808080" |
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36 | #else |
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37 | #define magic1(REG) #REG |
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38 | #define magic2(REG) #REG ", lsl #7" |
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39 | #endif |
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40 | |
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41 | char* __attribute__((naked)) |
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42 | strcpy (char* dst, const char* src) |
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43 | { |
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44 | asm ( |
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45 | ".syntax unified\n\t" |
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46 | #if !(defined(__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED) || \ |
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47 | (defined (__thumb__) && !defined (__thumb2__))) |
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48 | #ifdef _ISA_ARM_7 |
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49 | "pld [r1]\n\t" |
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50 | #endif |
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51 | "eor r2, r0, r1\n\t" |
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52 | "mov ip, r0\n\t" |
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53 | "tst r2, #3\n\t" |
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54 | "bne 4f\n\t" |
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55 | "tst r1, #3\n\t" |
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56 | "bne 3f\n" |
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57 | "5:\n\t" |
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58 | #ifndef __thumb2__ |
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59 | "str r5, [sp, #-4]!\n\t" |
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60 | "mov r5, #0x01\n\t" |
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61 | "orr r5, r5, r5, lsl #8\n\t" |
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62 | "orr r5, r5, r5, lsl #16\n\t" |
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63 | #endif |
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64 | |
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65 | "str r4, [sp, #-4]!\n\t" |
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66 | "tst r1, #4\n\t" |
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67 | "ldr r3, [r1], #4\n\t" |
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68 | "beq 2f\n\t" |
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69 | "sub r2, r3, "magic1(r5)"\n\t" |
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70 | "bics r2, r2, r3\n\t" |
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71 | "tst r2, "magic2(r5)"\n\t" |
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72 | "itt eq\n\t" |
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73 | "streq r3, [ip], #4\n\t" |
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74 | "ldreq r3, [r1], #4\n" |
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75 | "bne 1f\n\t" |
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76 | /* Inner loop. We now know that r1 is 64-bit aligned, so we |
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77 | can safely fetch up to two words. This allows us to avoid |
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78 | load stalls. */ |
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79 | ".p2align 2\n" |
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80 | "2:\n\t" |
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81 | #ifdef _ISA_ARM_7 |
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82 | "pld [r1, #8]\n\t" |
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83 | #endif |
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84 | "ldr r4, [r1], #4\n\t" |
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85 | "sub r2, r3, "magic1(r5)"\n\t" |
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86 | "bics r2, r2, r3\n\t" |
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87 | "tst r2, "magic2(r5)"\n\t" |
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88 | "sub r2, r4, "magic1(r5)"\n\t" |
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89 | "bne 1f\n\t" |
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90 | "str r3, [ip], #4\n\t" |
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91 | "bics r2, r2, r4\n\t" |
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92 | "tst r2, "magic2(r5)"\n\t" |
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93 | "itt eq\n\t" |
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94 | "ldreq r3, [r1], #4\n\t" |
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95 | "streq r4, [ip], #4\n\t" |
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96 | "beq 2b\n\t" |
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97 | "mov r3, r4\n" |
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98 | "1:\n\t" |
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99 | #ifdef __ARMEB__ |
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100 | "rors r3, r3, #24\n\t" |
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101 | #endif |
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102 | "strb r3, [ip], #1\n\t" |
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103 | "tst r3, #0xff\n\t" |
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104 | #ifdef __ARMEL__ |
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105 | "ror r3, r3, #8\n\t" |
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106 | #endif |
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107 | "bne 1b\n\t" |
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108 | "ldr r4, [sp], #4\n\t" |
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109 | #ifndef __thumb2__ |
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110 | "ldr r5, [sp], #4\n\t" |
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111 | #endif |
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112 | "bx lr\n" |
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113 | |
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114 | /* Strings have the same offset from word alignment, but it's |
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115 | not zero. */ |
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116 | "3:\n\t" |
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117 | "tst r1, #1\n\t" |
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118 | "beq 1f\n\t" |
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119 | "ldrb r2, [r1], #1\n\t" |
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120 | "strb r2, [ip], #1\n\t" |
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121 | "cmp r2, #0\n\t" |
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122 | "it eq\n" |
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123 | "bxeq lr\n" |
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124 | "1:\n\t" |
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125 | "tst r1, #2\n\t" |
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126 | "beq 5b\n\t" |
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127 | "ldrh r2, [r1], #2\n\t" |
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128 | #ifdef __ARMEB__ |
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129 | "tst r2, #0xff00\n\t" |
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130 | "iteet ne\n\t" |
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131 | "strhne r2, [ip], #2\n\t" |
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132 | "lsreq r2, r2, #8\n\t" |
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133 | "strbeq r2, [ip]\n\t" |
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134 | "tstne r2, #0xff\n\t" |
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135 | #else |
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136 | "tst r2, #0xff\n\t" |
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137 | "itet ne\n\t" |
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138 | "strhne r2, [ip], #2\n\t" |
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139 | "strbeq r2, [ip]\n\t" |
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140 | "tstne r2, #0xff00\n\t" |
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141 | #endif |
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142 | "bne 5b\n\t" |
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143 | "bx lr\n" |
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144 | |
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145 | /* src and dst do not have a common word-alignement. Fall back to |
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146 | byte copying. */ |
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147 | "4:\n\t" |
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148 | "ldrb r2, [r1], #1\n\t" |
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149 | "strb r2, [ip], #1\n\t" |
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150 | "cmp r2, #0\n\t" |
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151 | "bne 4b\n\t" |
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152 | "bx lr\n\t" |
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153 | |
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154 | #elif !defined (__thumb__) || defined (__thumb2__) |
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155 | "mov r3, r0\n\t" |
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156 | "1:\n\t" |
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157 | "ldrb r2, [r1], #1\n\t" |
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158 | "strb r2, [r3], #1\n\t" |
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159 | "cmp r2, #0\n\t" |
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160 | "bne 1b\n\t" |
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161 | "bx lr\n\t" |
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162 | #else |
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163 | "movs r3, r0\n\t" |
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164 | "1:\n\t" |
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165 | "ldrb r2, [r1]\n\t" |
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166 | "adds r1, #1\n\t" |
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167 | "strb r2, [r3]\n\t" |
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168 | "adds r3, #1\n\t" |
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169 | "cmp r2, #0\n\t" |
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170 | "bne 1b\n\t" |
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171 | "bx lr\n\t" |
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172 | #endif |
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173 | ); |
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174 | } |
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