1 | ; |
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2 | ; (c) Copyright 1986 HEWLETT-PACKARD COMPANY |
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3 | ; |
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4 | ; To anyone who acknowledges that this file is provided "AS IS" |
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5 | ; without any express or implied warranty: |
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6 | ; permission to use, copy, modify, and distribute this file |
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7 | ; for any purpose is hereby granted without fee, provided that |
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8 | ; the above copyright notice and this notice appears in all |
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9 | ; copies, and that the name of Hewlett-Packard Company not be |
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10 | ; used in advertising or publicity pertaining to distribution |
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11 | ; of the software without specific, written prior permission. |
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12 | ; Hewlett-Packard Company makes no representations about the |
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13 | ; suitability of this software for any purpose. |
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14 | ; |
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15 | |
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16 | ; Standard Hardware Register Definitions for Use with Assembler |
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17 | ; version A.08.06 |
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18 | ; - fr16-31 added at Utah |
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19 | ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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20 | ; Hardware General Registers |
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21 | r0: .equ 0 |
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22 | |
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23 | r1: .equ 1 |
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24 | |
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25 | r2: .equ 2 |
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26 | |
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27 | r3: .equ 3 |
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28 | |
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29 | r4: .equ 4 |
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30 | |
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31 | r5: .equ 5 |
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32 | |
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33 | r6: .equ 6 |
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34 | |
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35 | r7: .equ 7 |
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36 | |
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37 | r8: .equ 8 |
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38 | |
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39 | r9: .equ 9 |
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40 | |
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41 | r10: .equ 10 |
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42 | |
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43 | r11: .equ 11 |
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44 | |
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45 | r12: .equ 12 |
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46 | |
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47 | r13: .equ 13 |
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48 | |
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49 | r14: .equ 14 |
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50 | |
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51 | r15: .equ 15 |
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52 | |
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53 | r16: .equ 16 |
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54 | |
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55 | r17: .equ 17 |
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56 | |
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57 | r18: .equ 18 |
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58 | |
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59 | r19: .equ 19 |
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60 | |
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61 | r20: .equ 20 |
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62 | |
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63 | r21: .equ 21 |
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64 | |
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65 | r22: .equ 22 |
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66 | |
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67 | r23: .equ 23 |
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68 | |
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69 | r24: .equ 24 |
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70 | |
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71 | r25: .equ 25 |
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72 | |
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73 | r26: .equ 26 |
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74 | |
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75 | r27: .equ 27 |
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76 | |
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77 | r28: .equ 28 |
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78 | |
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79 | r29: .equ 29 |
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80 | |
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81 | r30: .equ 30 |
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82 | |
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83 | r31: .equ 31 |
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84 | |
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85 | ; Hardware Space Registers |
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86 | sr0: .equ 0 |
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87 | |
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88 | sr1: .equ 1 |
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89 | |
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90 | sr2: .equ 2 |
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91 | |
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92 | sr3: .equ 3 |
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93 | |
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94 | sr4: .equ 4 |
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95 | |
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96 | sr5: .equ 5 |
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97 | |
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98 | sr6: .equ 6 |
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99 | |
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100 | sr7: .equ 7 |
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101 | |
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102 | ; Hardware Floating Point Registers |
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103 | fr0: .equ 0 |
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104 | |
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105 | fr1: .equ 1 |
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106 | |
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107 | fr2: .equ 2 |
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108 | |
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109 | fr3: .equ 3 |
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110 | |
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111 | fr4: .equ 4 |
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112 | |
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113 | fr5: .equ 5 |
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114 | |
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115 | fr6: .equ 6 |
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116 | |
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117 | fr7: .equ 7 |
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118 | |
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119 | fr8: .equ 8 |
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120 | |
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121 | fr9: .equ 9 |
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122 | |
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123 | fr10: .equ 10 |
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124 | |
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125 | fr11: .equ 11 |
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126 | |
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127 | fr12: .equ 12 |
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128 | |
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129 | fr13: .equ 13 |
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130 | |
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131 | fr14: .equ 14 |
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132 | |
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133 | fr15: .equ 15 |
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134 | |
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135 | fr16: .equ 16 |
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136 | |
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137 | fr17: .equ 17 |
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138 | |
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139 | fr18: .equ 18 |
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140 | |
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141 | fr19: .equ 19 |
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142 | |
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143 | fr20: .equ 20 |
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144 | |
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145 | fr21: .equ 21 |
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146 | |
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147 | fr22: .equ 22 |
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148 | |
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149 | fr23: .equ 23 |
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150 | |
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151 | fr24: .equ 24 |
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152 | |
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153 | fr25: .equ 25 |
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154 | |
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155 | fr26: .equ 26 |
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156 | |
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157 | fr27: .equ 27 |
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158 | |
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159 | fr28: .equ 28 |
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160 | |
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161 | fr29: .equ 29 |
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162 | |
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163 | fr30: .equ 30 |
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164 | |
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165 | fr31: .equ 31 |
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166 | |
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167 | ; Hardware Control Registers |
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168 | cr0: .equ 0 |
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169 | |
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170 | rctr: .equ 0 ; Recovery Counter Register |
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171 | |
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172 | |
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173 | cr8: .equ 8 ; Protection ID 1 |
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174 | |
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175 | pidr1: .equ 8 |
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176 | |
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177 | |
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178 | cr9: .equ 9 ; Protection ID 2 |
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179 | |
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180 | pidr2: .equ 9 |
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181 | |
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182 | |
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183 | cr10: .equ 10 |
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184 | |
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185 | ccr: .equ 10 ; Coprocessor Confiquration Register |
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186 | |
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187 | |
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188 | cr11: .equ 11 |
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189 | |
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190 | sar: .equ 11 ; Shift Amount Register |
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191 | |
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192 | |
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193 | cr12: .equ 12 |
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194 | |
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195 | pidr3: .equ 12 ; Protection ID 3 |
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196 | |
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197 | |
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198 | cr13: .equ 13 |
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199 | |
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200 | pidr4: .equ 13 ; Protection ID 4 |
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201 | |
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202 | |
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203 | cr14: .equ 14 |
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204 | |
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205 | iva: .equ 14 ; Interrupt Vector Address |
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206 | |
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207 | |
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208 | cr15: .equ 15 |
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209 | |
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210 | eiem: .equ 15 ; External Interrupt Enable Mask |
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211 | |
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212 | |
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213 | cr16: .equ 16 |
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214 | |
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215 | itmr: .equ 16 ; Interval Timer |
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216 | |
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217 | |
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218 | cr17: .equ 17 |
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219 | |
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220 | pcsq: .equ 17 ; Program Counter Space queue |
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221 | |
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222 | |
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223 | cr18: .equ 18 |
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224 | |
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225 | pcoq: .equ 18 ; Program Counter Offset queue |
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226 | |
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227 | |
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228 | cr19: .equ 19 |
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229 | |
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230 | iir: .equ 19 ; Interruption Instruction Register |
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231 | |
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232 | |
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233 | cr20: .equ 20 |
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234 | |
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235 | isr: .equ 20 ; Interruption Space Register |
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236 | |
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237 | |
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238 | cr21: .equ 21 |
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239 | |
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240 | ior: .equ 21 ; Interruption Offset Register |
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241 | |
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242 | |
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243 | cr22: .equ 22 |
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244 | |
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245 | ipsw: .equ 22 ; Interrpution Processor Status Word |
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246 | |
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247 | |
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248 | cr23: .equ 23 |
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249 | |
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250 | eirr: .equ 23 ; External Interrupt Request |
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251 | |
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252 | |
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253 | cr24: .equ 24 |
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254 | |
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255 | ppda: .equ 24 ; Physcial Page Directory Address |
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256 | |
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257 | tr0: .equ 24 ; Temporary register 0 |
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258 | |
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259 | |
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260 | cr25: .equ 25 |
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261 | |
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262 | hta: .equ 25 ; Hash Table Address |
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263 | |
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264 | tr1: .equ 25 ; Temporary register 1 |
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265 | |
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266 | |
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267 | cr26: .equ 26 |
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268 | |
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269 | tr2: .equ 26 ; Temporary register 2 |
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270 | |
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271 | |
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272 | cr27: .equ 27 |
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273 | |
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274 | tr3: .equ 27 ; Temporary register 3 |
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275 | |
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276 | |
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277 | cr28: .equ 28 |
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278 | |
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279 | tr4: .equ 28 ; Temporary register 4 |
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280 | |
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281 | |
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282 | cr29: .equ 29 |
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283 | |
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284 | tr5: .equ 29 ; Temporary register 5 |
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285 | |
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286 | |
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287 | cr30: .equ 30 |
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288 | |
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289 | tr6: .equ 30 ; Temporary register 6 |
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290 | |
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291 | |
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292 | cr31: .equ 31 |
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293 | |
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294 | tr7: .equ 31 ; Temporary register 7 |
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295 | |
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296 | ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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297 | ; Procedure Call Convention ~ |
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298 | ; Register Definitions for Use with Assembler ~ |
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299 | ; version A.08.06 |
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300 | ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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301 | ; Software Architecture General Registers |
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302 | rp: .equ r2 ; return pointer |
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303 | |
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304 | mrp: .equ r31 ; millicode return pointer |
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305 | |
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306 | ret0: .equ r28 ; return value |
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307 | |
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308 | ret1: .equ r29 ; return value (high part of double) |
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309 | |
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310 | sl: .equ r29 ; static link |
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311 | |
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312 | sp: .equ r30 ; stack pointer |
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313 | |
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314 | dp: .equ r27 ; data pointer |
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315 | |
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316 | arg0: .equ r26 ; argument |
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317 | |
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318 | arg1: .equ r25 ; argument or high part of double argument |
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319 | |
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320 | arg2: .equ r24 ; argument |
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321 | |
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322 | arg3: .equ r23 ; argument or high part of double argument |
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323 | |
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324 | ;_____________________________________________________________________________ |
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325 | ; Software Architecture Space Registers |
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326 | ; sr0 ; return link form BLE |
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327 | sret: .equ sr1 ; return value |
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328 | |
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329 | sarg: .equ sr1 ; argument |
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330 | |
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331 | ; sr4 ; PC SPACE tracker |
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332 | ; sr5 ; process private data |
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333 | ;_____________________________________________________________________________ |
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334 | ; Software Architecture Pseudo Registers |
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335 | previous_sp: .equ 64 ; old stack pointer (locates previous frame) |
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336 | |
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337 | #if 0 |
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338 | ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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339 | ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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340 | ; Standard space and subspace definitions. version A.08.06 |
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341 | ; These are generally suitable for programs on HP_UX and HPE. |
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342 | ; Statements commented out are used when building such things as operating |
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343 | ; system kernels. |
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344 | ;;;;;;;;;;;;;;;; |
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345 | .SPACE $TEXT$, SPNUM=0,SORT=8 |
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346 | ; .subspa $FIRST$, QUAD=0,ALIGN=2048,ACCESS=0x2c,SORT=4,FIRST |
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347 | ; .subspa $REAL$, QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=4,FIRST,LOCK |
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348 | .subspa $MILLICODE$, QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=8 |
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349 | .subspa $LIT$, QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=16 |
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350 | .subspa $CODE$, QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=24 |
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351 | ; .subspa $UNWIND$, QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=64 |
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352 | ; .subspa $RECOVER$, QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=80 |
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353 | ; .subspa $RESERVED$, QUAD=0,ALIGN=8,ACCESS=0x73,SORT=82 |
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354 | ; .subspa $GATE$, QUAD=0,ALIGN=8,ACCESS=0x4c,SORT=84,CODE_ONLY |
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355 | ; Additional code subspaces should have ALIGN=8 for an interspace BV |
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356 | ; and should have SORT=24. |
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357 | ; |
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358 | ; For an incomplete executable (program bound to shared libraries), |
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359 | ; sort keys $GLOBAL$ -1 and $GLOBAL$ -2 are reserved for the $DLT$ |
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360 | ; and $PLT$ subspaces respectively. |
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361 | ;;;;;;;;;;;;;;; |
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362 | .SPACE $PRIVATE$, SPNUM=1,PRIVATE,SORT=16 |
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363 | .subspa $GLOBAL$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=40 |
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364 | .import $global$ |
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365 | .subspa $SHORTDATA$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=24 |
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366 | .subspa $DATA$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=16 |
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367 | .subspa $PFA_COUNTER$, QUAD=1,ALIGN=4,ACCESS=0x1f,SORT=8 |
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368 | .subspa $SHORTBSS$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=80,ZERO |
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369 | .subspa $BSS$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=82,ZERO |
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370 | ; .subspa $PCB$, QUAD=1,ALIGN=8,ACCESS=0x10,SORT=82 |
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371 | ; .subspa $STACK$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=82 |
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372 | ; .subspa $HEAP$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=82 |
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373 | ;;;;;;;;;;;;;;;; |
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374 | ; .SPACE $PFA$, SPNUM=0,PRIVATE,UNLOADABLE,SORT=64 |
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375 | ; .subspa $PFA_ADDRESS$, ALIGN=4,ACCESS=0x2c,UNLOADABLE |
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376 | ;;;;;;;;;;;;;;;; |
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377 | ; .SPACE $DEBUG$, SPNUM=2,PRIVATE,UNLOADABLE,SORT=80 |
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378 | ; .subspa $HEADER$, ALIGN=4,ACCESS=0,UNLOADABLE,FIRST |
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379 | ; .subspa $GNTT$, ALIGN=4,ACCESS=0,UNLOADABLE |
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380 | ; .subspa $LNTT$, ALIGN=4,ACCESS=0,UNLOADABLE |
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381 | ; .subspa $SLT$, ALIGN=4,ACCESS=0,UNLOADABLE |
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382 | ; .subspa $VT$, ALIGN=4,ACCESS=0,UNLOADABLE |
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383 | |
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384 | ; To satisfy the copyright terms each .o will have a reference |
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385 | ; the the actual copyright. This will force the actual copyright |
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386 | ; message to be brought in from libgloss/hp-milli.s |
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387 | .space $PRIVATE$ |
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388 | .subspa $DATA$ |
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389 | #else |
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390 | .data |
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391 | #endif |
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392 | .import ___hp_free_copyright,data |
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393 | L$copyright .word ___hp_free_copyright |
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