[1] | 1 | /////////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File : boot_bdv_driver.c |
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| 3 | // Date : 18/01/2017 |
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| 4 | // Author : Alain Greiner / Vu Son |
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| 5 | // Copyright (c) UPMC-LIP6 |
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| 6 | /////////////////////////////////////////////////////////////////////////////////// |
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| 7 | |
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| 8 | #include <boot_config.h> |
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| 9 | #include <boot_bdv_driver.h> |
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| 10 | #include <boot_mmc_driver.h> |
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| 11 | #include <boot_utils.h> |
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| 12 | |
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| 13 | #ifndef SEG_IOC_BASE |
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[6] | 14 | # error "The SEG_IOC_BASE value should be defined in the 'hard_config.h' file" |
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[1] | 15 | #endif |
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| 16 | |
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[6] | 17 | #ifndef X_IO |
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| 18 | # error "The X_IO value should be defined in the 'hard_config.h' file" |
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[1] | 19 | #endif |
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| 20 | |
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[6] | 21 | #ifndef Y_IO |
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| 22 | # error "The Y_IO value should be defined in the 'hard_config.h' file" |
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| 23 | #endif |
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[1] | 24 | |
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[6] | 25 | #ifndef Y_WIDTH |
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| 26 | # error "The Y_WIDTH value should be defined in the 'hard_config.h' file" |
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| 27 | #endif |
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| 28 | |
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| 29 | |
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[1] | 30 | /**************************************************************************** |
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| 31 | * Internal functions. * |
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| 32 | ****************************************************************************/ |
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| 33 | |
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| 34 | /**************************************************************************** |
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| 35 | * This function returns the value of a BDV register. * |
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| 36 | * @ reg : BDV register to be read. * |
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| 37 | * @ returns the value stored in 'reg'. * |
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| 38 | ****************************************************************************/ |
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| 39 | static uint32_t boot_bdv_get_register( uint32_t reg ) |
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| 40 | { |
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[6] | 41 | cxy_t cxy = (X_IO << Y_WIDTH) + Y_IO; |
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[1] | 42 | uint32_t * ptr = (uint32_t *)SEG_IOC_BASE + reg; |
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| 43 | |
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| 44 | return boot_remote_lw( XPTR( cxy , ptr ) ); |
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| 45 | |
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| 46 | } // boot_bdv_get_register() |
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| 47 | |
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| 48 | /**************************************************************************** |
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| 49 | * This function set a new value to a BDV register. * |
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| 50 | * @ reg : BDV register to be configured. * |
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| 51 | * @ val : new value to be written. * |
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| 52 | ****************************************************************************/ |
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| 53 | static void boot_bdv_set_register( uint32_t reg, |
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| 54 | uint32_t val ) |
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| 55 | { |
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[6] | 56 | cxy_t cxy = (X_IO << Y_WIDTH) + Y_IO; |
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[1] | 57 | uint32_t * ptr = (uint32_t *)SEG_IOC_BASE + reg; |
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| 58 | |
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| 59 | boot_remote_sw( XPTR( cxy , ptr ) , val ); |
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| 60 | |
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| 61 | } // boot_bdv_set_register() |
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| 62 | |
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| 63 | /**************************************************************************** |
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| 64 | * Driver API functions. * |
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| 65 | ****************************************************************************/ |
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| 66 | |
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| 67 | /////////////////// |
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| 68 | int boot_bdv_init() |
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| 69 | { |
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| 70 | // Check block size |
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| 71 | if (boot_bdv_get_register(BDV_BLOCK_SIZE) != 512) |
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| 72 | { |
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| 73 | boot_puts("\n[BOOT ERROR] boot_bdv_init(): " |
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| 74 | "Block size must be 512 bytes\n"); |
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| 75 | return -1; |
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| 76 | } |
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| 77 | |
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| 78 | // Disable IRQq |
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| 79 | boot_bdv_set_register(BDV_IRQ_ENABLE, 0); |
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| 80 | |
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| 81 | return 0; |
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| 82 | |
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| 83 | } // boot_bdv_init() |
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| 84 | |
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| 85 | //////////////////////////////////// |
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| 86 | int boot_bdv_access( uint32_t lba, |
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| 87 | xptr_t buf_paddr, |
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| 88 | uint32_t count) |
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| 89 | { |
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| 90 | uint32_t error; |
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| 91 | uint32_t status; |
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| 92 | |
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| 93 | // get target buffer cluster and pointer |
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| 94 | cxy_t buf_cxy = GET_CXY( buf_paddr ); |
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| 95 | uint32_t buf_ptr = (uint32_t)GET_PTR( buf_paddr ); |
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| 96 | |
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| 97 | // Check buffer address alignment |
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| 98 | if (buf_ptr & 0x3F) |
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| 99 | { |
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| 100 | boot_puts("\n[BOOT ERROR] boot_bdv_access(): " |
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| 101 | "Buffer address is not cache-line-size-aligned\n"); |
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| 102 | return -1; |
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| 103 | } |
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| 104 | |
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| 105 | // Set BDV device registers |
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| 106 | boot_bdv_set_register(BDV_BUFFER , buf_ptr ); |
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| 107 | boot_bdv_set_register(BDV_BUFFER_EXT, buf_cxy ); |
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| 108 | boot_bdv_set_register(BDV_COUNT , count ); |
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| 109 | boot_bdv_set_register(BDV_LBA , lba ); |
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| 110 | |
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| 111 | #if USE_IOB // software L2/L3 cache coherence |
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| 112 | if( boot_mmc_inval( buf_paddr, count<<9 ) ) return -1; |
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| 113 | #endif |
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| 114 | |
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| 115 | // Launch data transfer |
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| 116 | boot_bdv_set_register(BDV_OPERATION, BDV_READ); |
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| 117 | |
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| 118 | #if DEBUG_BOOT_IOC |
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| 119 | boot_printf("\n[BOOT] boot_bdv_access(): Transfer launched at cycle %d\n" |
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| 120 | " lba = %d / buf = %l / nblocks = %d\n", |
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| 121 | boot_get_proctime() , lba , buf_paddr , count ); |
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| 122 | #endif |
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| 123 | |
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| 124 | // Wait transfer completion |
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| 125 | do |
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| 126 | { |
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| 127 | status = boot_bdv_get_register(BDV_STATUS); |
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| 128 | |
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| 129 | } while ((status != BDV_READ_SUCC ) && |
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| 130 | (status != BDV_READ_ERR ) && |
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| 131 | (status != BDV_WRITE_SUCC) && |
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| 132 | (status != BDV_WRITE_ERR )); |
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| 133 | |
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| 134 | #if DEBUG_BOOT_IOC |
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| 135 | boot_printf("\n[BOOT] boot_bdv_access(): Transfer terminated at cycle %d\n", |
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| 136 | boot_get_proctime() ); |
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| 137 | |
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| 138 | // uint32_t * data = (uint32_t *)(uint32_t)buf_paddr; |
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| 139 | // uint32_t line; |
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| 140 | // uint32_t word; |
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| 141 | // boot_printf("\n"); |
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| 142 | // for( line = 0 ; line < 16 ; line++ ) |
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| 143 | // { |
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| 144 | // for( word = 0 ; word < 8 ; word++ ) |
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| 145 | // { |
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| 146 | // boot_printf(" | %x", data[line*8+word] ); |
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| 147 | // } |
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| 148 | // boot_printf(" |\n"); |
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| 149 | // } |
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| 150 | |
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| 151 | #endif |
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| 152 | |
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| 153 | // Check error |
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| 154 | error = ((status == BDV_READ_ERR) || |
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| 155 | (status == BDV_WRITE_ERR)); |
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| 156 | |
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| 157 | return error; |
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| 158 | |
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| 159 | } // boot_bdv_access() |
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