Index: trunk/hal/tsar_mips32/core/hal_context.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_context.c	(revision 151)
+++ trunk/hal/tsar_mips32/core/hal_context.c	(revision 296)
@@ -43,27 +43,54 @@
 
 /////////////////////////////////////////////////////////////////////////////////////////
-// This structure defines the cpu_context for TSAR MIPS32.
+// These structuree defines the cpu_context anf fpu_context for TSAR MIPS32.
 // These registers are saved/restored at each context switch.
-// WARNING : update the hal_cpu_context_save() and hal_cpu_context_restore()
-//           functions when modifying this structure. 
+// WARNING : update the hal_***_context_save() and hal_***_context_restore()
+//           functions when modifying this structure, and check the two
+//           CONFIG_CPU_CTX_SIZE & CONFIGFPU_CTX_SIZE configuration parameterss. 
 /////////////////////////////////////////////////////////////////////////////////////////
 
 typedef struct hal_cpu_context_s
 {
-	uint32_t s0_16;      // slot 0
-	uint32_t s1_17;      // slot 1
-	uint32_t s2_18;      // slot 2
-	uint32_t s3_19;      // slot 3
-	uint32_t s4_20;      // slot 4
-	uint32_t s5_21;      // slot 5
-	uint32_t s6_22;      // slot 6
-	uint32_t s7_23;      // slot 7
-	uint32_t sp_29;      // slot 8
-	uint32_t fp_30;      // slot 9
-	uint32_t ra_31;      // slot 10
-	uint32_t c0_sr;      // slot 11
-	uint32_t c0_th;      // slot 12
-	uint32_t c2_ptpr;    // slot 13
-	uint32_t c2_mode;    // slot 14
+    uint32_t c0_epc;     // slot 0
+    uint32_t at_01;      // slot 1
+    uint32_t v0_02;      // slot 2
+    uint32_t v1_03;      // slot 3
+    uint32_t a0_04;      // slot 4
+    uint32_t a1_05;      // slot 5
+    uint32_t a2_06;      // slot 6
+    uint32_t a3_07;      // slot 7
+
+    uint32_t t0_08;      // slot 8
+    uint32_t t1_09;      // slot 9
+    uint32_t t2_10;      // slot 10
+    uint32_t t3_11;      // slot 11
+    uint32_t t4_12;      // slot 12
+    uint32_t t5_13;      // slot 13
+    uint32_t t6_14;      // slot 14
+    uint32_t t7_15;      // slot 15
+
+	uint32_t s0_16;      // slot 16
+	uint32_t s1_17;      // slot 17
+	uint32_t s2_18;      // slot 18
+	uint32_t s3_19;      // slot 19
+	uint32_t s4_20;      // slot 20
+	uint32_t s5_21;      // slot 21
+	uint32_t s6_22;      // slot 22
+	uint32_t s7_23;      // slot 23
+
+    uint32_t t8_24;      // slot 24
+    uint32_t t8_25;      // slot 25
+    uint32_t hi_26;      // slot 26
+    uint32_t lo_27;      // slot 27
+    uint32_t gp_28;      // slot 28
+	uint32_t sp_29;      // slot 29
+	uint32_t fp_30;      // slot 30
+	uint32_t ra_31;      // slot 31
+
+	uint32_t c2_ptpr;    // slot 32
+	uint32_t c2_mode;    // slot 33
+
+	uint32_t c0_sr;      // slot 34
+	uint32_t c0_th;      // slot 35
 } 
 hal_cpu_context_t;
@@ -79,6 +106,18 @@
 hal_fpu_context_t;
 
-//////////////////////////////////////////////////////////
-error_t hal_cpu_context_create( struct thread_s * thread )
+
+
+/////////////////////////////////////////////////////////////////////////////////////////
+//        CPU context access functions
+/////////////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////////////////
+// Seven registers are initialised by this function:
+// GPR : sp_29 / fp_30 / ra_31
+// CP0 : c0_sr / c0_th
+// CP2 : c2_ptpr / c2_mode
+/////////////////////////////////////////////////////////////////////////////////////////
+error_t hal_cpu_context_create( thread_t * thread )
 {
     kmem_req_t  req;
@@ -127,9 +166,174 @@
 	context->c2_mode    = c2_mode;
 
-    context_dmsg("\n[INFO] %s : exit for thread %x in process %x\n",
-                 __FUNCTION__ , thread->trdid , thread->process->pid );
+    context_dmsg("\n[INFO] %s : exit for thread %x in process %x / ra = %x\n",
+                 __FUNCTION__ , thread->trdid , thread->process->pid , context->ra_31 );
 
     return 0;
 }  // end hal_cpu_context_create()
+
+/////////////////////////////////////////////////
+void hal_cpu_context_display( thread_t * thread )
+{
+    hal_cpu_context_t * ctx = (hal_cpu_context_t *)thread->cpu_context;
+
+    printk("\n*** cpu_context for thread %x in cluster %x / ctx = %x ***\n" 
+           " gp_28   = %X    sp_29   = %X    ra_31   = %X\n" 
+           " c0_sr   = %X    c0_epc  = %X    c0_th = %X\n"
+           " c2_ptpr = %X    c2_mode = %X\n",
+           thread->trdid, local_cxy, ctx,
+           ctx->gp_28   , ctx->sp_29   , ctx->ra_31,
+           ctx->c0_sr   , ctx->c0_epc  , ctx->c0_th,
+           ctx->c2_ptpr , ctx->c2_mode );
+}
+
+/////////////////////////////////////////////////////////////////////////////////////////
+// These registers are saved to CPU context defined by <ctx> argument.
+// - GPR : all, but (zero, k0, k1), plus (hi, lo)
+// - CP0 : c0_th , c0_sr 
+// - CP2 : c2_ptpr , C2_mode, C2_epc
+/////////////////////////////////////////////////////////////////////////////////////////
+void hal_cpu_context_save( void * ctx )
+{
+    asm volatile(
+    ".set noat                     \n"
+    ".set noreorder                \n"
+    "move    $26,   $4             \n"   /* $26 <= &ctx */
+
+    "mfc0    $27,   $14            \n"
+    "sw      $27,   0*4($26)       \n"   /* save c0_epc to slot 0 */
+ 
+    "sw      $1,    1*4($26)       \n"
+    "sw      $2,    2*4($26)       \n"
+    "sw      $3,    3*4($26)       \n"
+    "sw      $4,    4*4($26)       \n"
+    "sw      $5,    5*4($26)       \n"
+    "sw      $6,    6*4($26)       \n"
+    "sw      $7,    7*4($26)       \n"
+
+    "sw      $8,    8*4($26)       \n"
+    "sw      $9,    9*4($26)       \n"
+    "sw      $10,  10*4($26)       \n"
+    "sw      $11,  11*4($26)       \n"
+    "sw      $12,  12*4($26)       \n"
+    "sw      $13,  13*4($26)       \n"
+    "sw      $14,  14*4($26)       \n"
+    "sw      $15,  15*4($26)       \n"
+
+    "sw      $16,  16*4($26)       \n"
+    "sw      $17,  17*4($26)       \n"
+    "sw      $18,  18*4($26)       \n"
+    "sw      $19,  19*4($26)       \n"
+    "sw      $20,  20*4($26)       \n"
+    "sw      $21,  21*4($26)       \n"
+    "sw      $22,  22*4($26)       \n"
+    "sw      $23,  23*4($26)       \n"
+
+    "sw      $24,  24*4($26)       \n"
+    "sw      $25,  25*4($26)       \n"
+
+    "mfhi    $27                   \n"
+    "sw      $27,  26*4($26)       \n"   /* save hi to slot 26 */
+    "mflo    $27                   \n"
+    "sw      $27,  27*4($26)       \n"   /* save lo to slot 27 */
+
+    "sw      $28,  28*4($26)       \n"
+    "sw      $29,  29*4($26)       \n"
+    "sw      $30,  30*4($26)       \n"
+    "sw      $31,  31*4($26)       \n"
+
+	"mfc2    $27,  $0              \n"
+	"sw      $27,  32*4($26)       \n"   /* save c2_ptpr to slot 32 */
+	"mfc2    $27,  $1              \n"
+	"sw      $27,  33*4($26)       \n"   /* save c2_mode to slot 33 */
+
+    "mfc0	 $27,  $12             \n"
+	"sw      $27,  34*4($26)       \n"   /* save c0_sr to slot 34 */
+    "mfc0	 $27,  $4, 2           \n"
+	"sw      $27,  35*4($26)       \n"   /* save c0_th to slot 35 */
+
+    "sync                          \n"
+
+    "move    $4,   $27               \n"
+    "jal     hal_cpu_context_display \n"    /* display context */
+    "nop                             \n"
+
+	".set reorder                  \n"
+    ".set at                       \n"
+    : : : "$26" , "$27" , "memory" ); 
+}
+
+/////////////////////////////////////////////////////////////////////////////////////////
+// These registers are restored from cpu context defined by <ctx> argument:
+// - GPR : all, but (zero, k0, k1), plus (hi, lo)
+// - CP0 : c0_th , c0_sr
+// - CP2 : c2_ptpr , C2_mode
+/////////////////////////////////////////////////////////////////////////////////////////
+void hal_cpu_context_restore( void * ctx )
+{
+    asm volatile(
+    ".set noat                     \n"
+    ".set noreorder                \n"
+    "move    $26,   $4             \n"   /* $26 <= &ctx */
+
+    "lw      $4,   35*4($26)         \n"
+    "jal     hal_cpu_context_display \n"    /* display context */ 
+    "nop                             \n"
+
+    "lw      $27,   0*4($26)       \n"
+    "mtc0    $27,   $14            \n"   /* restore C0_epc from slot 0 */
+
+    "lw      $1,    1*4($26)       \n"
+    "lw      $2,    2*4($26)       \n"
+    "lw      $3,    3*4($26)       \n"
+    "lw      $4,    4*4($26)       \n"
+    "lw      $5,    5*4($26)       \n"
+    "lw      $6,    6*4($26)       \n"
+    "lw      $7,    7*4($26)       \n"
+
+    "lw      $8,    8*4($26)       \n"
+    "lw      $9,    9*4($26)       \n"
+    "lw      $10,  10*4($26)       \n"
+    "lw      $11,  11*4($26)       \n"
+    "lw      $12,  12*4($26)       \n"
+    "lw      $13,  13*4($26)       \n"
+    "lw      $14,  14*4($26)       \n"
+    "lw      $15,  15*4($26)       \n"
+
+	"lw      $16,  16*4($26)       \n"
+	"lw      $17,  17*4($26)       \n"
+    "lw      $18,  18*4($26)       \n"
+    "lw      $19,  19*4($26)       \n"
+    "lw      $20,  20*4($26)       \n"
+    "lw      $21,  21*4($26)       \n"
+    "lw      $22,  22*4($26)       \n"
+    "lw      $23,  23*4($26)       \n"
+
+    "lw      $24,  24*4($26)       \n"
+    "lw      $25,  25*4($26)       \n"
+
+    "lw      $27,  26*4($26)       \n"
+    "mthi    $27                   \n"   /* restore hi from slot 26 */
+    "lw      $27,  27*4($26)       \n"
+    "mtlo    $27                   \n"   /* restote lo from slot 27 */
+
+	"lw      $28,  28*4($26)       \n"
+	"lw      $29,  29*4($26)       \n"
+	"lw      $30,  30*4($26)       \n"
+	"lw      $31,  31*4($26)       \n"
+
+	"lw      $27,  32*4($26)       \n"
+	"mtc2    $27,  $0              \n"   /* restore c2_ptpr from slot 32 */
+	"lw      $27,  33*4($26)       \n"
+	"mtc2    $27,  $1              \n"   /* restore c2_mode from slot 33 */
+
+	"lw      $27,  34*4($26)       \n"
+    "mtc0	 $27,  $12             \n"   /* restore c0_sr from slot 34 */
+	"lw      $27,  35*4($26)       \n"
+    "mtc0	 $27,  $4, 2           \n"   /* restore co_th from slot 35 */
+
+    ".set reorder                  \n"
+    ".set at                       \n"
+    : : : "$26" , "$27" ); 
+}
 
 /////////////////////////////////////////////
@@ -226,64 +430,11 @@
 }  // end hal_fpu_context_destroy()
 
-//////////////////////////////////////////////      
-void hal_cpu_context_save( thread_t * thread )
-{
-    uint32_t ctx = (uint32_t)thread->cpu_context;
-
-    asm volatile(
-    ".set noreorder                \n" 
-    "sw      $16,   0*4(%0)        \n"   /* save s0 to slot 0                   */
-    "sw      $17,   1*4(%0)        \n"   /* save s1 to slot 1                   */
-    "sw      $18,   2*4(%0)        \n"   /* save s2 to slot 2                   */
-    "sw      $19,   3*4(%0)        \n"   /* save s3 to slot 3                   */
-    "sw      $20,   4*4(%0)        \n"   /* save s4 to slot 4                   */
-    "sw      $21,   5*4(%0)        \n"   /* save s5 to slot 5                   */
-    "sw      $22,   6*4(%0)        \n"   /* save s6 to slot 6                   */
-    "sw      $23,   7*4(%0)        \n"   /* save s7 to slot 7                   */
-    "sw      $29,   8*4(%0)        \n"   /* save sp to slot 8                   */
-    "sw      $30,   9*4(%0)        \n"   /* save fp to slot 9                   */
-    "sw      $31,   10*4(%0)       \n"   /* save ra to slot 10                  */
-    "mfc0	 $26,   $4,	  2        \n"   /* get c0_th from CP0                  */
-	"sw      $26,   12*4(%0)       \n"   /* save c0_th to slot 12               */
-	"mfc2    $26,   $0             \n"   /* get c2_ptpr from CP2                */
-	"sw      $26,   13*4(%0)       \n"   /* save c2_ptpr to slot 13             */
-	"mfc2    $26,   $1             \n"   /* get c2_mod from CP2                 */
-	"sw      $26,   14*4(%0)       \n"   /* save c2_mode to slot 14             */
-    "sync                          \n"
-	".set reorder                  \n"
-    : : "r"( ctx ) : "$26" , "memory" ); 
-}
-
-/////////////////////////////////////////////////      
-void hal_cpu_context_restore( thread_t * thread )
-{
-    uint32_t ctx = (uint32_t)thread->cpu_context;
-
-    asm volatile(
-    ".set noreorder                \n"
-    "nop                           \n"
-	"lw      $16,  0*4(%0)         \n"   /* restore s0_16                       */
-	"lw      $17,  1*4(%0)         \n"   /* restore s1_17                       */
-    "lw      $18,  2*4(%0)         \n"   /* restore s2_18                       */
-    "lw      $19,  3*4(%0)         \n"   /* restore s3_19                       */
-    "lw      $20,  4*4(%0)         \n"   /* restore s4_20                       */
-    "lw      $21,  5*4(%0)         \n"   /* restore s5_21                       */
-    "lw      $22,  6*4(%0)         \n"   /* restore s6_22                       */
-    "lw      $23,  7*4(%0)         \n"   /* restore s7_23                       */
-	"lw      $29,  8*4(%0)         \n"   /* restore sp_29                       */	
-	"lw      $30,  9*4(%0)         \n"   /* restore fp_30                       */
-	"lw  	 $31,  10*4(%0)        \n"   /* restore ra_31                       */
-    "lw      $26,  12*4(%0)        \n"   /* get c0_th from slot 12              */
-	"mtc0    $26,  $4,    2        \n"   /* restore c0_th                       */
-    "lw      $26,  13*4(%0)        \n"   /* get c2_ptpr from slot 13            */
-	"mtc2    $26,  $0              \n"   /* restore c2_ptpr                     */
-    "lw      $26,  14*4(%0)        \n"   /* get c2_mode from slot 14            */
-	"mtc2    $26,  $1              \n"   /* restore c2_mode                     */
-    ".set reorder                  \n"
-    : : "r"(ctx)
-      : "$16","$17","$18","$19","$20","$21","$22","$23","$26","$29","$30","$31" ); 
-}
-
-//////////////////////////////////////////////
+/////////////////////////////////////////////////////////////////////////////////////////
+// These registers are initialised:
+// - GPR : sp_29 , fp_30 , a0
+// - CP0 : c0_sr , c0_epc , c0_th
+// - CP2 : C2_ptpr , c2_mode
+// TODO Quand cette fonction est-elle appelée? [AG]
+/////////////////////////////////////////////////////////////////////////////////////////
 void hal_cpu_context_load( thread_t * thread )
 {
