Index: trunk/hal/tsar_mips32/core/hal_context.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_context.c	(revision 425)
+++ trunk/hal/tsar_mips32/core/hal_context.c	(revision 432)
@@ -41,5 +41,5 @@
 #define SR_USR_MODE       0x0000FF13
 #define SR_USR_MODE_FPU   0x2000FF13
-#define SR_SYS_MODE       0x0000FF00
+#define SR_SYS_MODE       0x0000FF01
 
 /////////////////////////////////////////////////////////////////////////////////////////
@@ -174,17 +174,4 @@
     }
 
-context_dmsg("\n[DBG] %s : thread %x in process %x\n"
-                 " - a0   = %x\n"
-                 " - sp   = %x\n"
-                 " - ra   = %x\n"
-                 " - sr   = %x\n"
-                 " - th   = %x\n"   
-                 " - epc  = %x\n"   
-                 " - ptpr = %x\n"   
-                 " - mode = %x\n",  
-                 __FUNCTION__ , thread->trdid , thread->process->pid,
-                 context->a0_04, context->sp_29, context->ra_31,
-                 context->c0_sr, context->c0_th, context->c0_epc,
-                 context->c2_ptpr, context->c2_mode );
     return 0;
 
@@ -284,5 +271,5 @@
            " c0_sr   = %X    c0_epc  = %X    c0_th = %X\n"
            " c2_ptpr = %X    c2_mode = %X\n",
-           ptr->trdid, ptr->process->pid, hal_time_stamp(),
+           ptr, ptr->process->pid, (uint32_t)hal_get_cycles(),
            sp_29   , ra_31,
            c0_sr   , c0_epc  , c0_th,
Index: trunk/hal/tsar_mips32/core/hal_exception.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_exception.c	(revision 425)
+++ trunk/hal/tsar_mips32/core/hal_exception.c	(revision 432)
@@ -201,7 +201,10 @@
     }
 
-excp_dmsg("\n[DBG] %s : core[%x,%d] / is_ins %d / %s / vaddr %x\n",
-__FUNCTION__ , local_cxy , this->core->lid , is_ins,
-hal_mmu_exception_str(excp_code) , bad_vaddr );
+#if CONFIG_DEBUG_HAL_EXCEPTIONS
+uint32_t cycle = (uint32_t)hal_get_cycles();
+if( CONFIG_DEBUG_HAL_EXCEPTIONS < cycle )
+printk("\n[DBG] %s : thread %x enter / is_ins %d / %s / vaddr %x / cycle %d\n",
+__FUNCTION__, this, is_ins, hal_mmu_exception_str(excp_code), bad_vaddr, cycle );
+#endif
 
    // analyse exception code
@@ -226,6 +229,10 @@
             {
 
-excp_dmsg("\n[DBG] %s : core[%x,%d] / page-fault handled for vaddr = %x\n",
-__FUNCTION__ , local_cxy , this->core->lid , bad_vaddr );
+#if CONFIG_DEBUG_HAL_EXCEPTIONS
+cycle = (uint32_t)hal_get_cycles();
+if( CONFIG_DEBUG_HAL_EXCEPTIONS < cycle )
+printk("\n[DBG] %s : thread %x exit / page-fault handled for vaddr = %x\n",
+__FUNCTION__ , this , bad_vaddr );
+#endif
   
                 return EXCP_NON_FATAL;
@@ -261,6 +268,10 @@
                 {
 
-excp_dmsg("\n[DBG] %s : core[%x,%d] / copy-on-write handled for vaddr = %x\n",
-__FUNCTION__ , local_cxy , this->core->lid , bad_vaddr );
+#if CONFIG_DEBUG_HAL_EXCEPTIONS
+cycle = (uint32_t)hal_get_cycles();
+if( CONFIG_DEBUG_HAL_EXCEPTIONS < cycle )
+printk("\n[DBG] %s : thread %x exit / copy-on-write handled for vaddr = %x\n",
+__FUNCTION__ , this , bad_vaddr );
+#endif
 
                     return EXCP_NON_FATAL;
@@ -377,7 +388,10 @@
 	excCode        = (uzone[UZ_CR] >> 2) & 0xF;
 
-excp_dmsg("\n[DBG] %s : core[%x,%d] / thread %x in process %x / xcode %x / cycle %d\n",
-__FUNCTION__, local_cxy, this->core->lid, this->trdid, 
-this->process->pid, excCode, (uint32_t)hal_get_cycles() );
+#if CONFIG_DEBUG_HAL_EXCEPTIONS
+uint32_t cycle = (uint32_t)hal_get_cycles();
+if( CONFIG_DEBUG_HAL_EXCEPTIONS < cycle )
+printk("\n[DBG] %s : thread %x on core[%x,%d] enter / process %x / xcode %x / cycle %d\n",
+__FUNCTION__, this, local_cxy, this->core->lid, this->process->pid, excCode, cycle );
+#endif
 
 	switch(excCode)
@@ -434,7 +448,10 @@
     }
 
-excp_dmsg("\n[DBG] %s : core[%x,%d] exit / thread %x in process %x / cycle %d\n",
-__FUNCTION__, local_cxy, this->core->lid, this->trdid, this->process->pid,
-(uint32_t)hal_get_cycles() );
+#if CONFIG_DEBUG_HAL_EXCEPTIONS
+cycle = (uint32_t)hal_get_cycles();
+if( CONFIG_DEBUG_HAL_EXCEPTIONS < cycle )
+printk("\n[DBG] %s : thread %x on core[%x,%d] exit / process %x / xcode %x / cycle %d\n",
+__FUNCTION__, this, local_cxy, this->core->lid, this->process->pid, excCode, cycle );
+#endif
 
 }  // end hal_do_exception()
Index: trunk/hal/tsar_mips32/core/hal_gpt.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_gpt.c	(revision 425)
+++ trunk/hal/tsar_mips32/core/hal_gpt.c	(revision 432)
@@ -132,6 +132,10 @@
     xptr_t     page_xp;
 
-gpt_dmsg("\n[DBG] %s : core[%x,%d] enter\n", 
-__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid );
+#if CONFIG_DEBUG_GPT_ACCESS
+uint32_t cycle = (uint32_t)hal_get_cycles;
+if( CONFIG_DEBUG_GPT_ACCESS < cycle )
+printk("\n[DBG] %s : thread %x enter / cycle %d\n", 
+__FUNCTION__, CURRENT_THREAD, cycle );
+#endif
 
     // check page size
@@ -157,6 +161,10 @@
 	gpt->ppn  = ppm_page2ppn( page_xp );
 
-gpt_dmsg("\n[DBG] %s : core[%x,%d] exit\n",
-__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid );
+#if CONFIG_DEBUG_GPT_ACCESS
+cycle = (uint32_t)hal_get_cycles;
+if( CONFIG_DEBUG_GPT_ACCESS < cycle )
+printk("\n[DBG] %s : thread %x exit / cycle %d\n", 
+__FUNCTION__, CURRENT_THREAD, cycle );
+#endif
 
 	return 0;
@@ -332,7 +340,11 @@
     uint32_t            tsar_attr;           // PTE attributes for TSAR MMU
 
-gpt_dmsg("\n[DBG] %s : core[%x,%d] enter for vpn = %x / ppn = %x / gpt_attr = %x\n", 
-__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn , ppn , attr );
- 
+#if CONFIG_DEBUG_GPT_ACCESS
+uint32_t cycle = (uint32_t)hal_get_cycles;
+if( CONFIG_DEBUG_GPT_ACCESS < cycle )
+printk("\n[DBG] %s : thread %x enter / vpn %x / attr %x / ppn %x / cycle %d\n", 
+__FUNCTION__, CURRENT_THREAD, vpn, attr, ppn, cycle );
+#endif
+
     // compute indexes in PT1 and PT2
     ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
@@ -342,9 +354,12 @@
 	small = attr & GPT_SMALL;
 
-    // compute tsar_attr from generic attributes
+    // compute tsar attributes from generic attributes
     tsar_attr = gpt2tsar( attr );
 
-gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / &pt1 = %x / tsar_attr = %x\n", 
-__FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pt1 , tsar_attr );
+#if (CONFIG_DEBUG_GPT_ACCESS & 1)
+if( CONFIG_DEBUG_GPT_ACCESS < cycle )
+printk("\n[DBG] %s : thread %x / vpn %x / &pt1 %x / tsar_attr %x\n", 
+__FUNCTION__, CURRENT_THREAD, vpn, pt1, tsar_attr );
+#endif
 
     // get pointer on PT1[ix1]
@@ -377,6 +392,9 @@
         pte1 = *pte1_ptr;
         
-gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / current_pte1 = %x\n", 
-__FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pte1 );
+#if (CONFIG_DEBUG_GPT_ACCESS & 1)
+if( CONFIG_DEBUG_GPT_ACCESS < cycle )
+printk("\n[DBG] %s : thread %x / vpn %x / current_pte1 %x\n", 
+__FUNCTION__, CURRENT_THREAD, vpn, pte1 );
+#endif
         
         // allocate a PT2 if PT1 entry not valid
@@ -419,6 +437,9 @@
 	    pt2     = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) );
 
-gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / pte1 = %x / &pt2 = %x\n", 
-__FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pte1 , pt2 );
+#if (CONFIG_DEBUG_GPT_ACCESS & 1)
+if( CONFIG_DEBUG_GPT_ACCESS < cycle )
+printk("\n[DBG] %s : thread %x / vpn %x / pte1 %x / &pt2 %x\n", 
+__FUNCTION__, CURRENT_THREAD, vpn, pte1, pt2 );
+#endif
         
     }
@@ -431,8 +452,11 @@
 	hal_fence();
 
-gpt_dmsg("\n[DBG] %s : core[%x,%d] exit / vpn = %x / pte2_attr = %x / pte2_ppn = %x\n", 
-__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn , 
-pt2[2 * ix2] , pt2[2 * ix2 + 1] );
- 
+#if CONFIG_DEBUG_GPT_ACCESS
+cycle = (uint32_t)hal_get_cycles;
+if( CONFIG_DEBUG_GPT_ACCESS < cycle )
+printk("\n[DBG] %s : thread %x exit / vpn %x / pte2_attr %x / pte2_ppn %x / cycle %d\n", 
+__FUNCTION__, CURRENT_THREAD, vpn, pt2[2 * ix2], pt2[2 * ix2 + 1], cycle );
+#endif
+
 	return 0;
 
@@ -738,6 +762,10 @@
     ppn_t        dst_pt2_ppn;
 
-gpt_dmsg("\n[DBG] %s : core[%x,%d] enter for vpn %x\n", 
-__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn );
+#if CONFIG_DEBUG_GPT_ACCESS
+uint32_t cycle = (uint32_t)hal_get_cycles;
+if( CONFIG_DEBUG_GPT_ACCESS < cycle )
+printk("\n[DBG] %s : thread %x enter / vpn %x / cycle %d\n", 
+__FUNCTION__, CURRENT_THREAD, vpn, cycle );
+#endif
 
     // get remote src_gpt cluster and local pointer
@@ -825,6 +853,10 @@
             *ppn    = src_pte2_ppn;
         
-gpt_dmsg("\n[DBG] %s : core[%x,%d] exit for vpn %x / copy done\n", 
-__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn );
+#if CONFIG_DEBUG_GPT_ACCESS
+cycle = (uint32_t)hal_get_cycles;
+if( CONFIG_DEBUG_GPT_ACCESS < cycle )
+printk("\n[DBG] %s : thread %x exit / copy done for vpn %x / cycle %d\n", 
+__FUNCTION__, CURRENT_THREAD, vpn, cycle );
+#endif
 
             hal_fence();
@@ -837,7 +869,11 @@
     *mapped = false;
     *ppn    = 0;
-    
-gpt_dmsg("\n[DBG] %s : core[%x,%d] exit for vpn %x / nothing done\n", 
-__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn );
+   
+#if CONFIG_DEBUG_GPT_ACCESS
+cycle = (uint32_t)hal_get_cycles;
+if( CONFIG_DEBUG_GPT_ACCESS < cycle )
+printk("\n[DBG] %s : thread %x exit / nothing done for vpn %x / cycle %d\n", 
+__FUNCTION__, CURRENT_THREAD, vpn, cycle );
+#endif
 
     hal_fence();
@@ -918,8 +954,7 @@
 
 /////////////////////////////////////////
-void hal_gpt_flip_cow( bool_t  set_cow,
-                       xptr_t  gpt_xp,
-                       vpn_t   vpn_base,
-                       vpn_t   vpn_size )
+void hal_gpt_set_cow( xptr_t  gpt_xp,
+                      vpn_t   vpn_base,
+                      vpn_t   vpn_size )
 {
     cxy_t      gpt_cxy;
@@ -936,7 +971,5 @@
     uint32_t * pt2;
     ppn_t      pt2_ppn;
-
-    uint32_t   old_attr;
-    uint32_t   new_attr;
+    uint32_t   attr;
 
     // get GPT cluster and local pointer
@@ -967,24 +1000,16 @@
   
             // get current PTE2 attributes
-            old_attr = hal_remote_lw( XPTR( gpt_cxy , &pt2[2*ix2] ) );
+            attr = hal_remote_lw( XPTR( gpt_cxy , &pt2[2*ix2] ) );
 
             // only MAPPED PTEs are modified        
-            if( old_attr & TSAR_MMU_MAPPED ) 
+            if( attr & TSAR_MMU_MAPPED ) 
             {
-                if( (set_cow != 0) && (old_attr & TSAR_MMU_WRITABLE) )
-                { 
-                    new_attr = (old_attr | TSAR_MMU_COW) & (~TSAR_MMU_WRITABLE);
-                    hal_remote_sw( XPTR( gpt_cxy , &pt2[2*ix2] ) , new_attr );
-                }
-                if( (set_cow == 0) && (old_attr & TSAR_MMU_COW ) )
-                { 
-                    new_attr = (old_attr | TSAR_MMU_WRITABLE) & (~TSAR_MMU_COW);
-                    hal_remote_sw( XPTR( gpt_cxy , &pt2[2*ix2] ) , new_attr );
-                }
-            }   // end if PTE2 mapped
-        }   // end if PTE1 mapped
+                attr = (attr | TSAR_MMU_COW) & (~TSAR_MMU_WRITABLE);
+                hal_remote_sw( XPTR( gpt_cxy , &pt2[2*ix2] ) , attr );
+            } 
+        } 
     }   // end loop on pages
 
-}  // end hal_gpt_flip_cow()
+}  // end hal_gpt_set_cow()
 
 //////////////////////////////////////////
Index: trunk/hal/tsar_mips32/core/hal_interrupt.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_interrupt.c	(revision 425)
+++ trunk/hal/tsar_mips32/core/hal_interrupt.c	(revision 432)
@@ -34,5 +34,5 @@
 
 irq_dmsg("\n[DBG] %s : core[%x,%d] enter at cycle %d\n",
-__FUNCTION__ , local_cxy , this->core->lid , hal_time_stamp() );
+__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , hal_time_stamp() );
 
     // As ALMOS-MKH does not define a generic interrupt handler,
@@ -41,5 +41,5 @@
 
 irq_dmsg("\n[DBG] %s : core[%x,%d] exit at cycle %d\n",
-__FUNCTION__ , local_cxy , this->core->lid , hal_time_stamp() );
+__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , hal_time_stamp() );
 
 }
Index: trunk/hal/tsar_mips32/core/hal_kentry.S
===================================================================
--- trunk/hal/tsar_mips32/core/hal_kentry.S	(revision 425)
+++ trunk/hal/tsar_mips32/core/hal_kentry.S	(revision 432)
@@ -200,6 +200,6 @@
 	mtc0	$3,	    $12			        # set new c0_sr 
 
-#-----------------------
-#if CONFIG_KENTRY_DEBUG 
+#--------------------------
+#if CONFIG_DEBUG_HAL_KENTRY 
 
     # display "enter" message
@@ -349,6 +349,6 @@
     sw      $5,    8($4)                # current uzone pointer <= previous
 
-#----------------------
-#if CONFIG_KENTRY_DEBUG
+#--------------------------
+#if CONFIG_DEBUG_HAL_KENTRY
 
     # display "exit" message
Index: trunk/hal/tsar_mips32/core/hal_ppm.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_ppm.c	(revision 425)
+++ trunk/hal/tsar_mips32/core/hal_ppm.c	(revision 432)
@@ -43,5 +43,5 @@
 // This hal_ppm_init() function initializes the pages_tbl[] array used by the generic
 // kmem memory allocator in the local cluster. This array starts in first free page
-// after kernel code, as defined by the 'offset' field in boot_info.
+// after kernel code, as defined by the 'pages_offset' field in boot_info.
 //////////////////////////////////////////////////////////////////////////////////////////
 
@@ -101,4 +101,6 @@
 	}
 
+// printk("\n@@@ in %s : reserved = %d / total = %d\n", __FUNCTION__, reserved_pages, pages_nr );
+
 	// - set PG_RESERVED flag for reserved pages (kernel code & pages_tbl[])
 	// - release all other pages to populate the free lists
@@ -112,7 +114,12 @@
 
 		// TODO optimisation : decompose this enormous set of small pages
-		// to several sets of big pages with various order values
+		// to several sets of big pages with various order values [AG]
+
+// if( (i < (reserved_pages+10)) || (i > (pages_nr-5)) ) ppm_print();
+
 	}
 
+// assert( false , __FUNCTION__ , "PMM init completed\n");
+ 
 	// check consistency
 	return ppm_assert_order( ppm );
