Changeset 438 for trunk/hal/tsar_mips32


Ignore:
Timestamp:
Apr 4, 2018, 2:49:02 PM (7 years ago)
Author:
alain
Message:

Fix a bug in scheduler related to RPC blocking.

Location:
trunk/hal/tsar_mips32
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • trunk/hal/tsar_mips32/core/hal_exception.c

    r437 r438  
    201201    }
    202202
    203 #if CONFIG_DEBUG_HAL_EXCEPTIONS
     203#if DEBUG_HAL_EXCEPTIONS
    204204uint32_t cycle = (uint32_t)hal_get_cycles();
    205 if( CONFIG_DEBUG_HAL_EXCEPTIONS < cycle )
     205if( DEBUG_HAL_EXCEPTIONS < cycle )
    206206printk("\n[DBG] %s : thread %x enter / is_ins %d / %s / vaddr %x / cycle %d\n",
    207207__FUNCTION__, this, is_ins, hal_mmu_exception_str(excp_code), bad_vaddr, cycle );
    … …  
    229229            {
    230230
    231 #if CONFIG_DEBUG_HAL_EXCEPTIONS
     231#if DEBUG_HAL_EXCEPTIONS
    232232cycle = (uint32_t)hal_get_cycles();
    233 if( CONFIG_DEBUG_HAL_EXCEPTIONS < cycle )
     233if( DEBUG_HAL_EXCEPTIONS < cycle )
    234234printk("\n[DBG] %s : thread %x exit / page-fault handled for vaddr = %x\n",
    235235__FUNCTION__ , this , bad_vaddr );
    … …  
    268268                {
    269269
    270 #if CONFIG_DEBUG_HAL_EXCEPTIONS
     270#if DEBUG_HAL_EXCEPTIONS
    271271cycle = (uint32_t)hal_get_cycles();
    272 if( CONFIG_DEBUG_HAL_EXCEPTIONS < cycle )
     272if( DEBUG_HAL_EXCEPTIONS < cycle )
    273273printk("\n[DBG] %s : thread %x exit / copy-on-write handled for vaddr = %x\n",
    274274__FUNCTION__ , this , bad_vaddr );
    … …  
    390390    excPC          = uzone[UZ_EPC];
    391391
    392 #if CONFIG_DEBUG_HAL_EXCEPTIONS
     392#if DEBUG_HAL_EXCEPTIONS
    393393uint32_t cycle = (uint32_t)hal_get_cycles();
    394 if( CONFIG_DEBUG_HAL_EXCEPTIONS < cycle )
     394if( DEBUG_HAL_EXCEPTIONS < cycle )
    395395printk("\n[DBG] %s : thread %x enter / core[%x,%d] / pid %x / epc %x / xcode %x / cycle %d\n",
    396396__FUNCTION__, this, local_cxy, this->core->lid, this->process->pid, excPC, excCode, cycle );
    … …  
    450450    }
    451451
    452 #if CONFIG_DEBUG_HAL_EXCEPTIONS
     452#if DEBUG_HAL_EXCEPTIONS
    453453cycle = (uint32_t)hal_get_cycles();
    454 if( CONFIG_DEBUG_HAL_EXCEPTIONS < cycle )
     454if( DEBUG_HAL_EXCEPTIONS < cycle )
    455455printk("\n[DBG] %s : thread %x exit / core[%x,%d] / pid %x / epc %x / xcode %x / cycle %d\n",
    456456__FUNCTION__, this, local_cxy, this->core->lid, this->process->pid, excPC, excCode, cycle );

  • trunk/hal/tsar_mips32/core/hal_gpt.c

    r432 r438  
    132132    xptr_t     page_xp;
    133133
    134 #if CONFIG_DEBUG_GPT_ACCESS
     134#if DEBUG_GPT_ACCESS
    135135uint32_t cycle = (uint32_t)hal_get_cycles;
    136 if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     136if( DEBUG_GPT_ACCESS < cycle )
    137137printk("\n[DBG] %s : thread %x enter / cycle %d\n",
    138138__FUNCTION__, CURRENT_THREAD, cycle );
    … …  
    161161        gpt->ppn  = ppm_page2ppn( page_xp );
    162162
    163 #if CONFIG_DEBUG_GPT_ACCESS
     163#if DEBUG_GPT_ACCESS
    164164cycle = (uint32_t)hal_get_cycles;
    165 if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     165if( DEBUG_GPT_ACCESS < cycle )
    166166printk("\n[DBG] %s : thread %x exit / cycle %d\n",
    167167__FUNCTION__, CURRENT_THREAD, cycle );
    … …  
    340340    uint32_t            tsar_attr;           // PTE attributes for TSAR MMU
    341341
    342 #if CONFIG_DEBUG_GPT_ACCESS
     342#if DEBUG_GPT_ACCESS
    343343uint32_t cycle = (uint32_t)hal_get_cycles;
    344 if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     344if( DEBUG_GPT_ACCESS < cycle )
    345345printk("\n[DBG] %s : thread %x enter / vpn %x / attr %x / ppn %x / cycle %d\n",
    346346__FUNCTION__, CURRENT_THREAD, vpn, attr, ppn, cycle );
    … …  
    357357    tsar_attr = gpt2tsar( attr );
    358358
    359 #if (CONFIG_DEBUG_GPT_ACCESS & 1)
    360 if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     359#if (DEBUG_GPT_ACCESS & 1)
     360if( DEBUG_GPT_ACCESS < cycle )
    361361printk("\n[DBG] %s : thread %x / vpn %x / &pt1 %x / tsar_attr %x\n",
    362362__FUNCTION__, CURRENT_THREAD, vpn, pt1, tsar_attr );
    … …  
    392392        pte1 = *pte1_ptr;
    393393       
    394 #if (CONFIG_DEBUG_GPT_ACCESS & 1)
    395 if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     394#if (DEBUG_GPT_ACCESS & 1)
     395if( DEBUG_GPT_ACCESS < cycle )
    396396printk("\n[DBG] %s : thread %x / vpn %x / current_pte1 %x\n",
    397397__FUNCTION__, CURRENT_THREAD, vpn, pte1 );
    … …  
    437437            pt2     = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) );
    438438
    439 #if (CONFIG_DEBUG_GPT_ACCESS & 1)
    440 if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     439#if (DEBUG_GPT_ACCESS & 1)
     440if( DEBUG_GPT_ACCESS < cycle )
    441441printk("\n[DBG] %s : thread %x / vpn %x / pte1 %x / &pt2 %x\n",
    442442__FUNCTION__, CURRENT_THREAD, vpn, pte1, pt2 );
    … …  
    452452        hal_fence();
    453453
    454 #if CONFIG_DEBUG_GPT_ACCESS
     454#if DEBUG_GPT_ACCESS
    455455cycle = (uint32_t)hal_get_cycles;
    456 if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     456if( DEBUG_GPT_ACCESS < cycle )
    457457printk("\n[DBG] %s : thread %x exit / vpn %x / pte2_attr %x / pte2_ppn %x / cycle %d\n",
    458458__FUNCTION__, CURRENT_THREAD, vpn, pt2[2 * ix2], pt2[2 * ix2 + 1], cycle );
    … …  
    762762    ppn_t        dst_pt2_ppn;
    763763
    764 #if CONFIG_DEBUG_GPT_ACCESS
     764#if DEBUG_GPT_ACCESS
    765765uint32_t cycle = (uint32_t)hal_get_cycles;
    766 if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     766if( DEBUG_GPT_ACCESS < cycle )
    767767printk("\n[DBG] %s : thread %x enter / vpn %x / cycle %d\n",
    768768__FUNCTION__, CURRENT_THREAD, vpn, cycle );
    … …  
    853853            *ppn    = src_pte2_ppn;
    854854       
    855 #if CONFIG_DEBUG_GPT_ACCESS
     855#if DEBUG_GPT_ACCESS
    856856cycle = (uint32_t)hal_get_cycles;
    857 if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     857if( DEBUG_GPT_ACCESS < cycle )
    858858printk("\n[DBG] %s : thread %x exit / copy done for vpn %x / cycle %d\n",
    859859__FUNCTION__, CURRENT_THREAD, vpn, cycle );
    … …  
    870870    *ppn    = 0;
    871871   
    872 #if CONFIG_DEBUG_GPT_ACCESS
     872#if DEBUG_GPT_ACCESS
    873873cycle = (uint32_t)hal_get_cycles;
    874 if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     874if( DEBUG_GPT_ACCESS < cycle )
    875875printk("\n[DBG] %s : thread %x exit / nothing done for vpn %x / cycle %d\n",
    876876__FUNCTION__, CURRENT_THREAD, vpn, cycle );

  • trunk/hal/tsar_mips32/core/hal_kentry.S

    r432 r438  
    200200        mtc0    $3,         $12                         # set new c0_sr
    201201
    202 #--------------------------
    203 #if CONFIG_DEBUG_HAL_KENTRY
     202#--------------------
     203#if DEBUG_HAL_KENTRY
    204204
    205205    # display "enter" message
    … …  
    349349    sw      $5,    8($4)                # current uzone pointer <= previous
    350350
    351 #--------------------------
    352 #if CONFIG_DEBUG_HAL_KENTRY
     351#-------------------
     352#if DEBUG_HAL_KENTRY
    353353
    354354    # display "exit" message

  • trunk/hal/tsar_mips32/drivers/soclib_bdv.c

    r437 r438  
    7575    ioc_xp   = (xptr_t)hal_remote_lwd( XPTR( th_cxy , &th_ptr->ioc_cmd.dev_xp ) );
    7676
    77 #if CONFIG_DEBUG_HAL_IOC_RX
    78 uint32_t cycle = (uint32_t)hal_get_cycles();
    79 if( (CONFIG_DEBUG_HAL_IOC_RX < cycle) && (cmd_type != IOC_WRITE ) )
     77#if DEBUG_HAL_IOC_RX
     78uint32_t cycle = (uint32_t)hal_get_cycles();
     79if( (DEBUG_HAL_IOC_RX < cycle) && (cmd_type != IOC_WRITE ) )
    8080printk("\n[DBG] %s : thread %x enter for RX / cycle %d\n",
    8181__FUNCTION__ , CURRENT_THREAD , cycle );
    8282#endif
    8383
    84 #if CONFIG_DEBUG_HAL_IOC_TX
    85 uint32_t cycle = (uint32_t)hal_get_cycles();
    86 if( (CONFIG_DEBUG_HAL_IOC_TX < cycle) && (cmd_type == IOC_WRITE) )
     84#if DEBUG_HAL_IOC_TX
     85uint32_t cycle = (uint32_t)hal_get_cycles();
     86if( (DEBUG_HAL_IOC_TX < cycle) && (cmd_type == IOC_WRITE) )
    8787printk("\n[DBG] %s : thread %x enter for TX / cycle %d\n",
    8888__FUNCTION__ , CURRENT_THREAD , cycle );
    … …  
    152152    }
    153153   
    154 #if CONFIG_DEBUG_HAL_IOC_RX
     154#if DEBUG_HAL_IOC_RX
    155155cycle = (uint32_t)hal_get_cycles();
    156 if( (CONFIG_DEBUG_HAL_IOC_RX < cycle) && (cmd_type != TXT_WRITE) )
     156if( (DEBUG_HAL_IOC_RX < cycle) && (cmd_type != TXT_WRITE) )
    157157printk("\n[DBG] %s : thread %x exit after RX / cycle %d\n",
    158158__FUNCTION__ , CURRENT_THREAD , cycle );
    159159#endif
    160160
    161 #if CONFIG_DEBUG_HAL_IOC_TX
     161#if DEBUG_HAL_IOC_TX
    162162cycle = (uint32_t)hal_get_cycles();
    163 if( (CONFIG_DEBUG_HAL_IOC_TX < cycle) && (cmd_type == TXT_WRITE) )
     163if( (DEBUG_HAL_IOC_TX < cycle) && (cmd_type == TXT_WRITE) )
    164164printk("\n[DBG] %s : thread %x exit after TX / cycle %d\n",
    165165__FUNCTION__ , CURRENT_THREAD , cycle );
    … …  
    199199            error = (status != BDV_READ_SUCCESS);
    200200
    201 #if CONFIG_DEBUG_HAL_IOC_RX
    202 uint32_t cycle = (uint32_t)hal_get_cycles();
    203 if( CONFIG_DEBUG_HAL_IOC_RX < cycle )
     201#if DEBUG_HAL_IOC_RX
     202uint32_t cycle = (uint32_t)hal_get_cycles();
     203if( DEBUG_HAL_IOC_RX < cycle )
    204204printk("\n[DBG] %s : IOC_IRQ / RX transfer / client %x / server %x / cycle %d\n",
    205205__FUNCTION__, client_ptr , chdev->server , cycle );
    … …  
    211211            error = (status != BDV_WRITE_SUCCESS);
    212212
    213 #if CONFIG_DEBUG_HAL_IOC_TX
    214 uint32_t cycle = (uint32_t)hal_get_cycles();
    215 if( CONFIG_DEBUG_HAL_IOC_TX < cycle )
     213#if DEBUG_HAL_IOC_TX
     214uint32_t cycle = (uint32_t)hal_get_cycles();
     215if( DEBUG_HAL_IOC_TX < cycle )
    216216printk("\n[DBG] %s : IOC_IRQ / RX transfer / client %x / server %x / cycle %d\n",
    217217__FUNCTION__, client_ptr , chdev->server , cycle );

  • trunk/hal/tsar_mips32/drivers/soclib_pic.c

    r435 r438  
    130130                           &pti_status );
    131131
    132 #if CONFIG_DEBUG_HAL_IRQS
     132#if DEBUG_HAL_IRQS
    133133uint32_t cycle = (uint32_t)hal_get_cycles();
    134 if (CONFIG_DEBUG_HAL_IRQS < cycle )
     134if (DEBUG_HAL_IRQS < cycle )
    135135printk("\n[DBG] %s : core[%x,%d] enter / WTI = %x / HWI = %x / PTI = %x / cycle %d\n",
    136136__FUNCTION__ , local_cxy , core->lid , wti_status , hwi_status , pti_status, cycle );
    … …  
    143143        index = wti_status - 1;
    144144
     145        ////////////////////////////////////////////////////////
    145146        if( index < LOCAL_CLUSTER->cores_nr )   // it is an IPI
    146147        {
    147148            assert( (index == core->lid) , __FUNCTION__ , "illegal IPI index" );
    148149
    149 #if CONFIG_DEBUG_HAL_IRQS
    150 if (CONFIG_DEBUG_HAL_IRQS < cycle )
     150#if DEBUG_HAL_IRQS
     151if (DEBUG_HAL_IRQS < cycle )
    151152printk("\n[DBG] %s : core[%x,%d] received an IPI\n", __FUNCTION__ , local_cxy , core->lid );
    152153#endif
    153             // acknowledge WTI (this require an XCU read)
     154            // acknowledge IRQ (this require an XCU read)
    154155            uint32_t   ack  = xcu_base[(XCU_WTI_REG << 5) | core->lid];
    155            
     156
    156157            // check RPC FIFO,  and activate or create a RPC thread
    157158            // condition is always true, but we must use the ack value
    158159            if( ack + 1 ) rpc_check();
    159160        }
    160         else                                    // it is an external device
     161        ////////////////////////////////////////////////////////////////
     162        else                                    // it is an external IRQ
    161163        {
    162164            // get pointer on source chdev
    … …  
    171173
    172174                // disable WTI in local XCU controller
    173                 uint32_t * base = soclib_pic_xcu_base();
    174                 base[(XCU_MSK_WTI_DISABLE << 5) | core->lid] = 1 << core->lid;
     175                xcu_base[(XCU_MSK_WTI_DISABLE << 5) | core->lid] = 1 << core->lid;
     176
     177                hal_fence();
    175178            }
    176179            else                                 // call relevant ISR
    177180            {
    178181
    179 #if CONFIG_DEBUG_HAL_IRQS
    180 if (CONFIG_DEBUG_HAL_IRQS < cycle )
     182#if DEBUG_HAL_IRQS
     183if (DEBUG_HAL_IRQS < cycle )
    181184printk("\n[DBG] %s : core[%x,%d] received external WTI %d\n",
    182185__FUNCTION__ , local_cxy , core->lid , index );
    … …  
    188191        }
    189192
    190         if( hwi_status )      // pending HWI
     193    /////////////////////////////////////////////////////////////
     194        if( hwi_status )                     // It is an Internal IRQ
    191195        {
    192196        index = hwi_status - 1;
    … …  
    204208            // disable HWI in local XCU controller
    205209            xcu_base[(XCU_MSK_HWI_DISABLE << 5) | core->lid] = 1 << core->lid;
     210
     211            hal_fence();
    206212                }
    207213        else                    // call relevant ISR
    208214        {
    209215
    210 #if CONFIG_DEBUG_HAL_IRQS
    211 if (CONFIG_DEBUG_HAL_IRQS < cycle )
     216#if DEBUG_HAL_IRQS
     217if (DEBUG_HAL_IRQS < cycle )
    212218printk("\n[DBG] %s : core[%x,%d] received HWI %d\n",
    213219__FUNCTION__ , local_cxy , core->lid , index );
    … …  
    217223        }
    218224        }
    219 
    220     if( pti_status )      // pending PTI
     225    ///////////////////////////////////////////////////////
     226    if( pti_status )                   // It is a Timer IRQ
    221227        {
    222228        index = pti_status - 1;
    … …  
    224230        assert( (index == core->lid) , __FUNCTION__ , "unconsistent PTI index\n");
    225231
    226 #if CONFIG_DEBUG_HAL_IRQS
    227 if (CONFIG_DEBUG_HAL_IRQS < cycle )
     232#if DEBUG_HAL_IRQS
     233if (DEBUG_HAL_IRQS < cycle )
    228234printk("\n[DBG] %s : core[%x,%d] received PTI %d\n",
    229235__FUNCTION__ , core->lid , local_cxy , index );
    230236#endif
    231         // acknowledge PTI (this require a read access to XCU)
     237        // acknowledge IRQ (this require a read access to XCU)
    232238        uint32_t   ack  = xcu_base[(XCU_PTI_ACK << 5) | core->lid];
    233239
    … …  
    359365{
    360366
    361 #if CONFIG_DEBUG_HAL_IRQS
     367#if DEBUG_HAL_IRQS
    362368uint32_t cycle = (uint32_t)hal_get_cycles();
    363 if( CONFIG_DEBUG_HAL_IRQS < cycle )
     369if( DEBUG_HAL_IRQS < cycle )
    364370printk("\n[DBG] %s : thread %x enter for core[%x,%d] / cycle %d\n",
    365371__FUNCTION__ , CURRENT_THREAD , local_cxy , lid , cycle );
    … …  
    422428        ((soclib_pic_core_t *)core->pic_extend)->wti_vector[wti_id] = src_chdev;
    423429
    424 #if CONFIG_DEBUG_HAL_IRQS
    425 if( CONFIG_DEBUG_HAL_IRQS < cycle )
     430#if DEBUG_HAL_IRQS
     431if( DEBUG_HAL_IRQS < cycle )
    426432printk("\n[DBG] %s : %s / channel = %d / rx = %d / hwi_id = %d / wti_id = %d / cluster = %x\n",
    427433__FUNCTION__ , chdev_func_str( func ) , channel , is_rx , hwi_id , wti_id , local_cxy );
    … …  
    444450        ((soclib_pic_core_t *)core->pic_extend)->wti_vector[hwi_id] = src_chdev;
    445451
    446 #if CONFIG_DEBUG_HAL_IRQS
    447 if( CONFIG_DEBUG_HAL_IRQS < cycle )
     452#if DEBUG_HAL_IRQS
     453if( DEBUG_HAL_IRQS < cycle )
    448454printk("\n[DBG] %s : %s / channel = %d / hwi_id = %d / cluster = %x\n",
    449455__FUNCTION__ , chdev_func_str( func ) , channel , hwi_id , local_cxy );

  • trunk/hal/tsar_mips32/drivers/soclib_tty.c

    r436 r438  
    3030#include <hal_special.h>
    3131
    32 #if (CONFIG_DEBUG_SYS_READ & 1)
     32#if (DEBUG_SYS_READ & 1)
    3333extern uint32_t  enter_tty_cmd_read;
    3434extern uint32_t  exit_tty_cmd_read;
    … …  
    3838#endif
    3939
    40 #if (CONFIG_DEBUG_SYS_WRITE & 1)
     40#if (DEBUG_SYS_WRITE & 1)
    4141extern uint32_t  enter_tty_cmd_write;
    4242extern uint32_t  exit_tty_cmd_write;
    … …  
    115115    xptr_t   error_xp = XPTR( th_cxy , &th_ptr->txt_cmd.error );
    116116
    117 #if (CONFIG_DEBUG_SYS_READ & 1)
     117#if (DEBUG_SYS_READ & 1)
    118118if( type == TXT_READ) enter_tty_cmd_read = (uint32_t)hal_get_cycles();
    119119#endif
    120120
    121 #if (CONFIG_DEBUG_SYS_WRITE & 1)
     121#if (DEBUG_SYS_WRITE & 1)
    122122if( type == TXT_WRITE) enter_tty_cmd_write = (uint32_t)hal_get_cycles();
    123123#endif
    124124
    125 #if CONFIG_DEBUG_HAL_TXT_RX
     125#if DEBUG_HAL_TXT_RX
    126126uint32_t cycle = (uint32_t)hal_get_cycles();
    127 if( (CONFIG_DEBUG_HAL_TXT_RX < cycle) && (type == TXT_READ) )
     127if( (DEBUG_HAL_TXT_RX < cycle) && (type == TXT_READ) )
    128128printk("\n[DBG] %s : thread %x enter for RX / cycle %d\n",
    129129__FUNCTION__ , CURRENT_THREAD , cycle );
    130130#endif
    131131
    132 #if CONFIG_DEBUG_HAL_TXT_TX
     132#if DEBUG_HAL_TXT_TX
    133133uint32_t cycle = (uint32_t)hal_get_cycles();
    134 if( (CONFIG_DEBUG_HAL_TXT_TX < cycle) && (type == TXT_WRITE) )
     134if( (DEBUG_HAL_TXT_TX < cycle) && (type == TXT_WRITE) )
    135135printk("\n[DBG] %s : thread %x enter for TX / cycle %d\n",
    136136__FUNCTION__ , CURRENT_THREAD , cycle );
    … …  
    238238    }
    239239
    240 #if CONFIG_DEBUG_HAL_TXT_RX
     240#if DEBUG_HAL_TXT_RX
    241241cycle = (uint32_t)hal_get_cycles();
    242 if( (CONFIG_DEBUG_HAL_TXT_RX < cycle) && (type == TXT_READ) )
     242if( (DEBUG_HAL_TXT_RX < cycle) && (type == TXT_READ) )
    243243printk("\n[DBG] %s : thread %x exit after RX / cycle %d\n",
    244244__FUNCTION__ , CURRENT_THREAD , cycle );
    245245#endif
    246246
    247 #if CONFIG_DEBUG_HAL_TXT_TX
     247#if DEBUG_HAL_TXT_TX
    248248cycle = (uint32_t)hal_get_cycles();
    249 if( (CONFIG_DEBUG_HAL_TXT_TX < cycle) && (type == TXT_WRITE) )
     249if( (DEBUG_HAL_TXT_TX < cycle) && (type == TXT_WRITE) )
    250250printk("\n[DBG] %s : thread %x exit after TX / cycle %d\n",
    251251__FUNCTION__ , CURRENT_THREAD , cycle );
    252252#endif
    253253
    254 #if (CONFIG_DEBUG_SYS_READ & 1)
     254#if (DEBUG_SYS_READ & 1)
    255255if( type == TXT_READ ) exit_tty_cmd_read = (uint32_t)hal_get_cycles();
    256256#endif
    257257
    258 #if (CONFIG_DEBUG_SYS_WRITE & 1)
     258#if (DEBUG_SYS_WRITE & 1)
    259259if( type == TXT_WRITE ) exit_tty_cmd_write = (uint32_t)hal_get_cycles();
    260260#endif
    … …  
    288288    server_lid = server->core->lid;
    289289
    290 #if (CONFIG_DEBUG_SYS_READ & 1)
     290#if (DEBUG_SYS_READ & 1)
    291291if( is_rx ) enter_tty_isr_read = (uint32_t)hal_get_cycles();
    292292#endif
    293293
    294 #if (CONFIG_DEBUG_SYS_WRITE & 1)
     294#if (DEBUG_SYS_WRITE & 1)
    295295if( is_rx == 0 ) enter_tty_isr_write = (uint32_t)hal_get_cycles();
    296296#endif
    297297
    298 #if CONFIG_DEBUG_HAL_TXT_RX
     298#if DEBUG_HAL_TXT_RX
    299299uint32_t cycle = (uint32_t)hal_get_cycles();
    300 if( (CONFIG_DEBUG_HAL_TXT_RX < cycle) && is_rx )
     300if( (DEBUG_HAL_TXT_RX < cycle) && is_rx )
    301301printk("\n[DBG] %s : enter for RX / cycle %d\n", __FUNCTION__ , cycle );
    302302#endif
    303303
    304 #if CONFIG_DEBUG_HAL_TXT_TX
     304#if DEBUG_HAL_TXT_TX
    305305uint32_t cycle = (uint32_t)hal_get_cycles();
    306 if( (CONFIG_DEBUG_HAL_TXT_TX < cycle) && (is_rx == 0) )
     306if( (DEBUG_HAL_TXT_TX < cycle) && (is_rx == 0) )
    307307printk("\n[DBG] %s : enter for TX / cycle %d\n", __FUNCTION__ , cycle );
    308308#endif
    … …  
    459459    hal_fence();
    460460
    461 #if CONFIG_DEBUG_HAL_TXT_RX
     461#if DEBUG_HAL_TXT_RX
    462462cycle = (uint32_t)hal_get_cycles();
    463 if( (CONFIG_DEBUG_HAL_TXT_RX < cycle) && is_rx )
     463if( (DEBUG_HAL_TXT_RX < cycle) && is_rx )
    464464printk("\n[DBG] %s : exit after RX / cycle %d\n", __FUNCTION__, cycle );
    465465#endif
    466466
    467 #if CONFIG_DEBUG_HAL_TXT_TX
     467#if DEBUG_HAL_TXT_TX
    468468cycle = (uint32_t)hal_get_cycles();
    469 if( (CONFIG_DEBUG_HAL_TXT_TX < cycle) && (is_rx == 0) )
     469if( (DEBUG_HAL_TXT_TX < cycle) && (is_rx == 0) )
    470470printk("\n[DBG] %s : exit after TX / cycle %d\n", __FUNCTION__, cycle );
    471471#endif
    472472
    473 #if (CONFIG_DEBUG_SYS_READ & 1)
     473#if (DEBUG_SYS_READ & 1)
    474474if( is_rx ) exit_tty_isr_read = (uint32_t)hal_get_cycles();
    475475#endif
    476476
    477 #if (CONFIG_DEBUG_SYS_WRITE & 1)
     477#if (DEBUG_SYS_WRITE & 1)
    478478if( is_rx == 0 ) exit_tty_isr_write = (uint32_t)hal_get_cycles();
    479479#endif
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