Index: trunk/hal/x86_64/core/hal_acpi.c
===================================================================
--- trunk/hal/x86_64/core/hal_acpi.c	(revision 457)
+++ trunk/hal/x86_64/core/hal_acpi.c	(revision 482)
@@ -300,5 +300,5 @@
 /* -------------------------------------------------------------------------- */
 
-void hal_acpi_init()
+void hal_acpi_init( void )
 {
 	rsdp_t *rsdp;
Index: trunk/hal/x86_64/core/hal_acpi.h
===================================================================
--- trunk/hal/x86_64/core/hal_acpi.h	(revision 457)
+++ trunk/hal/x86_64/core/hal_acpi.h	(revision 482)
@@ -58,5 +58,5 @@
  */
 
-void hal_acpi_init();
+void hal_acpi_init( void );
 
 #define ACPI_RSDP_ALIGN	16
Index: trunk/hal/x86_64/core/hal_apic.c
===================================================================
--- trunk/hal/x86_64/core/hal_apic.c	(revision 457)
+++ trunk/hal/x86_64/core/hal_apic.c	(revision 482)
@@ -104,5 +104,5 @@
 
 uint64_t
-hal_pit_timer_read()
+hal_pit_timer_read( void )
 {
 	uint8_t lo, hi;
@@ -197,15 +197,15 @@
 #define RS232_SCRATCH	0x07
 
-static bool_t hal_com_received()
+static bool_t hal_com_received( void )
 {
 	return (in8(RS232_COM1_BASE + RS232_LSR) & LSR_DR) != 0;
 }
 
-static bool_t hal_com_transmit_empty()
+static bool_t hal_com_transmit_empty( void )
 {
 	return (in8(RS232_COM1_BASE + RS232_LSR) & LSR_TBE) != 0;
 }
 
-char hal_com_read()
+char hal_com_read( void )
 {
 	while (!hal_com_received());
@@ -228,5 +228,5 @@
  * Called early to provide x86-specific messages. Interrupts disabled.
  */
-void hal_com_init_early()
+void hal_com_init_early( void )
 {
 	/* Disable all interrupts */
@@ -246,5 +246,5 @@
 }
 
-static void hal_com_init()
+static void hal_com_init( void )
 {
 	/* Disable all interrupts */
@@ -337,5 +337,5 @@
 }
 
-static void hal_ioapic_init()
+static void hal_ioapic_init( void )
 {
 	uint32_t ver;
@@ -374,10 +374,10 @@
 }
 
-uint32_t hal_lapic_gid()
+uint32_t hal_lapic_gid( void )
 {
 	return hal_lapic_read(LAPIC_ID) >> LAPIC_ID_SHIFT;
 }
 
-static void hal_lapic_icr_wait()
+static void hal_lapic_icr_wait( void )
 {
 	while ((hal_lapic_read(LAPIC_ICRLO) & LAPIC_DLSTAT_BUSY) != 0) {
@@ -390,5 +390,5 @@
  * exact bus frequency.
  */
-static void hal_lapic_calibrate()
+static void hal_lapic_calibrate( void )
 {
 	uint64_t pittick, lapictick0, lapictick1;
@@ -442,5 +442,5 @@
  * Only the Spurious and APIC Timer interrupts are enabled.
  */
-void cpu_lapic_init()
+void cpu_lapic_init( void )
 {
 	if ((rdmsr(MSR_APICBASE) & APICBASE_PHYSADDR) != lapic_pa) {
@@ -536,5 +536,5 @@
 /* -------------------------------------------------------------------------- */
 
-void hal_apic_init()
+void hal_apic_init( void )
 {
 	/* Disable the PIC */
Index: trunk/hal/x86_64/core/hal_apic.h
===================================================================
--- trunk/hal/x86_64/core/hal_apic.h	(revision 457)
+++ trunk/hal/x86_64/core/hal_apic.h	(revision 482)
@@ -21,7 +21,7 @@
 
 #ifndef x86_ASM
-char hal_com_read();
+char hal_com_read( void );
 void hal_com_send(uint8_t chan, char c);
-void hal_com_init_early();
+void hal_com_init_early( void );
 
 void hal_ioapic_bind_irq(uint8_t irq, uint8_t vec, uint8_t dest);
@@ -32,7 +32,7 @@
 void hal_ioapic_set_entry(uint8_t irq, uint8_t vec, uint8_t dest);
 
-uint32_t hal_lapic_gid();
-void cpu_lapic_init();
-void hal_apic_init();
+uint32_t hal_lapic_gid( void );
+void cpu_lapic_init( void );
+void hal_apic_init( void );
 
 int boot_cpuN(uint32_t gid, paddr_t pa);
Index: trunk/hal/x86_64/core/hal_gpt.c
===================================================================
--- trunk/hal/x86_64/core/hal_gpt.c	(revision 457)
+++ trunk/hal/x86_64/core/hal_gpt.c	(revision 482)
@@ -61,5 +61,5 @@
  * function, cluster0's heap is empty.
  */
-void hal_gpt_bootstrap_reset()
+void hal_gpt_bootstrap_reset( void )
 {
 	/*
@@ -78,5 +78,5 @@
  * only call hal_gpt_bootstrap_valloc, without entering it in a PA.
  */
-size_t hal_gpt_bootstrap_uniformize()
+size_t hal_gpt_bootstrap_uniformize( void )
 {
 	size_t pa_offset = pa_avail - 0;
Index: trunk/hal/x86_64/core/hal_init.c
===================================================================
--- trunk/hal/x86_64/core/hal_init.c	(revision 457)
+++ trunk/hal/x86_64/core/hal_init.c	(revision 482)
@@ -47,8 +47,8 @@
 void kernel_init(boot_info_t *info);
 
-static void gdt_create();
-static void idt_create();
+static void gdt_create( void );
+static void idt_create( void );
 void cpu_tls_init(size_t lid);
-void cpu_identify();
+void cpu_identify( void );
 void cpu_attach(size_t lid);
 
@@ -85,5 +85,5 @@
  * Configure the features of the system depending on the multiboot info.
  */
-static void multiboot_init()
+static void multiboot_init( void )
 {
 	size_t mmap_length = mb_info.mi_mmap_length;
@@ -118,5 +118,5 @@
 /* -------------------------------------------------------------------------- */
 
-static size_t init_bootinfo_pages_nr()
+static size_t init_bootinfo_pages_nr( void )
 {
 	size_t mmap_length = mb_info.mi_mmap_length;
@@ -273,5 +273,5 @@
 static uint32_t cpuN_booted __in_kdata;
 
-void start_secondary_cpus()
+void start_secondary_cpus( void )
 {
 	pt_entry_t flags = PG_V | PG_KW;
@@ -311,5 +311,5 @@
 }
 
-void init_x86_64_cpuN()
+void init_x86_64_cpuN( void )
 {
 	lid_t lid;
@@ -346,5 +346,5 @@
 /* -------------------------------------------------------------------------- */
 
-static void apic_map()
+static void apic_map( void )
 {
 	extern vaddr_t lapic_va, ioapic_va;
@@ -489,5 +489,5 @@
 }
 
-static void gdt_create()
+static void gdt_create( void )
 {
 	memset(&gdtstore, 0, PAGE_SIZE);
@@ -506,5 +506,5 @@
 }
 
-void cpu_load_gdt()
+void cpu_load_gdt( void )
 {
 	struct region_descriptor region;
@@ -519,5 +519,5 @@
 } idt_bitmap __in_kdata;
 
-int idt_slot_alloc()
+int idt_slot_alloc( void )
 {
 	size_t i;
@@ -556,5 +556,5 @@
 }
 
-static void idt_create()
+static void idt_create( void )
 {
 	extern uint64_t x86_traps[], x86_intrs[], x86_rsvd;
@@ -594,5 +594,5 @@
 }
 
-void cpu_load_idt()
+void cpu_load_idt( void )
 {
 	struct region_descriptor region;
@@ -671,5 +671,5 @@
 uint64_t cpu_features[4] __in_kdata;
 
-void cpu_identify()
+void cpu_identify( void )
 {
 	/*
Index: trunk/hal/x86_64/core/hal_internal.h
===================================================================
--- trunk/hal/x86_64/core/hal_internal.h	(revision 457)
+++ trunk/hal/x86_64/core/hal_internal.h	(revision 482)
@@ -33,12 +33,12 @@
 /* hal_init.c */
 void cpu_activate(uint32_t gid);
-int idt_slot_alloc();
+int idt_slot_alloc( void );
 void idt_slot_free(int slot);
 
 /* hal_cpu.S */
 void invlpg(vaddr_t va);
-void sti();
-void cli();
-uint64_t rdtsc();
+void sti( void );
+void cli( void );
+uint64_t rdtsc( void );
 uint8_t in8(uint32_t port);
 uint16_t in16(uint32_t port);
@@ -47,5 +47,5 @@
 uint64_t rdmsr(uint32_t);
 void wrmsr(uint32_t, uint64_t);
-void mfence();
+void mfence( void );
 uint64_t rcr0(void);
 vaddr_t rcr2(void);
@@ -55,10 +55,10 @@
 void lcr4(uint64_t);
 void cpuid(uint32_t eax, uint32_t ecx, uint32_t *desc);
-void tlbflushg();
-void tlbflush();
-void clts();
-void stts();
-void pause();
-void wbinvd();
+void tlbflushg( void );
+void tlbflush( void );
+void clts( void );
+void stts( void );
+void pause( void );
+void wbinvd( void );
 
 void cpu_context_switch(void *oldctx, void *newctx);
@@ -72,6 +72,6 @@
 paddr_t hal_gpt_bootstrap_palloc(size_t npages);
 vaddr_t hal_gpt_bootstrap_valloc(size_t npages);
-void hal_gpt_bootstrap_reset();
-size_t hal_gpt_bootstrap_uniformize();
+void hal_gpt_bootstrap_reset( void );
+size_t hal_gpt_bootstrap_uniformize( void );
 
 void hal_gpt_enter(vaddr_t va, paddr_t pa, pt_entry_t flags);
@@ -85,6 +85,6 @@
 
 /* x86_printf.c */
-void x86_lock();
-void x86_unlock();
+void x86_lock( void );
+void x86_unlock( void );
 
 void x86_panic(char *msg);
Index: trunk/hal/x86_64/core/hal_segmentation.h
===================================================================
--- trunk/hal/x86_64/core/hal_segmentation.h	(revision 457)
+++ trunk/hal/x86_64/core/hal_segmentation.h	(revision 482)
@@ -163,5 +163,5 @@
 void lidt(struct region_descriptor *);
 void ltr(uint16_t);
-tls_t *curtls();
+tls_t *curtls( void );
 
 #define INTRS_ENABLED	0xFFEFAAAA
Index: trunk/hal/x86_64/core/hal_special.c
===================================================================
--- trunk/hal/x86_64/core/hal_special.c	(revision 457)
+++ trunk/hal/x86_64/core/hal_special.c	(revision 482)
@@ -32,5 +32,5 @@
 struct thread_s;
 
-tls_t *curtls()
+tls_t *curtls( void )
 {
 	tls_t *cputls;
@@ -43,20 +43,20 @@
 }
 
-gid_t hal_get_gid()
+gid_t hal_get_gid( void )
 {
 	return curtls()->tls_gid;
 }
 
-cycle_t hal_time_stamp()
+cycle_t hal_time_stamp( void )
 {
 	return rdtsc();
 }
 
-inline reg_t hal_get_sr()
+inline reg_t hal_get_sr( void )
 {
 	return 0;
 }
 
-uint64_t hal_get_cycles()
+uint64_t hal_get_cycles( void )
 {
 	uint64_t cycles;
@@ -73,5 +73,5 @@
 }
 
-struct thread_s *hal_get_current_thread()
+struct thread_s *hal_get_current_thread( void )
 {
 	return curtls()->tls_thr;
@@ -85,5 +85,5 @@
 /* -------------------------------------------------------------------------- */
 
-void hal_fpu_enable()
+void hal_fpu_enable( void )
 {
 	/* FPU not implemented yet */
@@ -92,5 +92,5 @@
 }
 
-void hal_fpu_disable()
+void hal_fpu_disable( void )
 {
 	/* FPU not implemented yet */
@@ -99,5 +99,5 @@
 }
 
-uint32_t hal_get_stack()
+uint32_t hal_get_stack( void )
 {
 	x86_panic((char *)__func__);
@@ -111,5 +111,5 @@
 }
 
-uint32_t hal_get_bad_vaddr()
+uint32_t hal_get_bad_vaddr( void )
 {
 	x86_panic((char *)__func__);
@@ -128,15 +128,15 @@
 }
 
-void hal_fence()
+void hal_fence( void )
 {
 	mfence();
 }
 
-void hal_rdbar()
+void hal_rdbar( void )
 {
 	x86_panic((char *)__func__);
 }
 
-void hal_core_sleep()
+void hal_core_sleep( void )
 {
 	x86_panic((char *)__func__);
Index: trunk/hal/x86_64/core/x86_printf.c
===================================================================
--- trunk/hal/x86_64/core/x86_printf.c	(revision 457)
+++ trunk/hal/x86_64/core/x86_printf.c	(revision 482)
@@ -46,5 +46,5 @@
 static uint32_t x86_lock_val __in_kdata = 0;
 
-void x86_lock()
+void x86_lock( void )
 {
 	while (!hal_atomic_cas(&x86_lock_val, 0, 1)) {
@@ -53,5 +53,5 @@
 }
 
-void x86_unlock()
+void x86_unlock( void )
 {
 	while (!hal_atomic_cas(&x86_lock_val, 1, 0)) {
@@ -72,5 +72,5 @@
 }
 
-static void check_scroll()
+static void check_scroll( void )
 {
 	char *base = (char *)iom_base + (0xB8000 - IOM_BEGIN);
