Changeset 570 for trunk/hal/tsar_mips32/core
- Timestamp:
- Oct 5, 2018, 12:08:35 AM (6 years ago)
- Location:
- trunk/hal/tsar_mips32/core
- Files:
-
- 9 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/hal/tsar_mips32/core/hal_context.c
r492 r570 195 195 196 196 // get ppn of remote child process page table 197 uint32_t pt_ppn = hal_remote_l w( XPTR(child_cxy , &process->vmm.gpt.ppn) );197 uint32_t pt_ppn = hal_remote_l32( XPTR(child_cxy , &process->vmm.gpt.ppn) ); 198 198 199 199 // save CPU registers in local CPU context … … 245 245 hal_cpu_context_init( thread ); 246 246 247 // restore CPU registers ... and jump 247 // restore CPU registers ... and jump to user code 248 248 hal_do_cpu_restore( (hal_cpu_context_t *)thread->cpu_context ); 249 249 … … 263 263 264 264 // get relevant context slots values 265 uint32_t sp_29 = hal_remote_l w( XPTR( cxy , &ctx->sp_29 ) );266 uint32_t ra_31 = hal_remote_l w( XPTR( cxy , &ctx->ra_31 ) );267 uint32_t c0_sr = hal_remote_l w( XPTR( cxy , &ctx->c0_sr ) );268 uint32_t c0_epc = hal_remote_l w( XPTR( cxy , &ctx->c0_epc ) );269 uint32_t c0_th = hal_remote_l w( XPTR( cxy , &ctx->c0_th ) );270 uint32_t c2_ptpr = hal_remote_l w( XPTR( cxy , &ctx->c2_ptpr ) );271 uint32_t c2_mode = hal_remote_l w( XPTR( cxy , &ctx->c2_mode ) );265 uint32_t sp_29 = hal_remote_l32( XPTR( cxy , &ctx->sp_29 ) ); 266 uint32_t ra_31 = hal_remote_l32( XPTR( cxy , &ctx->ra_31 ) ); 267 uint32_t c0_sr = hal_remote_l32( XPTR( cxy , &ctx->c0_sr ) ); 268 uint32_t c0_epc = hal_remote_l32( XPTR( cxy , &ctx->c0_epc ) ); 269 uint32_t c0_th = hal_remote_l32( XPTR( cxy , &ctx->c0_th ) ); 270 uint32_t c2_ptpr = hal_remote_l32( XPTR( cxy , &ctx->c2_ptpr ) ); 271 uint32_t c2_mode = hal_remote_l32( XPTR( cxy , &ctx->c2_mode ) ); 272 272 273 273 printk("\n***** CPU context for thread %x in process %x / cycle %d\n" -
trunk/hal/tsar_mips32/core/hal_drivers.c
r550 r570 26 26 27 27 #include <soclib_tty.h> 28 #include <soclib_mt ty.h>28 #include <soclib_mty.h> 29 29 #include <soclib_pic.h> 30 30 #include <soclib_iob.h> 31 31 #include <soclib_bdv.h> 32 32 #include <soclib_hba.h> 33 #include <soclib_sdc.h>34 33 #include <soclib_mmc.h> 35 34 #include <soclib_nic.h> … … 51 50 uint32_t impl ) 52 51 { 53 switch (impl) {54 case IMPL_TXT_TTY :{52 if( impl == IMPL_TXT_TTY ) 53 { 55 54 soclib_tty_init( txt ); 56 break;57 55 } 58 case IMPL_TXT_MTY : {59 soclib_mtty_init( txt );60 break;56 else if (impl == IMPL_TXT_MTY ) 57 { 58 soclib_mty_init( txt ); 61 59 } 62 default : {63 assert( false, "bad implementation" );64 }60 else 61 { 62 assert( false, "undefined implementation" ); 65 63 } 66 64 } … … 74 72 uint32_t impl ) 75 73 { 76 assert( (impl == IMPL_PIC_SCL), " bad implementation" );74 assert( (impl == IMPL_PIC_SCL), "undefined implementation" ); 77 75 78 76 soclib_pic_init( pic ); … … 97 95 uint32_t impl ) 98 96 { 99 assert( (impl == IMPL_IOB_TSR), " bad implementation" );97 assert( (impl == IMPL_IOB_TSR), "undefined implementation" ); 100 98 101 99 soclib_iob_init( iob ); … … 126 124 soclib_hba_init( ioc ); 127 125 } 128 else if (impl == IMPL_IOC_SPI)129 130 soclib_sdc_init( ioc );131 }126 // else if (impl == IMPL_IOC_SPI) 127 // { 128 // soclib_sdc_init( ioc ); 129 // } 132 130 else 133 131 { … … 144 142 uint32_t impl ) 145 143 { 146 assert( (impl == IMPL_MMC_TSR), " bad implementation" );144 assert( (impl == IMPL_MMC_TSR), "undefined implementation" ); 147 145 148 146 soclib_mmc_init( mmc ); … … 157 155 uint32_t impl ) 158 156 { 159 assert( (impl == IMPL_NIC_CBF), " bad implementation" );157 assert( (impl == IMPL_NIC_CBF), "undefined implementation" ); 160 158 161 159 soclib_nic_init( nic ); … … 170 168 uint32_t impl ) 171 169 { 172 assert( (impl == IMPL_DMA_SCL), " bad implementation" );170 assert( (impl == IMPL_DMA_SCL), "undefined implementation" ); 173 171 174 172 soclib_dma_init( dma ); -
trunk/hal/tsar_mips32/core/hal_exception.c
r527 r570 35 35 #include <syscalls.h> 36 36 #include <shared_syscalls.h> 37 #include <remote_ spinlock.h>37 #include <remote_busylock.h> 38 38 #include <hal_kentry.h> 39 40 39 #include <hal_exception.h> 41 40 … … 340 339 error_t error ) 341 340 { 342 uint32_t save_sr;343 341 core_t * core = this->core; 344 342 process_t * process = this->process; … … 353 351 354 352 // get TXT0 lock in busy waiting mode 355 remote_ spinlock_lock_busy( lock_xp , &save_sr);353 remote_busylock_acquire( lock_xp ); 356 354 357 355 if( error == EXCP_USER_ERROR ) … … 366 364 } 367 365 368 nolock_printk(" local locks = %d / remote locks = %d / blocked_vector= %X\n\n",369 this-> local_locks, this->remote_locks, this->blocked);366 nolock_printk("busylocks = %d / blocked_vector = %X / flags = %X\n\n", 367 this->busylocks, this->blocked, this->flags ); 370 368 371 369 nolock_printk("c0_cr %X c0_epc %X c0_sr %X c0_th %X\n", … … 394 392 395 393 // release the lock 396 remote_ spinlock_unlock_busy( lock_xp , save_sr);394 remote_busylock_release( lock_xp ); 397 395 398 396 } // end hal_exception_dump() -
trunk/hal/tsar_mips32/core/hal_gpt.c
r492 r570 799 799 800 800 // get src_pte1 801 src_pte1 = hal_remote_l w( XPTR( src_cxy , &src_pt1[ix1] ) );801 src_pte1 = hal_remote_l32( XPTR( src_cxy , &src_pt1[ix1] ) ); 802 802 803 803 // do nothing if src_pte1 not MAPPED or not SMALL … … 844 844 845 845 // get attr and ppn from SRC_PT2 846 src_pte2_attr = hal_remote_l w( XPTR( src_cxy , &src_pt2[2 * ix2] ) );847 src_pte2_ppn = hal_remote_l w( XPTR( src_cxy , &src_pt2[2 * ix2 + 1] ) );846 src_pte2_attr = hal_remote_l32( XPTR( src_cxy , &src_pt2[2 * ix2] ) ); 847 src_pte2_ppn = hal_remote_l32( XPTR( src_cxy , &src_pt2[2 * ix2 + 1] ) ); 848 848 849 849 // do nothing if src_pte2 not MAPPED … … 1001 1001 1002 1002 // get PTE1 value 1003 pte1 = hal_remote_l w( XPTR( gpt_cxy , &pt1[ix1] ) );1003 pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); 1004 1004 1005 1005 // only MAPPED & SMALL PTEs are modified … … 1014 1014 1015 1015 // get current PTE2 attributes 1016 attr = hal_remote_l w( XPTR( gpt_cxy , &pt2[2*ix2] ) );1016 attr = hal_remote_l32( XPTR( gpt_cxy , &pt2[2*ix2] ) ); 1017 1017 1018 1018 // only MAPPED PTEs are modified … … 1020 1020 { 1021 1021 attr = (attr | TSAR_MMU_COW) & (~TSAR_MMU_WRITABLE); 1022 hal_remote_s w( XPTR( gpt_cxy , &pt2[2*ix2] ) , attr );1022 hal_remote_s32( XPTR( gpt_cxy , &pt2[2*ix2] ) , attr ); 1023 1023 } 1024 1024 } … … 1063 1063 1064 1064 // get PTE1 value 1065 pte1 = hal_remote_l w( XPTR( gpt_cxy , &pt1[ix1] ) );1065 pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); 1066 1066 1067 1067 if( (pte1 & TSAR_MMU_MAPPED) == 0 ) return; … … 1073 1073 1074 1074 // reset PTE2 1075 hal_remote_s w( XPTR( gpt_cxy, &pt2[2 * ix2] ) , 0 );1075 hal_remote_s32( XPTR( gpt_cxy, &pt2[2 * ix2] ) , 0 ); 1076 1076 hal_fence(); 1077 1077 1078 1078 // set PTE2 in this order 1079 hal_remote_s w( XPTR( gpt_cxy, &pt2[2 * ix2 + 1] ) , ppn );1079 hal_remote_s32( XPTR( gpt_cxy, &pt2[2 * ix2 + 1] ) , ppn ); 1080 1080 hal_fence(); 1081 hal_remote_s w( XPTR( gpt_cxy, &pt2[2 * ix2] ) , tsar_attr );1081 hal_remote_s32( XPTR( gpt_cxy, &pt2[2 * ix2] ) , tsar_attr ); 1082 1082 hal_fence(); 1083 1083 -
trunk/hal/tsar_mips32/core/hal_macros.h
r469 r570 28 28 // User-side, hardware dependant, macros definition. 29 29 // 30 // Any architecture specific implementation must implement thes macros.30 // Any architecture specific implementation must implement these macros. 31 31 ////////////////////////////////////////////////////////////////////////////////////////// 32 32 -
trunk/hal/tsar_mips32/core/hal_ppm.c
r457 r570 27 27 #include <hal_special.h> 28 28 #include <printk.h> 29 #include < spinlock.h>29 #include <busylock.h> 30 30 #include <process.h> 31 31 #include <ppm.h> … … 46 46 ////////////////////////////////////////////////////////////////////////////////////////// 47 47 48 48 49 /////////////////////////////////////////// 49 50 error_t hal_ppm_init( boot_info_t * info ) … … 59 60 60 61 // initialize lock protecting the free_pages[] lists 61 spinlock_init( &ppm->free_lock);62 busylock_init( &ppm->free_lock , LOCK_PPM_FREE ); 62 63 63 64 // initialize lock protecting the dirty_pages list 64 spinlock_init( &ppm->dirty_lock);65 queuelock_init( &ppm->dirty_lock , LOCK_PPM_DIRTY ); 65 66 66 67 // initialize all free_pages[] lists as empty -
trunk/hal/tsar_mips32/core/hal_remote.c
r501 r570 54 54 55 55 ///////////////////////////////// 56 void hal_remote_s w( xptr_t xp,56 void hal_remote_s32( xptr_t xp, 57 57 uint32_t data ) 58 58 { … … 80 80 81 81 ////////////////////////////////// 82 void hal_remote_s wd( xptr_t xp,82 void hal_remote_s64( xptr_t xp, 83 83 uint64_t data ) 84 84 { … … 113 113 void * pt ) 114 114 { 115 hal_remote_s w( xp , (uint32_t)pt );115 hal_remote_s32 ( xp , (uint32_t)pt ); 116 116 } 117 117 … … 143 143 144 144 //////////////////////////////////// 145 uint32_t hal_remote_l w( xptr_t xp )145 uint32_t hal_remote_l32( xptr_t xp ) 146 146 { 147 147 uint32_t data; … … 169 169 170 170 ///////////////////////////////////// 171 uint64_t hal_remote_l wd( xptr_t xp )171 uint64_t hal_remote_l64( xptr_t xp ) 172 172 { 173 173 uint32_t data_lsb; … … 200 200 void * hal_remote_lpt( xptr_t xp ) 201 201 { 202 return (void *)hal_remote_l w( xp );202 return (void *)hal_remote_l32 ( xp ); 203 203 } 204 204 -
trunk/hal/tsar_mips32/core/hal_special.c
r481 r570 32 32 struct thread_s; 33 33 34 ////////////////////////// 34 //////////////////////////////// 35 35 inline gid_t hal_get_gid( void ) 36 36 { … … 42 42 } 43 43 44 ///////////////////////////// 44 /////////////////////////////////// 45 45 inline reg_t hal_time_stamp( void ) 46 46 { … … 52 52 } 53 53 54 ///////////////////////// 54 /////////////////////////////// 55 55 inline reg_t hal_get_sr( void ) 56 56 { … … 62 62 } 63 63 64 ///////////////////////// 64 /////////////////////////////// 65 65 uint64_t hal_get_cycles( void ) 66 66 { … … 94 94 } 95 95 96 ///////////////////////////////////////////////// 96 /////////////////////////////////////////////////////// 97 97 inline struct thread_s * hal_get_current_thread( void ) 98 98 { … … 110 110 } 111 111 112 ///////////////////// 112 /////////////////////////// 113 113 void hal_fpu_enable( void ) 114 114 { … … 127 127 } 128 128 129 ////////////////////// 129 //////////////////////////// 130 130 void hal_fpu_disable( void ) 131 131 { … … 145 145 } 146 146 147 //////////////////////// 147 ////////////////////////////// 148 148 uint32_t hal_get_stack( void ) 149 149 { … … 168 168 } 169 169 170 //////////////////////////// 170 ////////////////////////////////// 171 171 uint32_t hal_get_bad_vaddr( void ) 172 172 { … … 201 201 } 202 202 203 //////////////// 204 void hal_fence( void )203 ///////////////////////////// 204 inline void hal_fence( void ) 205 205 { 206 206 asm volatile ("sync"); 207 207 } 208 208 209 //////////////// 210 void hal_rdbar( void )209 ///////////////////////////// 210 inline void hal_rdbar( void ) 211 211 { 212 212 asm volatile( "" ::: "memory" ); 213 213 } 214 214 215 ///////////////////// 215 /////////////////////////// 216 216 void hal_core_sleep( void ) 217 217 { -
trunk/hal/tsar_mips32/core/hal_vmm.c
r457 r570 64 64 } 65 65 66 // get lock protecting the VSL to found the "kentry" vseg67 remote_rwlock_wr_lock( XPTR( local_cxy , &vmm->vsegs_lock ));66 // get extended pointer on lock protecting the VSL 67 xptr_t lock_xp = XPTR( local_cxy , &vmm->vsegs_lock ); 68 68 69 // scan the VSL 69 // get VSL lock 70 remote_rwlock_wr_acquire( lock_xp ); 71 72 // scan the VSL to found the "kentry" vseg 70 73 xptr_t root_xp = XPTR( local_cxy , &vmm->vsegs_root ); 71 74 xptr_t iter_xp; 72 75 xptr_t vseg_xp; 73 76 vseg_t * vseg; 74 bool_t found = false; 77 bool_t found = false; 78 75 79 XLIST_FOREACH( root_xp , iter_xp ) 76 80 { … … 87 91 } 88 92 89 // release the lock protecting the VSL90 remote_rwlock_wr_ unlock( XPTR( local_cxy , &vmm->vsegs_lock ));93 // release the VSL lock 94 remote_rwlock_wr_release( lock_xp ); 91 95 92 96 if( found == false ) return error;
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