Changeset 6 for trunk/tools/arch_info
- Timestamp:
- Apr 26, 2017, 2:14:33 PM (8 years ago)
- Location:
- trunk/tools/arch_info
- Files:
-
- 4 edited
-
arch_classes.py (modified) (28 diffs)
-
arch_info.h (modified) (5 diffs)
-
boot_info.h (modified) (3 diffs)
-
genarch.py (modified) (5 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/tools/arch_info/arch_classes.py
r1 r6 13 13 # It handle 4 types of objects: clusters, cores, devices and irqs. 14 14 # - The number of cluster is variable (can be one). 15 # - The cluster topology can be a 2D mesh or a simpl aarray.15 # - The cluster topology can be a 2D mesh or a simple 1D array. 16 16 # - The number of cores per cluster is variable (can be zero). 17 17 # - The number of addressable devices per cluster is variable. … … 41 41 ######################################################################################### 42 42 # These arrays define the supported types of peripherals. 43 # They must be kept consistent with values defined in file arch_info.h.43 # They must be kept consistent with values defined in files arch_info.h & device.h. 44 44 ######################################################################################### 45 45 46 46 DEVICE_TYPES_STR = [ 47 'RAM', # 0 48 'DMA', # 1 49 'FBF', # 1 50 'IOB', # 3 51 'IOC_BDV', # 4 52 'IOC_HBA', # 5 53 'IOC_SDC', # 6 54 'IOC_SPI', # 7 55 'IOC_RDK', # 8 56 'MMC', # 9 57 'MWR_CPY', # 10 58 'MWR_GCD', # 11 59 'MWR_DCT', # 12 60 'NIC', # 13 61 'ROM', # 14 62 'SIM', # 15 63 'TIM', # 16 64 'TTY', # 17 65 'XCU', # 18 66 'PIC', # 19 67 'CMA', # 20 47 'RAM_SCL', # 0.0 48 'ROM_SCL', # 1.0 49 'FBF_SCL', # 2.0 50 'IOB_TSR', # 3.0 51 'IOC_BDV', # 4.0 52 'IOC_HBA', # 4.1 53 'IOC_SDC', # 4.2 54 'IOC_SPI', # 4.3 55 'IOC_RDK', # 4.4 56 'MMC_TSR', # 5.0 57 'DMA_SCL', # 6.0 58 'NIC_CBF', # 7.0 59 'TIM_SCL', # 8.0 60 'TXT_TTY', # 9.0 61 'ICU_XCU', # A.0 62 'PIC_TSR', # B.0 68 63 ] 69 64 70 65 DEVICE_TYPES_INT = [ 71 0x00000000, # 0 72 0x00010000, # 1 73 0x00020000, # 1 74 0x00030000, # 3 75 0x00040000, # 4 76 0x00040001, # 5 77 0x00040002, # 6 78 0x00040003, # 7 79 0x00040004, # 8 80 0x00050000, # 9 81 0x00060000, # 10 82 0x00060001, # 11 83 0x00060002, # 12 84 0x00070000, # 13 85 0x00080000, # 14 86 0x00090000, # 15 87 0x000A0000, # 16 88 0x000B0000, # 17 89 0x000C0000, # 18 90 0x000D0000, # 19 91 0x000E0000, # 20 66 0x00000000, # 0.0 67 0x00010000, # 1.0 68 0x00020000, # 1.0 69 0x00030000, # 3.0 70 0x00040000, # 4.0 71 0x00040001, # 4.1 72 0x00040002, # 4.2 73 0x00040003, # 4.3 74 0x00040004, # 4.4 75 0x00050000, # 5.0 76 0x00060000, # 6.0 77 0x00070000, # 7.0 78 0x00080000, # 8.0 79 0x00090000, # 9.0 80 0x000A0000, # A.0 81 0x000B0000, # B.0 92 82 ] 93 83 … … 104 94 x_width, # number of bits for x coordinate 105 95 y_width, # number of bits for y coordinate 106 irqs_per_core, # number or IRQs from XCU to one core96 irqs_per_core, # number or IRQs from ICU to one core 107 97 io_cxy, # IO cluster identifier 108 98 boot_cxy, # boot cluster identifier … … 186 176 ################################ add an input IRQ in a device 187 177 def addIrq( self, 188 dstdev, # destination device (PIC or XCU)178 dstdev, # destination device (PIC or ICU) 189 179 port, # input IRQ port index 190 180 srcdev, # source device … … 192 182 is_rx = False ): # I/O operation direction 193 183 194 assert (dstdev.ptype == ' XCU') or (dstdev.ptype == 'PIC')184 assert (dstdev.ptype == 'ICU_XCU') or (dstdev.ptype == 'PIC_TSR') 195 185 assert (port < dstdev.arg0) 196 186 … … 382 372 ram_size = 0 383 373 384 nb_cma = 0 385 cma_channels = 0 386 cma_base = 0xFFFFFFFFFFFFFFFF 387 cma_size = 0 388 389 nb_dma = 0 390 dma_channels = 0 391 dma_base = 0xFFFFFFFFFFFFFFFF 392 dma_size = 0 374 nb_rom = 0 375 rom_channels = 0 376 rom_base = 0xFFFFFFFFFFFFFFFF 377 rom_size = 0 393 378 394 379 nb_fbf = 0 … … 419 404 mmc_size = 0 420 405 421 nb_mwr = 0 422 mwr_channels = 0 423 mwr_base = 0xFFFFFFFFFFFFFFFF 424 mwr_size = 0 425 mwr_arg0 = 0 426 mwr_arg1 = 0 427 mwr_arg2 = 0 428 mwr_arg3 = 0 429 use_mwr_gcd = False 430 use_mwr_dct = False 431 use_mwr_cpy = False 406 nb_dma = 0 407 dma_channels = 0 408 dma_base = 0xFFFFFFFFFFFFFFFF 409 dma_size = 0 432 410 433 411 nb_nic = 0 … … 436 414 nic_size = 0 437 415 416 nb_sim = 0 417 sim_channels = 0 418 sim_base = 0xFFFFFFFFFFFFFFFF 419 sim_size = 0 420 421 nb_tim = 0 422 tim_channels = 0 423 tim_base = 0xFFFFFFFFFFFFFFFF 424 tim_size = 0 425 426 nb_txt = 0 427 txt_channels = 0 428 txt_base = 0xFFFFFFFFFFFFFFFF 429 txt_size = 0 430 431 nb_icu = 0 432 icu_channels = 0 433 icu_base = 0xFFFFFFFFFFFFFFFF 434 icu_size = 0 435 icu_arg0 = 0 436 438 437 nb_pic = 0 439 438 pic_channels = 0 … … 441 440 pic_size = 0 442 441 443 nb_rom = 0 444 rom_channels = 0 445 rom_base = 0xFFFFFFFFFFFFFFFF 446 rom_size = 0 447 448 nb_sim = 0 449 sim_channels = 0 450 sim_base = 0xFFFFFFFFFFFFFFFF 451 sim_size = 0 452 453 nb_tim = 0 454 tim_channels = 0 455 tim_base = 0xFFFFFFFFFFFFFFFF 456 tim_size = 0 457 458 nb_tty = 0 459 tty_channels = 0 460 tty_base = 0xFFFFFFFFFFFFFFFF 461 tty_size = 0 462 463 nb_xcu = 0 464 xcu_channels = 0 465 xcu_base = 0xFFFFFFFFFFFFFFFF 466 xcu_size = 0 467 xcu_arg0 = 0 468 469 nb_drom = 0 470 drom_channels = 0 471 drom_base = 0xFFFFFFFFFFFFFFFF 472 drom_size = 0 442 nb_rom = 0 443 rom_channels = 0 444 rom_base = 0xFFFFFFFFFFFFFFFF 445 rom_size = 0 473 446 474 447 # get devices attributes … … 476 449 for device in cluster.devices: 477 450 478 if ( device.ptype == 'RAM ' ):451 if ( device.ptype == 'RAM_SCL' ): 479 452 ram_base = device.base 480 453 ram_size = device.size … … 482 455 nb_ram +=1 483 456 484 elif ( device.ptype == 'CMA' ): 485 cma_base = device.base 486 cma_size = device.size 487 cma_channels = device.channels 488 nb_cma +=1 489 490 elif ( device.ptype == 'DMA' ): 491 dma_base = device.base 492 dma_size = device.size 493 dma_channels = device.channels 494 nb_dma +=1 495 496 elif ( device.ptype == 'FBF' ): 457 elif ( device.ptype == 'ROM_SCL' ): 458 rom_base = device.base 459 rom_size = device.size 460 rom_channels = device.channels 461 nb_rom +=1 462 463 elif ( device.ptype == 'FBF_SCL' ): 497 464 fbf_base = device.base 498 465 fbf_size = device.size … … 502 469 nb_fbf +=1 503 470 504 elif ( device.ptype == 'IOB ' ):471 elif ( device.ptype == 'IOB_TSR' ): 505 472 iob_base = device.base 506 473 iob_size = device.size … … 532 499 use_ioc_spi = True 533 500 nb_ioc += 1 534 535 501 elif ( device.ptype == 'IOC_RDK' ): 536 502 ioc_base = device.base … … 540 506 nb_ioc += 1 541 507 542 elif ( device.ptype == 'MMC ' ):508 elif ( device.ptype == 'MMC_TSR' ): 543 509 mmc_base = device.base 544 510 mmc_size = device.size … … 546 512 nb_mmc +=1 547 513 548 elif ( device.ptype == 'MWR_GCD' ): 549 mwr_base = device.base 550 mwr_size = device.size 551 mwr_channels = device.channels 552 mwr_arg0 = device.arg0 553 mwr_arg1 = device.arg1 554 mwr_arg2 = device.arg2 555 mwr_arg3 = device.arg3 556 use_mwr_gcd = True 557 nb_mwr +=1 558 elif ( device.ptype == 'MWR_DCT' ): 559 mwr_base = device.base 560 mwr_size = device.size 561 mwr_channels = device.channels 562 mwr_arg0 = device.arg0 563 mwr_arg1 = device.arg1 564 mwr_arg2 = device.arg2 565 mwr_arg3 = device.arg3 566 use_mwr_dct = True 567 nb_mwr +=1 568 elif ( device.ptype == 'MWR_CPY' ): 569 mwr_base = device.base 570 mwr_size = device.size 571 mwr_channels = device.channels 572 mwr_arg0 = device.arg0 573 mwr_arg1 = device.arg1 574 mwr_arg2 = device.arg2 575 mwr_arg3 = device.arg3 576 use_mwr_cpy = True 577 nb_mwr +=1 578 579 elif ( device.ptype == 'ROM' ): 580 rom_base = device.base 581 rom_size = device.size 582 rom_channels = device.channels 583 nb_rom +=1 584 585 elif ( device.ptype == 'DROM' ): 586 drom_base = device.base 587 drom_size = device.size 588 drom_channels = device.channels 589 nb_drom +=1 590 591 elif ( device.ptype == 'SIM' ): 592 sim_base = device.base 593 sim_size = device.size 594 sim_channels = device.channels 595 nb_sim +=1 596 597 elif ( device.ptype == 'NIC' ): 514 elif ( device.ptype == 'DMA_SCL' ): 515 dma_base = device.base 516 dma_size = device.size 517 dma_channels = device.channels 518 nb_dma +=1 519 520 elif ( device.ptype == 'NIC_CBF' ): 598 521 nic_base = device.base 599 522 nic_size = device.size … … 601 524 nb_nic +=1 602 525 603 elif ( device.ptype == 'PIC' ): 526 elif ( device.ptype == 'TIM_SCL' ): 527 tim_base = device.pseg.base 528 tim_size = device.pseg.size 529 tim_channels = device.channels 530 nb_tim +=1 531 532 elif ( device.ptype == 'TXT_TTY' ): 533 txt_base = device.base 534 txt_size = device.size 535 txt_channels = device.channels 536 nb_txt +=1 537 538 elif ( device.ptype == 'ICU_XCU' ): 539 icu_base = device.base 540 icu_size = device.size 541 icu_channels = device.channels 542 icu_arg0 = device.arg0 543 icu_arg1 = device.arg1 544 icu_arg2 = device.arg2 545 icu_arg3 = device.arg3 546 nb_icu +=1 547 548 elif ( device.ptype == 'PIC_TSR' ): 604 549 pic_base = device.base 605 550 pic_size = device.size 606 551 pic_channels = device.channels 607 552 nb_pic +=1 608 609 elif ( device.ptype == 'TIM' ):610 tim_base = device.pseg.base611 tim_size = device.pseg.size612 tim_channels = device.channels613 nb_tim +=1614 615 elif ( device.ptype == 'TTY' ):616 tty_base = device.base617 tty_size = device.size618 tty_channels = device.channels619 nb_tty +=1620 621 elif ( device.ptype == 'XCU' ):622 xcu_base = device.base623 xcu_size = device.size624 xcu_channels = device.channels625 xcu_arg0 = device.arg0626 xcu_arg1 = device.arg1627 xcu_arg2 = device.arg2628 nb_xcu +=1629 630 # no more than two access to external devices631 assert ( nb_fbf <= 2 )632 assert ( nb_cma <= 2 )633 assert ( nb_ioc <= 2 )634 assert ( nb_nic <= 2 )635 assert ( nb_tim <= 2 )636 assert ( nb_tty <= 2 )637 assert ( nb_pic <= 2 )638 553 639 554 # one and only one IOC controller … … 647 562 rdk_base = 0 648 563 rdk_size = 0 649 650 # only one type of MWR controller651 nb_mwr_types = 0652 if use_mwr_gcd: nb_mwr_types += 1653 if use_mwr_dct: nb_mwr_types += 1654 if use_mwr_cpy: nb_mwr_types += 1655 if ( nb_mwr > 0 ) : assert ( nb_mwr_types == 1 )656 564 657 565 # Compute total number of cores, devices and irqs … … 697 605 s += '/* Peripherals */\n' 698 606 s += '\n' 699 s += '#define NB_T TY_CHANNELS %d\n' % tty_channels607 s += '#define NB_TXT_CHANNELS %d\n' % txt_channels 700 608 s += '#define NB_IOC_CHANNELS %d\n' % ioc_channels 701 609 s += '#define NB_NIC_CHANNELS %d\n' % nic_channels 702 s += '#define NB_CMA_CHANNELS %d\n' % cma_channels703 610 s += '#define NB_TIM_CHANNELS %d\n' % tim_channels 704 s += '#define NB_DMA_CHANNELS %d\n' % dma_channels 705 s += '\n' 706 s += '#define USE_XCU %d\n' % ( nb_xcu != 0 ) 707 s += '#define USE_DMA %d\n' % ( nb_dma != 0 ) 708 s += '\n' 611 s += '\n' 612 s += '#define USE_ICU %d\n' % ( nb_icu != 0 ) 709 613 s += '#define USE_IOB %d\n' % ( nb_iob != 0 ) 710 614 s += '#define USE_PIC %d\n' % ( nb_pic != 0 ) 711 615 s += '#define USE_FBF %d\n' % ( nb_fbf != 0 ) 712 616 s += '#define USE_NIC %d\n' % ( nb_nic != 0 ) 617 s += '#define USE_DMA %d\n' % ( nb_dma != 0 ) 713 618 s += '\n' 714 619 s += '#define USE_IOC_BDV %d\n' % use_ioc_bdv … … 718 623 s += '#define USE_IOC_RDK %d\n' % use_ioc_rdk 719 624 s += '\n' 720 s += '#define USE_MWR_GCD %d\n' % use_mwr_gcd721 s += '#define USE_MWR_DCT %d\n' % use_mwr_dct722 s += '#define USE_MWR_CPY %d\n' % use_mwr_cpy723 s += '\n'724 625 s += '#define FBUF_X_SIZE %d\n' % fbf_arg0 725 626 s += '#define FBUF_Y_SIZE %d\n' % fbf_arg1 726 627 s += '\n' 727 s += '#define XCU_NB_HWI %d\n' % xcu_arg0 728 s += '#define XCU_NB_PTI %d\n' % xcu_arg1 729 s += '#define XCU_NB_WTI %d\n' % xcu_arg2 730 s += '#define XCU_NB_OUT %d\n' % xcu_channels 731 s += '\n' 732 s += '#define MWR_TO_COPROC %d\n' % mwr_arg0 733 s += '#define MWR_FROM_COPROC %d\n' % mwr_arg1 734 s += '#define MWR_CONFIG %d\n' % mwr_arg2 735 s += '#define MWR_STATUS %d\n' % mwr_arg3 628 s += '#define ICU_NB_HWI %d\n' % icu_arg0 629 s += '#define ICU_NB_PTI %d\n' % icu_arg1 630 s += '#define ICU_NB_WTI %d\n' % icu_arg2 631 s += '#define ICU_NB_OUT %d\n' % icu_arg3 736 632 s += '\n' 737 633 … … 741 637 s += '#define SEG_RAM_SIZE 0x%x\n' % ram_size 742 638 s += '\n' 743 s += '#define SEG_CMA_BASE 0x%x\n' % (cma_base & local_physical_mask) 744 s += '#define SEG_CMA_SIZE 0x%x\n' % cma_size 639 s += '#define SEG_FBF_BASE 0x%x\n' % (fbf_base & local_physical_mask) 640 s += '#define SEG_FBF_SIZE 0x%x\n' % fbf_size 641 s += '\n' 642 s += '#define SEG_IOB_BASE 0x%x\n' % (iob_base & local_physical_mask) 643 s += '#define SEG_IOB_SIZE 0x%x\n' % iob_size 644 s += '\n' 645 s += '#define SEG_IOC_BASE 0x%x\n' % (ioc_base & local_physical_mask) 646 s += '#define SEG_IOC_SIZE 0x%x\n' % ioc_size 647 s += '\n' 648 s += '#define SEG_MMC_BASE 0x%x\n' % (mmc_base & local_physical_mask) 649 s += '#define SEG_MMC_SIZE 0x%x\n' % mmc_size 745 650 s += '\n' 746 651 s += '#define SEG_DMA_BASE 0x%x\n' % (dma_base & local_physical_mask) 747 652 s += '#define SEG_DMA_SIZE 0x%x\n' % dma_size 748 653 s += '\n' 749 s += '#define SEG_FBF_BASE 0x%x\n' % (fbf_base & local_physical_mask)750 s += '#define SEG_FBF_SIZE 0x%x\n' % fbf_size751 s += '\n'752 s += '#define SEG_IOB_BASE 0x%x\n' % (iob_base & local_physical_mask)753 s += '#define SEG_IOB_SIZE 0x%x\n' % iob_size754 s += '\n'755 s += '#define SEG_IOC_BASE 0x%x\n' % (ioc_base & local_physical_mask)756 s += '#define SEG_IOC_SIZE 0x%x\n' % ioc_size757 s += '\n'758 s += '#define SEG_MMC_BASE 0x%x\n' % (mmc_base & local_physical_mask)759 s += '#define SEG_MMC_SIZE 0x%x\n' % mmc_size760 s += '\n'761 s += '#define SEG_MWR_BASE 0x%x\n' % (mwr_base & local_physical_mask)762 s += '#define SEG_MWR_SIZE 0x%x\n' % mwr_size763 s += '\n'764 654 s += '#define SEG_ROM_BASE 0x%x\n' % (rom_base & local_physical_mask) 765 655 s += '#define SEG_ROM_SIZE 0x%x\n' % rom_size … … 777 667 s += '#define SEG_TIM_SIZE 0x%x\n' % tim_size 778 668 s += '\n' 779 s += '#define SEG_T TY_BASE 0x%x\n' % (tty_base & local_physical_mask)780 s += '#define SEG_T TY_SIZE 0x%x\n' % tty_size781 s += '\n' 782 s += '#define SEG_ XCU_BASE 0x%x\n' % (xcu_base & local_physical_mask)783 s += '#define SEG_ XCU_SIZE 0x%x\n' % xcu_size669 s += '#define SEG_TXT_BASE 0x%x\n' % (txt_base & local_physical_mask) 670 s += '#define SEG_TXT_SIZE 0x%x\n' % txt_size 671 s += '\n' 672 s += '#define SEG_ICU_BASE 0x%x\n' % (icu_base & local_physical_mask) 673 s += '#define SEG_ICU_SIZE 0x%x\n' % icu_size 784 674 s += '\n' 785 675 s += '#define SEG_RDK_BASE 0x%x\n' % (rdk_base & local_physical_mask) 786 676 s += '#define SEG_RDK_SIZE 0x%x\n' % rdk_size 787 s += '\n'788 s += '#define SEG_DROM_BASE 0x%x\n' % (drom_base & local_physical_mask)789 s += '#define SEG_DROM_SIZE 0x%x\n' % drom_size790 677 s += '\n' 791 678 s += '#endif\n' … … 931 818 self.arg2 = arg2 # optional (semantic depends on ptype) 932 819 self.arg3 = arg3 # optional (semantic depends on ptype) 933 self.irqs = [] # set of input IRQs (for PIC and XCU only)820 self.irqs = [] # set of input IRQs (for PIC and ICU only) 934 821 self.irq_ctrl = None # interrupt controller for this device 935 822 return … … 946 833 s += ' arg2="%d"' % self.arg2 947 834 s += ' arg3="%d"' % self.arg3 948 if ( (self.ptype == 'PIC ') or (self.ptype == 'XCU') ):835 if ( (self.ptype == 'PIC_TSR') or (self.ptype == 'ICU_XCU') ): 949 836 s += ' >\n' 950 837 for irq in self.irqs: s += irq.xml() … … 958 845 959 846 if ( verbose ): 960 print '*** cbin for device[%d] / type %s' \961 % (self.index , self.ptype )847 print '*** cbin for device[%d] / type = %s / base = %x' \ 848 % (self.index , self.ptype , self.base) 962 849 963 850 # check index … … 985 872 986 873 byte_stream = bytearray() 987 byte_stream += mapping.int2bytes(4,ptype_id) # device type988 874 byte_stream += mapping.int2bytes(8,self.base) # segment base address 989 875 byte_stream += mapping.int2bytes(8,self.size) # segment size 876 byte_stream += mapping.int2bytes(4,ptype_id) # device type 990 877 byte_stream += mapping.int2bytes(4,self.channels) # number of channels 991 878 byte_stream += mapping.int2bytes(4,self.arg0) # optionnal arg0 … … 997 884 998 885 if ( verbose ): 999 print 'ptype = %d' % ptype_id1000 886 print 'base = %x' % self.base 1001 887 print 'size = %x' % self.size … … 1034 920 1035 921 if ( verbose ): 1036 print '*** cbin for irq[%d] / type= %s' \1037 % (self. index , self.isrtype)922 print '*** cbin for irq[%d] / src_dev = %s' \ 923 % (self.port , self.dev.ptype) 1038 924 1039 925 # check index … … 1041 927 print '[genarch error] in Irq.cbin()' 1042 928 print ' irq global index = %d / expected = %d' \ 1043 % (self.index ,expected)929 % (self.index , expected) 1044 930 sys.exit(1) 1045 931 -
trunk/tools/arch_info/arch_info.h
r1 r6 63 63 * The 16 MSB bits define the functionnal type. 64 64 * The 16 LSB bits define the implementation type. 65 * It must be consistent with values defined in file arch_class.py65 * It must be consistent with values defined in files arch_class.py, and device.* 66 66 ***************************************************************************************/ 67 67 68 68 enum deviceTypes 69 69 { 70 DEV_TYPE_RAM 71 DEV_TYPE_ DMA= 0x00010000,72 DEV_TYPE_FBF 73 DEV_TYPE_IOB 70 DEV_TYPE_RAM_SCL = 0x00000000, 71 DEV_TYPE_ROM_SCL = 0x00010000, 72 DEV_TYPE_FBF_SCL = 0x00020000, 73 DEV_TYPE_IOB_TSR = 0x00030000, 74 74 DEV_TYPE_IOC_BDV = 0x00040000, 75 75 DEV_TYPE_IOC_HBA = 0x00040001, … … 77 77 DEV_TYPE_IOC_SPI = 0x00040003, 78 78 DEV_TYPE_IOC_RDK = 0x00040004, 79 DEV_TYPE_MMC = 0x00050000, 80 DEV_TYPE_MWR_CPY = 0x00060000, 81 DEV_TYPE_MWR_GCD = 0x00060001, 82 DEV_TYPE_MWR_DCT = 0x00060002, 83 DEV_TYPE_NIC = 0x00070000, 84 DEV_TYPE_ROM = 0x00080000, 85 DEV_TYPE_SIM = 0x00090000, 86 DEV_TYPE_TIM = 0x000A0000, 87 DEV_TYPE_TTY = 0x000B0000, 88 DEV_TYPE_XCU = 0x000C0000, 89 DEV_TYPE_PIC = 0x000D0000, 90 DEV_TYPE_CMA = 0x000E0000, 79 DEV_TYPE_MMC_TSR = 0x00050000, 80 DEV_TYPE_DMA_SCL = 0x00060000, 81 DEV_TYPE_NIC_CBF = 0x00070000, 82 DEV_TYPE_TIM_SCL = 0x00080000, 83 DEV_TYPE_TXT_TTY = 0x00090000, 84 DEV_TYPE_ICU_XCU = 0x000A0000, 85 DEV_TYPE_PIC_TSR = 0x000B0000, 91 86 }; 92 87 … … 143 138 { 144 139 uint32_t gid; // core hardware identifier 140 uint16_t cxy; // cluster identifier 145 141 uint16_t lid; // core local index in cluster 146 uint16_t cxy; // cluster identifier147 142 } 148 143 archinfo_core_t; … … 154 149 typedef struct __attribute__((packed)) archinfo_device_s 155 150 { 151 uint64_t base; // base address in physical space 152 uint64_t size; // channel size (bytes) 156 153 uint32_t type; // supported values defined above 157 uint64_t base; // base address in physical space158 uint64_t size; // size (bytes)159 154 uint32_t channels; // number of channels 160 155 uint32_t arg0; // semantic depends on device type … … 162 157 uint32_t arg2; // semantic depends on device type 163 158 uint32_t arg3; // semantic depends on device type 164 uint32_t irqs; // number of input IRQs (for XCU or PIC)159 uint32_t irqs; // number of input IRQs (for ICU or PIC) 165 160 uint32_t irq_offset; // global index of first IRQ 166 161 } -
trunk/tools/arch_info/boot_info.h
r1 r6 32 32 ********************************************************************************************/ 33 33 34 #define BOOT_INFO_SIGNATURE 0x BABEF00D34 #define BOOT_INFO_SIGNATURE 0x12344321 35 35 36 36 /********************************************************************************************* … … 69 69 typedef struct boot_device_s 70 70 { 71 uint64_t base; /*! segment physical base address */ 72 uint64_t size; /*! channel size (bytes) */ 71 73 uint32_t type; /*! peripheral type (func | impl) */ 72 xptr_t base; /*! segment global base address */73 uint64_t size; /*! channel size (bytes) */74 74 uint32_t channels; /*! number of channels */ 75 75 uint32_t param0; /*! semantic depends on peripherat type */ … … 90 90 typedef struct boot_info_s 91 91 { 92 uint32_t signature; /*! boot info signature*/92 uint32_t signature; /*! boot info signature */ 93 93 94 94 // global platform parameters 95 95 96 uint32_t paddr_width; /*! number of bits in physical address*/97 uint32_t x_width; /*! number of bits to code X coordinate*/98 uint32_t y_width; /*! number of bits to code Y coordinate*/99 uint32_t x_size; /*! number of cluster in a row*/100 uint32_t y_size; /*! number of cluster in a column*/101 uint32_t io_cxy; /*! IO cluster identifier*/96 uint32_t paddr_width; /*! number of bits in physical address */ 97 uint32_t x_width; /*! number of bits to code X coordinate */ 98 uint32_t y_width; /*! number of bits to code Y coordinate */ 99 uint32_t x_size; /*! number of cluster in a row */ 100 uint32_t y_size; /*! number of cluster in a column */ 101 uint32_t io_cxy; /*! IO cluster identifier */ 102 102 103 // s pecific cluster parameters103 // shared resources 104 104 105 uint32_t cxy; /*! current cluster identifier */ 106 uint32_t cores_nr; /*! number of cores in current cluster */ 107 boot_core_t core[CONFIG_MAX_CORES_PER_CLUSTER]; /* array of core descriptors */ 108 uint32_t devices_nr; /*! number of peripherals in current cluster */ 109 boot_device_t dev[CONFIG_MAX_DEVICES_PER_CLUSTER]; /* array of device descriptors */ 110 uint32_t pages_nr; /*! total number of 4 Kbytes pages in cluster */ 111 uint32_t pages_offset; /*! number of pages already allocated for kernel */ 105 uint32_t ext_dev_nr; /*! number of external peripherals */ 106 boot_device_t ext_dev[CONFIG_MAX_EXT_DEV]; /*! array of external peripherals */ 107 108 // private resources (per cluster) 109 110 uint32_t cxy; /*! cluster identifier */ 111 uint32_t cores_nr; /*! number of local cores in */ 112 boot_core_t core[CONFIG_MAX_LOCAL_CORES]; /*! array of core descriptors */ 113 uint32_t int_dev_nr; /*! number of local peripherals */ 114 boot_device_t int_dev[CONFIG_MAX_INT_DEV]; /*! array of internal peripherals */ 115 uint32_t pages_nr; /*! number of 4 Kbytes pages */ 116 uint32_t pages_offset; /*! number of pages allocated for kernel */ 112 117 113 118 // kernel segments 114 119 115 intptr_t kernel_code_start; /*! kernel code base address*/116 intptr_t kernel_code_end; /*! kernel code last address (excluded)*/117 intptr_t kernel_data_start; /*! kernel data base address*/118 intptr_t kernel_data_end; /*! kernel data last address (excluded)*/120 intptr_t kernel_code_start; /*! kernel code base address */ 121 intptr_t kernel_code_end; /*! kernel code last address (excluded) */ 122 intptr_t kernel_data_start; /*! kernel data base address */ 123 intptr_t kernel_data_end; /*! kernel data last address (excluded) */ 119 124 } 120 125 boot_info_t; -
trunk/tools/arch_info/genarch.py
r1 r6 23 23 # --nb_ttys=int : number of TTY channels 24 24 # --nb_nics=int : number of NIC channels 25 # --nb_cmas=int : number of CMA channels26 25 # --fbf_size=int : frame buffer width & heigth 27 26 # --ioc_type=string : can be IOC_BDV , IOC_HBA , IOC_SDC , IOC_SPI 28 # --mwr_type=string : can be MWR_GCD , MWR_DCT , MWR_CPY29 27 # --io_cxy=int : IO cluster identifier 30 28 # --boot_cxy=int : boot cluster identifier … … 76 74 help = 'define number ot NIC channels' ) 77 75 78 parser.add_option( '--nb_cmas', type = 'int', dest = 'nb_cmas',79 default = 2,80 help = 'define number ot CMA channels' )81 82 76 parser.add_option( '--fbf_size', type = 'int', dest = 'fbf_size', 83 77 default = 128, … … 87 81 default = 'IOC_BDV', 88 82 help = 'define type of IOC: BDV / HBA / SDC / RDK / SPI' ) 89 90 parser.add_option( '--mwr_type', type = 'string', dest = 'mwr_type',91 default = 'MWR_CPY',92 help = 'define type of COPROC: CPY / DCT / GCD' )93 83 94 84 parser.add_option( '--io_cxy', type = 'int', dest = 'io_cxy', … … 129 119 fbf_size = options.fbf_size # frame buffer width & heigth 130 120 nb_nics = options.nb_nics # number of NIC channels 131 nb_cmas = options.nb_cmas # number of CMA channels132 121 ioc_type = options.ioc_type # ioc controller type 133 mwr_type = options.mwr_type # hardware coprocessor type134 122 io_cxy = options.io_cxy # IO cluster identifier 135 123 boot_cxy = options.boot_cxy # boot cluster identifier … … 163 151 nb_ttys, 164 152 nb_nics, 165 nb_cmas,166 153 fbf_size, 167 154 ioc_type, 168 mwr_type,169 155 io_cxy, 170 156 boot_cxy,
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