Index: trunk/hal/tsar_mips32/drivers/soclib_nic.h
===================================================================
--- trunk/hal/tsar_mips32/drivers/soclib_nic.h	(revision 451)
+++ trunk/hal/tsar_mips32/drivers/soclib_nic.h	(revision 658)
@@ -2,5 +2,5 @@
  * soclib_nic.h - SOCLIB_NIC (Network Interface Controler) driver definition.
  *
- * Author    Alain Greiner (2016)
+ * Author    Alain Greiner (2016,2017,2018,2019,2020)
  *
  * Copyright (c) UPMC Sorbonne Universites
@@ -30,53 +30,53 @@
 /********************************************************************************************
  * This driver supports the Soclib VciMasterNic component, that is a GMII compliant
- * multi-channels Gigabit Ethernet controler. 
- *
- * The VciMasterNic component supports up to 4 channels, indexed by the source IP address
- * for the RX packets, and by the destination IP address for the TX packets. 
+ * multi-channels Gigabit Ethernet controler with a DMA capability. 
+ *
+ * To improve the throughput, this component supports several channels.
+ * The channel index is derived from the (source) remote IP address and port
+ * for the received (RX) packets, and from the (destination) remote IP address
+ * and port for the sent (TX) packets. The actual number of channels is an 
+ * hardware parameter that cannot be larger than 8.
+ *
+ * The Ethernet packet length can have any value, in range [42,1538] bytes.
  * 
- * The Ethernet packet length can have any value, between 64 to 1538 bytes.
- * The data transfer unit between software and the NIC is a 4 Kbytes "container",
- * containing an integer number of variable size packets.
- *
- * The max number of packets in a container is 66 packets.
- * The first 34 words of a container are the container header :
- *
- *     word0  	| 	NB_WORDS	|	NB_PACKETS	|
- *     word1	|	PLEN[0]		|	PLEN[1]		|
- *      ...	    |	.......		|	........	|
- *     word33	|	PLEN[64]	|	PLEN[65]	|
- *
- *  - NB_PACKETS is the actual number of packets in the container.
- *	- NB_WORDS   is the number of useful words in the container.
- *	- PLEN[i]    is the number of bytes for the packet[i].
- *
- * Packets are stored in the (1024 - 34) following words, and the packets are word-aligned.
- *
- * The TX and RX queues are implemented as chained buffers, where each buffer is a 4 Kbytes
- * container. Each container is protected by a SET/RESET synchronisation variable. 
- * The structure implementing the chbuf descriptor is described below.
- *
- * To access both the container status, and the data contained in the container, the NIC
- * uses two physical addresses, that are packed in a 64 bits "container descriptor". 
- * - desc[25:0]  contain bits[31:6] of the status physical address.
- * - desc[51:26] contain bits[31:6] of the buffer physical address.
- * - desc[63:52] contain the common 12 physical address extension bits.
- *******************************************************************************************/
-
-/********************************************************************************************
- *       Addressable registers offsets 
+ * For each channel, the received packets (RX) and the sent packets (TX) are stored
+ * in two memory mapped software FIFOs, called NIC_TX_QUEUE and NIC_RX_QUEUE, implemented
+ * as chained buffers (chbuf). Each slot in these FIFOs is a container, containing one
+ * single packet. The number of containers, defining the queue depth, is a software defined 
+ * parameter. The data transfer unit between is a container (one single packet).
+ *
+ * - The "container" structure contains a 2040 bytes data buffer, the packet length, and
+ *   the container state : full (owned by the reader) / empty (owned by the writer).
+ *   For each container, the state variable is used as a SET/RESET flip-flop to synchronize 
+ *   the software server thread, and the hardware NIC DMA engines. 
+ *
+ * - The "chbuf" descriptor contains an array of local pointers on the containers, used 
+ *   by the software driver, an array of physical addresses, used by the DMA engines and
+ *   two "pointers", defining the current container to be written (wid) by the writer,
+ *   and the current container to be read (rid) by the reader.
+ *
+ * WARNING : Both the chbuf descriptor (containing the <rid> and wid> indexes), and the
+ *           containers themselve containing the <data> and the <sts> are shared variables
+ *           accessed by the server threads (accessing the L2 caches), and by the NIC_DMA
+ *           engines (accessing directly the L3 caches).
+ *           Therefore, the L2/L3 cache coherence must be handled by this NIC driver for
+ *           the INIT, READ & WRITE commands, using the MMC SYNC & INVAL commands.  
+ *******************************************************************************************/
+
+/********************************************************************************************
+ *   This section defines the NIC device addressable registers offsets:
+ * - The 8 channels registers are stored in the first 512 bytes (8 * 64 bytes).
+ * - The global registers are stored in the next 256 bytes (global offset is 512 bytes).
+ *   All values defined below are number of words (one word = 4 bytes).  
  *******************************************************************************************/
 
 enum SoclibMasterNicGlobalRegisters 
 {
-    NIC_G_RUN                        = 0,   /*! read_write : NIC component activated       */
-    NIC_G_NB_CHANNELS                = 1,   /*! read_only  : number of channels            */
-    NIC_G_BC_ENABLE                  = 2,   /*! read_write : broadcast enabled if non zero */ 
-    NIC_G_PERIOD                     = 3,   /*! read-write : container status poll period  */
-    NIC_G_MAC_4                      = 4,   /*! read-write : mac address 32 LSB bits       */
-    NIC_G_MAC_2                      = 5,   /*! read-write : mac address 16 MSB bits       */
+    NIC_G_CHANNELS                   = 1,   /*! read_only  : number of channels            */
+    NIC_G_NPKT_RESET                 = 2,   /*! write-only : reset packets counters        */
 
     NIC_G_NPKT_RX_G2S_RECEIVED       = 10,  /*! number of packets received                 */
     NIC_G_NPKT_RX_G2S_DISCARDED      = 11,  /*! number of RX packets discarded by RX_G2S   */
+
     NIC_G_NPKT_RX_DES_SUCCESS        = 12,  /*! number of RX packets transmited by RX_DES  */
     NIC_G_NPKT_RX_DES_TOO_SMALL      = 13,  /*! number of discarded too small RX packets   */
@@ -84,71 +84,90 @@
     NIC_G_NPKT_RX_DES_MFIFO_FULL     = 15,  /*! number of discarded RX packets fifo full   */
     NIC_G_NPKT_RX_DES_CRC_FAIL       = 16,  /*! number of discarded RX packets CRC32       */
-    NIC_G_NPKT_RX_DISPATCH_RECEIVED  = 17,  /*! number of packets received by RX_DISPATCH  */
-    NIC_G_NPKT_RX_DISPATCH_BROADCAST = 18,  /*! number of broadcast RX packets received    */
-    NIC_G_NPKT_RX_DISPATCH_DST_FAIL  = 19,  /*! number of discarded RX packets for DST MAC */
-    NIC_G_NPKT_RX_DISPATCH_CH_FULL   = 20,  /*! number of discarded RX packets cont full   */
-
-    NIC_G_NPKT_TX_DISPATCH_RECEIVED  = 41,  /*! number of packets received by TX_DISPATCH  */
-    NIC_G_NPKT_TX_DISPATCH_TOO_SMALL = 42,  /*! number of discarded too small TX packets   */
-    NIC_G_NPKT_TX_DISPATCH_TOO_BIG   = 43,  /*! number of discarded too big TX packets     */
-    NIC_G_NPKT_TX_DISPATCH_SRC_FAIL  = 44,  /*! number of discarded TX packets for SRC MAC */
-    NIC_G_NPKT_TX_DISPATCH_BROADCAST = 45,  /*! number of broadcast TX packets received    */
-    NIC_G_NPKT_TX_DISPATCH_TRANSMIT  = 46,  /*! number of transmit TX packets              */
-
-    NIC_GLOBAL_SPAN                  = 64   /*! 256 bytes for global registers             */
+
+    NIC_G_NPKT_RX_DISP_RECEIVED      = 17,  /*! number of packets received by RX_DISPATCH  */
+    NIC_G_NPKT_RX_DISP_DST_FAIL      = 18,  /*! number of discarded RX packets for DST MAC */
+    NIC_G_NPKT_RX_DISP_CH_FULL       = 19,  /*! number of discarded RX packets cont full   */
+
+    NIC_G_NPKT_TX_DISP_RECEIVED      = 41,  /*! number of packets received by TX_DISPATCH  */
+    NIC_G_NPKT_TX_DISP_TOO_SMALL     = 42,  /*! number of discarded too small TX packets   */
+    NIC_G_NPKT_TX_DISP_TOO_BIG       = 43,  /*! number of discarded too big TX packets     */
+    NIC_G_NPKT_TX_DISP_TRANSMIT      = 44,  /*! number of discarded TX packets for SRC MAC */
+
+    NIC_GLOBAL_OFFSET                = 128, /*! 512  bytes reserved for channel registers  */
 };
 
 enum SoclibMasterNicChannelRegisters 
 {
-    NIC_RX_STATUS             = 0,    /*! read-only  : RX channel status                   */
-    NIC_RX_CHBUF_DESC_L0      = 1,    /*! read-write : RX chbuf descriptor 32 LSB bits     */ 
-    NIC_RX_CHBUF_DESC_HI      = 2,    /*! read-write : RX chbuf descriptor 32 MSB bits     */ 
+    NIC_RX_CHANNEL_RUN        = 0,    /*! write-only : RX channel activation/desactivation */
+    NIC_RX_CHBUF_DESC_LO      = 1,    /*! read-write : RX chbuf descriptor 32 LSB bits     */
+    NIC_RX_CHBUF_DESC_HI      = 2,    /*! read-write : RX chbuf descriptor 32 MSB bits     */
     NIC_RX_CHBUF_NBUFS        = 3,    /*! read-write : RX chbuf depth (number of buffers)  */
-    
-    NIC_TX_STATUS             = 8,    /*! read-only  : TX channel status                   */
-    NIC_TX_CHBUF_DESC_L0      = 9,    /*! read-write : TX chbuf descriptor 32 LSB bits     */ 
-    NIC_TX_CHBUF_DESC_HI      = 10,   /*! read-write : TX chbuf descriptor 32 MSB bits     */ 
+    NIC_RX_CHANNEL_STATE      = 4,    /*! read-only  : RX channel status                   */
+
+    NIC_TX_CHANNEL_RUN        = 8,    /*! write-only : TX channel activation               */
+    NIC_TX_CHBUF_DESC_LO      = 9,    /*! read-write : TX chbuf descriptor 32 LSB bits     */
+    NIC_TX_CHBUF_DESC_HI      = 10,   /*! read-write : TX chbuf descriptor 32 MSB bits     */
     NIC_TX_CHBUF_NBUFS        = 11,   /*! read-write : TX chbuf depth (number of buffers)  */
+    NIC_TX_CHANNEL_STATE      = 12,   /*! read-only  : TX channel status                   */
 
     NIC_CHANNEL_SPAN          = 16    /*! 64 bytes per channel                             */
 };
-    
-
-
-/********************************************************************************************
- * This structure defines the chained buffer descriptor, used to implement both
- * the RX and TX packets queues. Each buffer in a chbuf is a 4 Kbytes container
- * containing a variable number of packets. All containers are allocated in 
- * the same cluster as the associated NIC device descriptor. The chbuf descriptor contains:
- * - an array of container pointers cont[], used by the kernet threads to access the
- *   packets contained in the containers.
- * - an array of set/reset Boolean full[] used by both the software threads and 
- *   by the hardware FSMs for lock-less synchronisation. 
- * - an array of containers descriptors containing the physical addresses of the
- *   "full[i]" and "cont[i]" variables, used by the DMA FSMs. 
- * Moreover, It contains three pointers (cont_id, pkt_id, and word_id) that are private
- * variables used by the software thread to scan the chbuf. 
- *******************************************************************************************/
+
+/********************************************************************************************
+ *  Return values for the RX/TX channel master FSM status
+ *******************************************************************************************/
+
+enum SoclibMasterNicStatusValues
+{
+    NIC_CHANNEL_STATUS_IDLE  = 0,
+    NIC_CHANNEL_STATUS_ERROR = 1,
+    NIC_CHANNEL_STATUS_BUSY  = 2,     // busy for any value >= 2
+};
+
+/********************************************************************************************
+ * This structure defines the chbuf descriptor, used to implement both the RX and TX packets
+ * queues. Each container contains one single packet, and has only two states (full/empty).
+ * All containers are allocated in the same cluster as the associated NIC chdev descriptor.
+ * The chbuf descriptor contains:
+ * - an array of containers physical addresses cont_pad[], used by the DMA engines.
+ * - an array of container pointers cont_ptr[], used by the kernel threads.
+ * - two indexes rid and wid, defining the next container for read & write respectively.
+ * WARNING : dont modify this structure, used by the DMA engines.
+ *******************************************************************************************/
+
+#define SOCLIB_NIC_CHBUF_DEPTH   8
 
 typedef struct nic_chbuf_s
 {
-    uint32_t * cont[CONFIG_NIC_CHBUF_DEPTH]; /*! container virtual base address            */
-    uint32_t   full[CONFIG_NIC_CHBUF_DEPTH]; /*! Boolean : container full if non zero      */
-    uint64_t   desc[CONFIG_NIC_CHBUF_DEPTH]; /*! container & status physical addresses     */
-    uint32_t   cont_id;                      /*! current container index                   */
-    uint32_t   pkt_id;                       /*! current packet index in container         */
-    uint32_t   word_id;                      /*! first word of current packet              */
+    uint32_t   wid;                              /*! current container write index         */
+    uint32_t   rid;                              /*! current container read index          */
+    uint64_t   cont_pad[SOCLIB_NIC_CHBUF_DEPTH]; /*! containers physical base addresses    */
+    uint32_t * cont_ptr[SOCLIB_NIC_CHBUF_DEPTH]; /*! containers virtual base addresses     */
 }
 nic_chbuf_t;
 
 /********************************************************************************************
- *        SOCLIB_NIC driver access functions 
- *******************************************************************************************/
-
-/********************************************************************************************
- * This function initializes the SOCLIB_NIC hardware registers, allocates memory for
- * the RX and TX containers, allocates and initializes the RX and TX chbuf descriptors.
+ * This structure defines the container descriptor format.
+ *******************************************************************************************/
+
+typedef struct nic_cont_s
+{
+    uint8_t    buf[2040];                        /*! Ethernet packet (42 to 1538 bytes     */
+    uint32_t   length;                           /*! actual packet length in bytes         */
+    uint32_t   state;                            /*! zero == empty / non zero == full      */
+}
+nic_cont_t;
+
+/********************************************************************************************
+ *    Driver access functions 
+ *******************************************************************************************/
+
+/********************************************************************************************
+ * This function initializes the SOCLIB_NIC hardware registers, for one NIC chdev 
+ * (one direction of one channel). It allocates memory for the RX and TX containers,
+ * it allocates and initializes the RX and TX chbuf descriptors.
  * It allocates one WTI mailbox for the IRQ signaling availability of an RX full container,
  * or a TX empty container, and route the WTI IRQ to the core running the server thread.
+ * It activates the TX and RX DMA engines.
  ********************************************************************************************
  * @ chdev  :  pointer on NIC chdev descriptor.
@@ -157,42 +176,46 @@
 
 /********************************************************************************************
- * This function implement the READ / WRITE / READABLE / WRITABLE commands for TX/RX queues.
- * These command don't access the NIC peripheral but only the TX and TX chbufs.
- * It must be executed by a dedicated kernel thread running in the cluster containing
- * the CHBUF implementing the TX/RX queues.
- * It implements also the SET_MAC, SET_BC, SET_RUN configuration commands, that directly
- * access the NIC peripheral registers.
- * - READABLE 
- *   Returns in the command "status" a non zero value if a packet is available in RX queue.
- *   Update the RX queue read pointer if required.
- * - READ 
- *   Move a packet from the RX queue to the command "buffer", and returns the packet
- *   "length" in the command. The READABLE command must be called before the READ command.
- * - WRITABLE 
- *   Returns in the command "status" a non zero value if a packet with a given "length"
- *   can be written in the TX queue. Update the RX queue read pointer if required.
- * - WRITE
+ * 1) This function implement the READ & WRITE commands, used by the local server threads
+ *    to access the NIC_TX & NIC_RX packets queues. These commands don't access the NIC 
+ *    registers but only the TX and RX chbufs implementing the queues:
+ *
+ * <READ>
+ *   Move a packet from the NIC_RX queue to the command "buffer".
+ *   Return 0 in "status" if queue empty / return length in "status" if success.
+ *
+ * <WRITE>
  *   Move a packet of a given "length" from the command "buffer" to the TX queue.
- *   The WRITABLE command must be called before the WRITE command.
- * - SET_MAC 
- *   Set the values defined in the "length" and "status" command arguments,
- *   into the NIC_C_MAC4 and NIG_G_MAC2  registers.
- * - SET_BC
- *   Enable/disable broadcast packets, as defined in the "status" command argument,
- *   into the NIC_G_BC_ENABLE register.
- * - SET_RUN
- *   Enable/disable NIC, as defined in the "status" command argument, 
- *   into the NIC_G_RUN register.
- * @ dev_xp  : extended pointer on the generic NIC device descriptor.
- ********************************************************************************************
- $ @ thread_xp : extended pointer on client thread (containing the command arguments).
+ *   Return 0 in "status" if queue full / return length in "status" if success.
+ *
+ * 2) It implements the GET_KEY / SET_RUN / GET_INSTRU / CLEAR_INSTRU commands,
+ *    directly called by any thread running in any cluster to access the NIC registers :
+ *
+ * <GET_KEY>
+ *   Return in "status" argument the channel index (key) computed from the IP address
+ *   defined in the "buffer" argument, and from the port defined by the "length" argument.
+ *
+ * <SET_RUN>
+ *   Enable/disable the NIC_TX_CHANNEL_RUN & NIC_RX_CHANNEL_RUN registers.The channel
+ *   is defined in the "length" argument / run value defined in the "status" argument.
+ *
+ * <GET_INSTRU>
+ *   Display on kernel TXT0 the contaent of all NIC instrumentation registers.
+ *
+ * <CLEAR_INSTRU>
+ *   Reset all NIC instrumentation registers.
+ *
+ * Note (i)  For the NIC device, the command arguments are always registered in the calling
+ *           thread descriptor (i.e. the calling thread is always the client thread).
+ * Note (ii) The actual command mnemonics are defined in the <dev_nic.h> file.
  *******************************************************************************************/
 extern void soclib_nic_cmd( xptr_t thread_xp );
 
 /********************************************************************************************
- * This ISR acknowledge the NIC_RX or NIC_TX channel ISR signaling that a new container
- * has beeen moved, and reactivate the corresponding server thread.
- * In case of address error reported by the NIC controler in accessing the kernel chbuf,
- * it goes to kernel panic.
+ * This ISR is executed when a new RX container has been moved to an empty TX queue,
+ * or when a TX container has been removed from a full TX queue. In both cases, it
+ * reactivate the corresponding server thread from the BLOCKED_ISR condition.
+ * It is also executed in case of error reported by the DMA engines accessing the TX or RX
+ * queues. It simply print an error message on the kernel terminal.
+ * TODO improve this error handling...
  ********************************************************************************************
  * @ chdev     : local pointer on NIC chdev descriptor.
