Changeset 687

Timestamp:

Jan 13, 2021, 12:49:41 AM (4 years ago)

Author:

alain

Message:

cosmetic

Location:

trunk/tools/arch_info

Files:

• arch_classes.py (modified) (6 diffs)
• arch_info.h (modified) (2 diffs)
• boot_info.h (modified) (2 diffs)
• genarch.py (modified) (1 diff)

trunk/tools/arch_info/arch_classes.py

@@ -105 +105 @@
                   cache_line,        # number of bytes in cache line
                   reset_address,     # Preloader physical base address
-                  p_width ):         # TSAR specific : number of bits to code core lid
+                  p_width,           # TSAR specific : number of bits to code core lid
+                  sys_clk ):         # system clock frequency (in Hertz)
 
         assert ( x_size <= (1<<x_width) )
@@ -125 +126 @@
         self.reset_address  = reset_address
         self.p_width        = p_width
+        self.sys_clk        = sys_clk
 
         self.total_cores    = 0
@@ -273 +275 @@
         s += '           y_size       = "%d"\n'   % (self.y_size)
         s += '           cores        = "%d"\n'   % (self.cores_max)
-        s += '           io_cxy       = "%d" >\n' % (self.io_cxy)
+        s += '           io_cxy       = "%d"\n'   % (self.io_cxy)
+        s += '           sys_clk      = "%d" >\n' % (self.sys_clk)
         s += '\n'
 
@@ -309 +312 @@
         byte_stream += self.int2bytes(4,  self.irqs_per_core)
         byte_stream += self.int2bytes(4,  self.cache_line)
-        byte_stream += self.int2bytes(4,  0)
+        byte_stream += self.int2bytes(4,  self.sys_clk)
 
         byte_stream += self.str2bytes(64, self.name)
@@ -368 +371 @@
                                  # required by
                                  # - top.cpp compilation
-                                 # - almos-mk bootloader compilation
+                                 # - almos-mkh bootloader compilation
                                  # - tsar_preloader compilation
 
@@ -634 +637 @@
         s += '#define BOOT_CORE_CXY          %d\n'    % self.boot_cxy
         s += '#define CACHE_LINE_SIZE        %d\n'    % self.cache_line
+        s += '#define SYS_CLK                %d\n'    % self.sys_clk
         s += '\n'
 

trunk/tools/arch_info/arch_info.h

@@ -2 +2 @@
  * archinfo.h - Hardware Architecture Information structures
  *
- * Author  Alain Greiner (2016)
+ * Author  Alain Greiner (2016,2017,2018,2019,2020)
  *
  * Copyright (c)  UPMC Sorbonne Universites
@@ -112 +112 @@
     uint32_t    irqs_per_core;   // number of IRQs per core
     uint32_t    cache_line_size; // number of bytes
-    uint32_t    reserved;        // reserved
+    uint32_t    sys_clk;         // system clock frequency (in Hertz)
 
     char        name[64];        // architecture name

trunk/tools/arch_info/boot_info.h

@@ -2 +2 @@
  * boot_info.h - informations passed by the bootloader to the kernel in each cluster.
  *
- * Author  Alain Greiner (june 2016,2017)
+ * Author  Alain Greiner (june 2016,2017,2018,2019,2020)
  *
  * Copyright (c) UPMC Sorbonne Universites
@@ -113 +113 @@
     uint32_t      y_size;                        /*! number of cluster in a column          */
     uint32_t      io_cxy;                        /*! IO cluster identifier                  */
+    uint32_t      sys_clk;                       /*! system frequency (in Hertz)            */
 
     uint8_t       cluster_info[CONFIG_MAX_CLUSTERS_X][CONFIG_MAX_CLUSTERS_Y]; 

trunk/tools/arch_info/genarch.py

@@ -87 +87 @@
 parser.add_option( '--sys_clk', type = 'int', dest = 'sys_clk', 
                    default = 50000,
-                   help = 'system clock frequency (50 KHz simu / 25 MHz FPGA, 600 MHz VLSI)' )
+                   help = 'system clock frequency (50 KHz simu / 1 GHz VLSI)' )
 
 parser.add_option( '--hard', type = 'string', dest = 'hard_path',