Changes between Version 11 and Version 12 of arch_info
- Timestamp:
- Jul 20, 2016, 2:52:36 PM (8 years ago)
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arch_info
v11 v12 72 72 73 73 || '''name''' || mapping name == architecture name || 74 || '''x_size''' || number of clusters in a row of the 2D mesh||75 || '''y_size''' || number of clusters in a column of the 2D mesh||74 || '''x_size''' || number of clusters in a row (for a 2D mesh) || 75 || '''y_size''' || number of clusters in a column (for a 2D mesh) || 76 76 || '''nprocs''' || max number of processors per cluster || 77 || '''x_width''' || number of bits to encode X coordinate in paddr || 78 || '''y_width''' || number of bits to encode Y coordinate in paddr || 79 || '''p_width''' || number of bits to encode local processor index || 80 || '''paddr_width''' || number of bits in physical address || 77 || '''x_width''' || number of bits to encode X coordinate in CXY || 78 || '''y_width''' || number of bits to encode Y coordinate in CXY || 79 || '''cluster_span''' || number of bits in localphysical address || 81 80 || '''coherence''' || Boolean true if hardware cache coherence || 82 || '''irq_per_proc''' || number of IRQ lines between XCU and one proc (GIET_VM use only one)||81 || '''irq_per_proc''' || number of IRQ lines between XCU and one core || 83 82 || '''use_ramdisk''' || Boolean true if the architecture contains a RamDisk || 84 || '''x_io''' || io_cluster X coordinate || 85 || '''y_io''' || io_cluster Y coordinate || 86 || '''peri_increment''' || virtual address increment for peripherals replicated in all clusters || 83 || '''io_cxy''' || io_cluster identifier || 84 || '''boot_cxy''' || boot_cluster identifier || 87 85 || '''reset_address''' || physical base address of the ROM containing the preloader code || 88 || '''ram_base''' ||physical memory bank base address in cluster [0,0] ||89 || '''ram_size''' || physical memory bank size in one cluster (bytes) ||90 86 91 87 === 3.2) Processor core ===
