Changes between Version 7 and Version 8 of arch_info


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Timestamp:
Jul 20, 2016, 2:39:19 PM (8 years ago)
Author:
alain
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  • arch_info

    v7 v8  
    33[[PageOutline]]
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    5 ALMOS-MK has been designed to support clustered manycore architectures, using 32 bits cores (such as the MIPS32 based TSAR architecture), or 64 bits cores (such as the I64 based multicores INTEL/AMD architectures). Each cluster contains one or several cores, a variable number of addressable peripherals, and one physical memory bank. ALMOS-MK implement one kernel instance per cluster.
     5ALMOS-MK has been designed to support clustered manycore architectures, using 32 bits cores (such as the MIPS32 based TSAR architecture), or 64 bits cores (such as the multi-cores INTEL/AMD architectures). Each cluster contains one or several cores, a variable number of addressable peripherals, and one physical memory bank. ALMOS-MK implements one kernel instance per cluster.
    66
    77All relevant parameters describing the clustered multi-core architecture must be defined in the binary '''arch_info.bin''' file.
    … …  
    6060These five C structures are defined in the  [source:almos-work/tools/arch_info/arch_info.h arch_info.h] file. The access functions are defined in the  [source:almos-work/tools/arch_info/arch_info.c arch_info.c] file.
    6161
    62 === 2.3) The python arch_info.py script ===
     62== 3) The python script ===
    6363
    6464This section defines the python constructs that can be used to generate  the '''arch_info.bin''' binary file.
     65These Python classes are defined in the [source:soft/almos-work/tools/python/genarch.py genarch.py] file.
    6566
    66 == 3) The boot_info_t structure ==
     67== __Python hardware architecture description__ ==
     68
     69The target hardware architecture must be defined in the ''arch.py'' file , you must use the following constructors:
     70
     71=== 3.1) architecture  ===
     72
     73The Archi( ) constructor build an architecture object and defines the target architecture general parameters:
     74
     75|| '''name'''               || mapping name == architecture name ||
     76|| '''x_size'''              || number of clusters in a row of the 2D mesh ||
     77|| '''y_size'''              || number of clusters in a column of the 2D mesh ||             
     78|| '''nprocs'''             || max number of processors per cluster ||     
     79|| '''x_width'''           || number of bits to encode X coordinate in paddr  ||
     80|| '''y_width'''            || number of bits to encode Y coordinate in paddr  ||
     81|| '''p_width'''            || number of bits to encode local processor index  ||
     82|| '''paddr_width'''     ||  number of bits in physical address ||
     83|| '''coherence'''        || Boolean true if hardware cache coherence ||     
     84|| '''irq_per_proc'''     || number of IRQ lines between XCU and one proc (GIET_VM use only one) ||
     85|| '''use_ramdisk'''     || Boolean true if the architecture contains a RamDisk ||
     86|| '''x_io'''                  || io_cluster X coordinate ||         
     87|| '''y_io'''                  || io_cluster Y coordinate ||
     88|| '''peri_increment''' || virtual address increment for peripherals replicated in all clusters ||
     89|| '''reset_address'''   || physical base address of the ROM containing the preloader code ||
     90|| '''ram_base'''          ||physical memory bank base address in cluster [0,0] ||
     91|| '''ram_size'''          || physical memory bank size in one cluster (bytes) ||
     92
     93=== 3.2) Processor core ===
     94
     95The '''archi.addProc( )''' construct adds one processor core in a cluster. It associates a core composite index (cry, lid) to the core hardware index, and has has the following arguments:
     96|| '''cxy'''  || cluster identifier ||
     97|| '''lid'''    ||  local core index ||
     98|| '''gid'''   || core hardware identifier ||
     99
     100=== 3.3) Physical memory bank ===
     101
     102The '''archi.addRam( )''' construct adds one physical memory segment in a cluster. It has the following arguments:
     103|| '''cxy'''        || cluster identifier ||
     104|| '''base'''       || local physical base address ||
     105|| '''size'''        || segment size (bytes) ||
     106
     107=== 3.4) Peripheral ===
     108
     109The '''archi.addPeriph( )''' construct adds one peripheral in a cluster. ALMOS-MK supports multi-channels peripherals.
     110This construct has the following arguments:
     111|| '''cxy'''         || cluster identifier ||
     112|| '''base'''       || local physical base address ||
     113|| '''size'''        || segment size (bytes) ||
     114|| '''ptype'''     || Peripheral type ||
     115|| '''subtype'''  || Peripheral subtype ||
     116|| '''channels''' || number of channels for multi-channels peripherals ||
     117|| '''arg0'''        || optionnal argument depending on peripheral type ||
     118|| '''arg1'''        || optionnal argument depending on peripheral type ||
     119|| '''arg2'''          || optionnal argument depending on peripheral type ||
     120|| '''arg3'''          || optionnal argument depending on peripheral type ||
     121
     122Each peripheral type is defines by a composite index (ptype,subtype).
     123The supported peripheral types and subtypes are defined in the [source:almos-work/tools/python/genarch.py genarch.py] file.
     124
     125The following peripheral components require specific arguments with the following semantic:
     126||               || Frame Buffer                    || Interrupt controller      || Generic DMA Controller               ||
     127|| ptype     ||   FBF                                 ||   XCU                           ||   MWR                                         ||
     128|| arg0       || number of pixels per line || Number of HWI inputs || number of TO_COPROC ports      ||
     129|| arg1       || number of lines                || Number of PTI inputs  || number of FROM_COPROC ports  ||
     130|| arg2       || unused                             || Number of WTI inputs  || number of CONFIG registers       ||
     131|| arg3       || unused                             || unused                       || number of STATUS registers       ||
     132
     133Hardware coprocessors using the Generic DMA controller to access memory are described as peripherals. They must be defined with the MWR ''ptype'' argument, and the ''subtype'' argument defines the coprocessor type.
     134
     135=== 3.5) Interrupt line ===
     136
     137The '''archi.addIrq()''' is used to describe the hardware interrupts routing from a physical peripheral to an interrupt concentrator. This construct adds one input IRQ line to an XCU peripheral, or to a PIC peripheral. It has the following arguments:
     138|| '''periph'''   || peripheral receiving the IRQ line ||
     139|| '''index'''    || input port index ||
     140|| '''isrtype'''  || Interrupt Service Routine type ||
     141|| '''channel''' || channel index for multi-channel ISR ||
     142
     143The supported ISR types are defined in the [source:almos-work/tools/python/genarch.py genarch.py] file.
     144
     145
     146== 4) The boot_info_t structure ==
    67147
    68148The ALMOS-MK boot-loader  uses the informations found in '''arch_info.bin''' to build one '''boot_info_t''' structure in each cluster. This generic  '''boot_info_t''' structure is used by the ALMOS kernel to build in each cluster its own representation of the hardware.