Changes between Version 32 and Version 33 of io_operations

Timestamp:

Nov 22, 2017, 3:01:40 PM (7 years ago)

Author:

alain

Comment:

--

io_operations

@@ -110 +110 @@
 Each external IRQ (IRQ generated by a given external device channel) is identified by a '''irq_id''' index, used as an identifier by the kernel. For a given hardware architecture, this '''irq_id''' index is defined by the ''arch_info'' file describing the architecture, and is registered by the kernel in the '''iopic_input''' structure, that is a global variable replicated in all clusters.
 
-The actual interrupt routing is defined during the PIC device initialization, by the architecture specific PIC driver. The PIC device is the first device initialized by the kernel_init() function.
+The actual interrupt routing is defined during the PIC device initialization, by the architecture specific PIC driver, as defined below. 
+
+=== TSAR_MIPS32 architecture ===
+
+The IOPIC external controller provides two services:
+ 1. It translate each IRQ identified by its '''irq_id''' to a write transactions to a specific mailbox contained in a local LAPIC controller, for a given core in a given cluster. as explained below.
+ 1. It allows the kernel to selectively enable/disable any external IRQ identified by its '''irq_id''' index.
+
+The LAPIC controller (called XCU) is replicated in all clusters containing at least one core. It handle three types of IRQs:  The '''HWI''' (HardWare Interrupts) are generated by local internal peripherals, and connected to the local XCU, to be routed to a given local core. The '''WTI''' ( Write Triggered Interrupts) are actually mailboxes implemented in the local XCU. They are used to implement both software IPIs (Inter-Processor-Interrupts),
+or to register the external IRQs (write transactions) generated by the IOPIC controller. Finally the '''PTI''' (Programmable Timer Interrupts) are actually timers contained contained in the LAPIC,programmed by the kernel, 
+and routed to a local core to implement context switches (TICK event). The numbers of interrupts of each type in a given cluster are defined in the XCU_CONFIG register of the XCU component, and cannot be larger than the
+SOCLIB_MAX_HWI, SOCLIB_MAX_WTI, SOCLIB_MAX_PTI constants defined in the '' soclib_pic.h'' file.
+
+The actual IRQ routing policy implemented by the SOCLIB_PIC driver depends on the IRQ type. For the external IRQs, the routing is done by the soclib_pic_bind_irq() function.
+
+ * ''Local Hardware Interrupt''' : There is only two local peripherals. The MMC device is the L2 cache configuration
+ * '''PTI''' : There is one PTI per local core, and the PTI index is equal to the core local index.
+ * '''IPI''' : There is one IPI per local core. Each IPI is implemented as a WTI mailbox.
+ * '''External Hardware Interrupt''' : each external IRQ is translated to a WTI event,
+
+ The LAPIC controller provides three main services:
+ 1. It allows the kernel to selectively enable/disable any IRQ (identified by its type and index) for a given core. It is the kernel responsibility to enable a given IRQ for a single core as a given IRQ event should be handled by only one core.
+ *   2) It makes a global OR between all enabled IRQs for a given core, to interrupt
+ *      the core when at least one enabled IRQ is active.
+ *   3) It is capable to return the highest priority active IRQ of each type.
+ *      For each type, the lowest index have the highest priority.
+
+===  X86_64 architecture === 
+