source: anr-2010/section-2.1.tex @ 359

\begin{table}\leavevmode\center
\begin{small}\begin{tabular}{|l|l|l|l|}\hline
Segment                 & 2010   & 2011    & 2012 \\\hline\hline
Communications          & 1,867  & 1,946   & 2,096 \\
High end                & 467    & 511     & 550 \\\hline
Consumer                & 550    & 592     & 672 \\
High end                & 53     & 62      & 75 \\\hline
Automotive              & 243    & 286     & 358 \\
High end                & -      & -       & - \\\hline
Industrial              & 1,102  & 1,228   & 1,406 \\
High end                & 177    & 188     & 207 \\\hline
Military/Aereo          & 566    & 636     & 717 \\
High end                & 56     & 65      & 82 \\\hline\hline
Total FPGA/PLD          & 4,659  & 5,015   & 5,583 \\
Total High-End  FPGA    & 753    & 826     & 914 \\\hline
\end{tabular}\end{small}
\caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)}
\end{table}
%
Microelectronic components allow the integration of complex functions into products, increases
commercial attractivity of these products and improves their competitivity.
Multimedia and tele-communication sectors have taken advantage from microelectronics facilities
thanks to the developpment of design methodologies and tools for embedded systems.
Unfortunately, the Non Recurring Engineering (NRE) costs involded in the design
and manufacturing ASICs is very high.
An IC foundry costs several billions of euros and the fabrication of a specific circuit
costs several millions. For example a conservative estimate for a 65nm ASIC project is 10
million USD.
Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium
volume markets.
\parlf
Today, FPGAs become important actors in the computational domain that was originally dominated
by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed
on a per-application basis. For many applications, FPGAs offer significant performance benefits over
microprocessors implementation. There is still a performance degradation of one order
of magnitude versus an equivalent ASIC implementations, but low cost 
(500 euros to 10K euros), fast time-to-market and flexibility of FPGAs make them an attractive 
choice for low-to-medium volume applications. 
Since their introduction in the mid eighties, FPGAs evolved from a simple, 
low-capacity gate array to devices (\altera STRATIX III, \xilinx Virtex V) that
provide a mix of coarse-grained data path units, memory blocks, microprocessor cores, 
on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement
complex systems like multi-processors platform with application dedicated coprocessors. 
Table~\ref{fpga_market} shows the estimation of the FPGA worldwide market in the next years in
various application domains. The ``high end'' lines concern only FPGA with high logic
capacity for complex system implementations.
This market is in significant expansion and is estimated to 914\,M\$ in 2012.
%The HPC market size is estimated today by FPGA providers at 214\,M\$. 
%Using FPGA limits the NRE costs to the design cost.
%This boosts the developpment of automatic design tools and methodologies.
%
\parlf
Today, several companies (Atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp, 
Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand 
for very high performance (HPC) primes over other requirements. They tend to use the highest 
performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative 
architectures and algorithms. These companies show up in different "traditional" applications and market 
segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC 
emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers 
at 214\,M\$. 
This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion
of FPGA-based solutions is limited by the lack of design automation.
\\
\\
Nowadays, there are no commercial or academic tools covering the whole design flow
from the system level specification to the bitstream generation neither for embedded system design
nor for HPC.

%PC => IA et Alain
%Le paragraphe ci dessous n'a rien a faire dans la partie Economic et societal issue
%Je le mets donc en commentaire

%By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
%parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
%processor,  bus core, ...) as well as incorporate their own IP.
%Designers can then generate a synthesized netlist, simulation test bench and custom
%software library that reflect the hardware configuration.
%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
%simulate the platform at a high design level (systemC). 
%In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
%tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
%PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
%coprocessors from a C++ description.
%Nevertheless, they can only deal with data dominated applications and they do not handle
%the platform level.
%Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
%Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
%Designers can design and simulate a system using MATLAB and Simulink. The tool will then
%automatically generate synthesizable Hardware Description Language (HDL) code mapped to
%\xilinx pre-optimized macro-cells.
%However, this tool targets only DSP based algorithms.
%\\
%Consequently, a designer developping an embedded system needs to master four different
%design environments:
%\begin{enumerate}
%  \item a virtual prototyping environment such as SoCLib for system level exploration,
%  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
%  from \xilinx) to define the hardware architecture,
%  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for 
%        coprocessor synthesis,
%  \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
%\end{enumerate}
%Furthermore, mixing these tools requires an important interfacing effort and this makes
%the design process very complex and achievable only by designers skilled in many domains.

\begin{center}\begin{minipage}{.9\linewidth}\textit{
The aim of the COACH project is to integrate all these design steps into a single design framework
and to allow \textbf{pure software} developpers to design embedded systems.
}\end{minipage}\end{center}

%PC => IA et Alain
% le paragraphe suivant est coupé collé de la section suivante 2.2


\parlf
The COACH project proposes an open-source framework for mapping multi-tasks software applications
on Field Programmable Gate Array circuits (FPGA).
It aims to propose solutions to the societal/economical challenges by
providing SMEs novel design capabilities enabling them to increase their
design productivity with design exploration and synthesis methods that are placed on top 
of the state-of-the-art methods.
We believe that the combination of a design environment dedicated to software developpers
and FPGA targets,
will allow small and even very small companies to propose embedded system and accelerating solutions 
for standard software applications with attractive and competitive prices.
This new market may explode in the same way as the micro-computer market in the eighties,
whose success was due to the low cost of the first micro-processors (compared to main frames) 
and the advent of high level programming languages which allowed a high number of programmers 
to launch start-ups in software engineering.