source: anr-2010/section-2.1.tex @ 276

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1\begin{table}\leavevmode\center
2\begin{small}\begin{tabular}{|l|l|l|l|}\hline
3Segment                 & 2010   & 2011    & 2012 \\\hline\hline
4Communications          & 1,867  & 1,946   & 2,096 \\
5High end                & 467    & 511     & 550 \\\hline
6Consumer                & 550    & 592     & 672 \\
7High end                & 53     & 62      & 75 \\\hline
8Automotive              & 243    & 286     & 358 \\
9High end                & -      & -       & - \\\hline
10Industrial              & 1,102  & 1,228   & 1,406 \\
11High end                & 177    & 188     & 207 \\\hline
12Military/Aereo          & 566    & 636     & 717 \\
13High end                & 56     & 65      & 82 \\\hline\hline
14Total FPGA/PLD          & 4,659  & 5,015   & 5,583 \\
15Total High-End  FPGA    & 753    & 826     & 914 \\\hline
16\end{tabular}\end{small}
17\caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)}
18\end{table}
19%
20Microelectronic components allow the integration of complex functions into products, increases
21commercial attractivity of these products and improves their competitivity.
22Multimedia and tele-communication sectors have taken advantage from microelectronics facilities
23thanks to the developpment of design methodologies and tools for embedded systems.
24Unfortunately, the Non Recurring Engineering (NRE) costs involded in the design
25and manufacturing ASICs is very high.
26An IC foundry costs several billions of euros and the fabrication of a specific circuit
27costs several millions. For example a conservative estimate for a 65nm ASIC project is 10
28million USD.
29Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium
30volume markets.
31\parlf
32Today, FPGAs become important actors in the computational domain that was originally dominated
33by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed
34on a per-application basis. For many applications, FPGAs offer significant performance benefits over
35microprocessors implementation. There is still a performance degradation of one order
36of magnitude versus an equivalent ASIC implementations, but low cost
37(500 euros to 10K euros), fast time-to-market and flexibility of FPGAs make them an attractive
38choice for low-to-medium volume applications.
39Since their introduction in the mid eighties, FPGAs evolved from a simple,
40low-capacity gate array to devices (\altera STRATIX III, \xilinx Virtex V) that
41provide a mix of coarse-grained data path units, memory blocks, microprocessor cores,
42on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement
43complex systems like multi-processors platform with application dedicated coprocessors.
44Table~\ref{fpga_market} shows the estimation of the FPGA worldwide market in the next years in
45various application domains. The ``high end'' lines concern only FPGA with high logic
46capacity for complex system implementations.
47This market is in significant expansion and is estimated to 914\,M\$ in 2012.
48%The HPC market size is estimated today by FPGA providers at 214\,M\$.
49%Using FPGA limits the NRE costs to the design cost.
50%This boosts the developpment of automatic design tools and methodologies.
51%
52\parlf
53Today, several companies (Atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp,
54Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand
55for very high performance (HPC) primes over other requirements. They tend to use the highest
56performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative
57architectures and algorithms. These companies show up in different "traditional" applications and market
58segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC
59emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers
60at 214\,M\$.
61This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion
62of FPGA-based solutions is limited by the lack of design automation.
63\\
64\\
65Nowadays, there are no commercial or academic tools covering the whole design flow
66from the system level specification to the bitstream generation neither for embedded system design
67nor for HPC.
68
69%PC => IA et Alain
70%Le paragraphe ci dessous n'a rien a faire dans la partie Economic et societal issue
71%Je le mets donc en commentaire
72
73%By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
74%parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
75%processor,  bus core, ...) as well as incorporate their own IP.
76%Designers can then generate a synthesized netlist, simulation test bench and custom
77%software library that reflect the hardware configuration.
78%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
79%simulate the platform at a high design level (systemC).
80%In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
81%tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
82%PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
83%coprocessors from a C++ description.
84%Nevertheless, they can only deal with data dominated applications and they do not handle
85%the platform level.
86%Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
87%Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
88%Designers can design and simulate a system using MATLAB and Simulink. The tool will then
89%automatically generate synthesizable Hardware Description Language (HDL) code mapped to
90%\xilinx pre-optimized macro-cells.
91%However, this tool targets only DSP based algorithms.
92%\\
93%Consequently, a designer developping an embedded system needs to master four different
94%design environments:
95%\begin{enumerate}
96%  \item a virtual prototyping environment such as SoCLib for system level exploration,
97%  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
98%  from \xilinx) to define the hardware architecture,
99%  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for
100%        coprocessor synthesis,
101%  \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
102%\end{enumerate}
103%Furthermore, mixing these tools requires an important interfacing effort and this makes
104%the design process very complex and achievable only by designers skilled in many domains.
105
106\begin{center}\begin{minipage}{.9\linewidth}\textit{
107The aim of the COACH project is to integrate all these design steps into a single design framework
108and to allow \textbf{pure software} developpers to design embedded systems.
109}\end{minipage}\end{center}
110
111%PC => IA et Alain
112% le paragraphe suivant est coupé collé de la section suivante 2.2
113
114
115\parlf
116The COACH project proposes an open-source framework for mapping multi-tasks software applications
117on Field Programmable Gate Array circuits (FPGA).
118It aims to propose solutions to the societal/economical challenges by
119providing SMEs novel design capabilities enabling them to increase their
120design productivity with design exploration and synthesis methods that are placed on top
121of the state-of-the-art methods.
122We believe that the combination of a design environment dedicated to software developpers
123and FPGA targets,
124will allow small and even very small companies to propose embedded system and accelerating solutions
125for standard software applications with attractive and competitive prices.
126This new market may explode in the same way as the micro-computer market in the eighties,
127whose success was due to the low cost of the first micro-processors (compared to main frames)
128and the advent of high level programming languages which allowed a high number of programmers
129to launch start-ups in software engineering.
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