source: anr-2010/section-2.tex @ 277

Embedded systems (SoC and MPSoC) became an inevitable evolution in the microelectronic industry.
Due to the exploding fabrication costs, the ASIC technology (Application Specific Integrated Circuit) 
is not an option for SMEs (Small and Medium Enterprises).
Fortunately, the new FPGA (Field Programmable Gate Array) components,
such as the Virtex5 family from \xilinx, or the Stratix4 family from \altera can implement a complete
multi-processor architecture on a single device.
But the design of embedded system is a long and complex task that requires expertise in software,
software/hardware partionning, operating system, hardware design, VHDL/Verilog modeling.
Only very few SMEs have these multiple expertises and are present on the embedded system market.
\begin{center}\begin{minipage}{.8\linewidth}\textit{
The major objective of COACH is to provide to SMEs an open-source framework to design
embedded systems on FPGA devices by system designers.
}\end{minipage}\end{center}
%Current design methodologies provide quite low-level abstraction capabilities, and 
%there is an urgent need to leverage system level exploration through the use of a high-level 
%specification of the application and  design space exploration tools.
%The first system oriented approaches are appearing, among which those
%based on C/C++ and SystemC are the most popular, but few of them are specifically targetting FPGAs.
%%%
\parlf
The COACH project will leverage on the expertise gained in the field of virtual prototyping
with the SoCLib platform, to propose a new design flow based on a small number of architectural templates.
An architectural template is a generic, parameterized architecture, relying on a predefined library 
of IP cores. 
Besides using a specific collection of general purpose IP cores (such as processors cores,
embedded memory controllers, system bus controllers, I/O and peripheral controllers), each architectural
template can be enriched by dedicated hardware coprocessors, obtained by high level synthesis (HLS) tools.
During this project, the COACH partners will develop three different architectural templates:
\begin{enumerate}
\item An \altera architectural template based on the \altera IP core library, the AVALON system bus and the NIOS processor.
\item A \xilinx architectural template based on the \xilinx IP core library, the PLB system bus and the Microblaze processor.
\item A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP
      communication infrastructure.
\end{enumerate}
The proposed design flow starts from a high level description of the application, specified as a set of 
parallel tasks written in C, without any assumption on the hardware or software implementation
of these tasks. It lets the system
designer in charge of expressing the coarse grain parallelism of the application, gives the designer
the possibility to explore various mapping of the application on the selected template architecture,
and offers a high predictability of results with respect to cost and performance objectives.
\\
When this interactive, system level, design space exploration is completed (converging to
a specific mapping on a specific version of the selected architectural template), the rest of the flow 
is fully automated: The synthesisable VHDL models for the various hardware components, as well as the binary
code for the software running on the embedded processors, and the bit-stream to program the the target FPGA 
will be automatically generated by the COACH tools.
%
\parlf
The strength of the COACH approach is the strong integration of the high-level synthesis tools 
in a platform based design flow supporting virtual prototyping and design space exploration.
Most building blocks already exist (resulting from previous projects): the GAUT 
or UGH synthesis tools, the MUTEKH or DNA embedded operating systems, the ASIP technology,
the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelisation tool,
as well as the SoCLib library of systemC simulation models. They must now be enhanced and integrated in
a consistent design flow.
%The five academic laboratories worked very closely during more than one year (one monthly meeting
%in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating
%those various technologies, and to define the detailed architecture of the proposed design flow.
%%%
\parlf
In HPC (High Performance Computing), the targeted application is an existing application
running on a PC.
The COACH framework helps designer to accelerate it by migrating critical parts into a
SoC embedded into an FPGA device plugged to the PC PCI/X bus.
\begin{center}\begin{minipage}{.8\linewidth}\textit{
The second objective of COACH is to extend the framework to HPC.
}\end{minipage}\end{center}
This will allow SMEs to enter HPC market for the applications that are
unadapted to the current GPU based solutions.
%%%
\parlf
In summary, the COACH project is clearly oriented toward industry, even if most technology building blocks
have been previously developed by academic laboratories.


%Finally, the key points of the proposed design flow are :
%\begin{itemize} 
%\item
%\textbf{System level exploration}: The application coarse grain parallelism 
%is explicitely described as a Tasks and Communication Graph (TCG).
%A template architecture is selected, and the performances are evaluated
%on various variant of this architecture using the SoCLib virtual protyping
%environment. This result in a specific hardware/software partitioning.  
%This system level exploration is fully controlled by the system designer, and is driven 
%by cost, throughput, latency and power consumption criteria. 
%
%\item
%\textbf{High Level Synthesis}: When dedicated hardware coprocessors have been
%identified as mandatory, they will be generated by the high level synthesis (HLS) tools. 
%The COACH framework will integrate various HLS tools, supporting the micro-architectural space
%design exploration. Here again, the exploration criteria are cost, throughput, latency
%and power consumption.
%At this stage, preliminary source-level transformations and optimisations by front-end
%tools will be required to improve the efficiency of the back-end HLS tools.
%
%\item
%\textbf{Early performance evaluation}: For each point in the design space,
%figures of merit must be available such as throughput, latency, power
%consumption, area, memory allocation and data locality. They are evaluated
%by reliable estimators obtained by running the actual multi-task software 
%application on the virtual prototype.
%
%\item
%\textbf{Independance from the Target FPGA}: The COACH description of the system 
%(both hardware and software) should be independent of the FPGA family.  
%Every point of the design space can be implemented on any FPGA component,
%as long as it contains the hardware ressources required by the selected architectural template.
%Basically, COACH will support both \altera and \xilinx FPGA families.
%\end{itemize}
%