source: anr-2010/section-4.4.tex

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1\definecolor{gtcBoxHeavy}{rgb}{0.10,0.10,0.90}
2\definecolor{gtcBoxLight}{rgb}{0.9,0.90,0.99}
3\definecolor{gtcTaskBG0} {rgb}{0.99,0.90,0.7}
4\definecolor{gtcTaskBG1} {rgb}{0.90,0.99,0.7}
5\definecolor{gtcMilestone}{rgb}{0.9,0.4,0.4}
6\immediate\write\ganttdata{ML=6 ML=12 ML=18 ML=24}
7\def\ganttlabelstyle#1{\begin{small}#1\end{small}}
8\def\gantttitlestyle#1{\begin{scriptsize}\textit{#1}\end{scriptsize}}
9
10%\begin{figure}\leavevmode\center
11%\hspace*{-.6cm}
12%\input{gantt.tex}
13%\caption{\label{gantt}Gantt diagram of deliverables}
14%\end{figure}
15
16\begin{figure}\leavevmode\center
17\hspace*{-.4cm}%\vspace{-1.5cm}
18\input{gantt1.tex}
19\caption{\label{gantt1}Gantt diagram of deliverables (task-1 to task-4 and task-8)}
20\end{figure}
21
22\begin{figure}\leavevmode\center
23\hspace*{-.4cm}%\vspace{-1.5cm}
24\input{gantt2.tex}
25\caption{\label{gantt2}Gantt diagram of deliverables (task-5, task-6 and task-7)}
26\end{figure}
27
28The figures~\ref{gantt1}~\&~\ref{gantt2} present the Gantt diagram of the project.
29Before the final release (T0+36), there are 4 milestones (red lines on the figures) at
30$T0+6$, $T0+12$, $T0+18$ and $T0+24$ that are rendez-vous points of the precedent
31deliverables.
32\begin{description}
33\item[Milestone 1 ($T0+6$)] Specification of COACH inputs, of the \xcoach format and of
34    the demonstatrors as a reference software.
35\item[Milestone 2 ($T0+12$)] The first COACH release. At this step the demonstrators are
36    written in the COACH input format. This COACH release allows to prototype and to generate the FPGA-SoC.
37    The main restrictions are:
38    1) Only the neutral architectural template is supported,
39    2) HAS is not available (but prototyping with virtual coprocessors is available),
40    3) Enhanced communication schemes are not available.
41    4) ASIP compilation flow is not available.
42\item[Milestone 3 ($T0+18$)]  The second COACH release. At this step most of the COACH
43    features are availables. A preliminary version of the ASIP synthesis flow is supported, for a
44   simple extensible MIPS model. The main restriction is that COACH can not yet
45   generate FPGA-SoC for \altera and \xilinx architectural templates.
46    The others restriction is that the HAS tools are not yet fully operational.
47\item[Milestone 4 ($T0+24$)] The pre-release of the COACH project. The full design flow is
48    supported.
49    The main restriction are:
50    1) The backend HAS tools have not been yet enhanced,
51    2) Dynamic partial reconfiguration is not supported,
52    3) NIOS processor instruction set extension is supported, but only for user specified patterns.
53\item[Final Release ($T0+36$)] 
54       
55\end{description}
56This organisation allows the project to globally progress step by step mixing development
57and demonstrator deliverables.
58Hence, demonstrator feed-back will arrive early and so the risk to point out incompatibility
59at the integration phase is significantly reduced.
60\par
61The risks that have been identified at the beginning of the project are the following:
62\begin{description}
63\item[\xcoach format (\novers{\specXcoachDoc}, \novers{\specXcoachToCA})]
64        Partners have to agree on a convenient exchange format for all tools involved.
65        Because all the HAS tools rely on it, the \xcoach format specification is a
66    crucial step. There are no work-around but as mentionned in
67    section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) the five academic partners have worked on it
68        for a full year and a preliminary document already exists.
69%\item[\xcoachplus format (\novers{\specXcoachDoc},
70%      \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})]
71%    Its aim is the generation of the coprocessors (hardware \& prototyping model).
72%    By centralizing the coprocessor generation, it guarantees their functioning
73%    independently of the used HAS tools.
74%       Our experience with UGH and GAUT give us confidence in the succes of this
75%       task.
76\item[Virtual prototyping of \altera \& \xilinx architectural templates ({\csgAlteraSystemC},
77     {\csgXilinxSystemC})]
78     The SoCLib component library contains several SystemC models used for the virtual
79     prototyping of the \altera and \xilinx architectural templates (NIOS and Microblaze processor cores).
80     Nevertheless, at this time we do not know how many IP cores SystemC simulation models have to be developped.
81     If the workload of this simulation model development is too important, virtual prototyping
82         of those architectural templates will not be directly supported.
83         The three architectural templates being quite similar, the virtual
84         prototyping will use the neutral architectural template.
85\item[VCI/AVALON \& VCI/PLB bridges (\novers{\hpcAvalonBridge}, \novers{\hpcPlbBridge})]
86     If one of these tasks is impossible or too important or leads to inefficiency,
87     it will be abandoned.
88     In this case, the neutral architectural template will not be available for HPC and
89     a SystemC VCI model corresponding to the PCI/X IP will be developped to allow
90     virtual prototyping.
91\end{description}
92\parlf
93Finally the list of all the deliverables is presented on figure~\ref{all-delivrables}.
94\begin{figure}\leavevmode\center
95{
96\fontsize{7pt}{9pt}\selectfont
97\settowidth\desclen{XILINX RTL optimisation (5)}
98\def\Sformat#1{\textsc{#1}}
99%\hspace*{-2.5mm}
100\begin{minipage}{1.0\linewidth}
101\input{table_livrable_01.tex}
102\hfill\hspace*{1mm}\hfill
103\input{table_livrable_02.tex}
104\end{minipage}
105}
106\caption{\label{all-delivrables}All the deliverables}
107\end{figure}
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