source: anr-2010/section-6.1.tex @ 283

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1%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
2\subsubsection{\inria/CAIRN}
3
4INRIA, the French national institute for research in computer science
5and control, operating under the dual authority of the Ministry of
6Research and the Ministry of Industry, is dedicated to fundamental and
7applied research in information and communication science and
8technology (ICST). The Institute also plays a major role in technology
9transfer by fostering training through research, diffusion of
10scientific and technical information, development, as well as
11providing expert advice and participating in international programs.
12\parlf
13By playing a leading role in the scientific community in the field and
14being in close contact with industry, INRIA is a major participant in
15the development of ICST in France. Throughout its eight research
16centres in Rocquencourt, Rennes, Sophia Antipolis, Grenoble, Nancy,
17Bordeaux, Lille and Saclay, INRIA has a workforce of 3 800, 2 800 of
18whom are scientists from INRIA and INRIA's partner organizations such
19as CNRS (the French National Center for Scientific Research),
20universities and leading engineering schools. They work in 168 joint
21research project-teams. Many INRIA researchers are also professors and
22approximately 1 000 doctoral students work on theses as part of INRIA
23research project-teams.
24%\parlf
25%INRIA develops many partnerships with industry and fosters technology
26%transfer and company foundation in the field of ICST - some ninety
27%companies have been founded with the support of INRIA-Transfert, a
28%subsidiary of INRIA, specialized in guiding, evaluating, qualifying,
29%and financing innovative high-tech IT start-up companies. INRIA is
30%involved in standardization committees such as the IETF, ISO and the
31%W3C of which INRIA was the European host from 1995 to 2002.
32%\parlf
33%INRIA maintains important international relations and exchanges. In
34%Europe, INRIA is a member of ERCIM which brings together research
35%institutes from 19 European countries. INRIA is a partner in about 120
36%FP6 actions and 40 FP7 actions, mainly in the ICST field. INRIA also
37%collaborates with numerous scientific and academic institutions abroad
38%(joint laboratories such as LIAMA, associated research teams, training
39%and internship programs).
40
41The CAIRN group of INRIA Rennes -- Bretagne Atlantique study reconfigurable
42system-on-chip, i.e. hardware systems whose configuration may change before or even during
43execution. To this end, CAIRN has 13 permanent researchers and a variable number of PhD
44students, post-docs and engineers.
45CAIRN intends to approach reconfigurable architectures from three
46angles: the invention of new reconfigurable platforms, the development
47of associated transformation, compilation and synthesis tools, and the
48exploration of the interaction between algorithms and architectures.
49CAIRN is a joint team with CNRS, University of Rennes 1 and ENS Cachan.
50
51\subsubsection{\lip/Compsys}
52The Compsys group of Ecole Normale Sup\'erieure de Lyon is a project-team
53of INRIA Rh\^one-Alpes and a part of Laboratoire de l'Informatique du
54Parall\'elisme (LIP), UMR 5668 of CNRS. It has four permanent researchers
55and a variable number of PhD students and post-docs. Its field of
56expertise is compilation for embedded system, optimizing compilers
57and automatic parallelization. Its members were among the initiators
58of the polyhedral model for automatic parallelization and program
59optimization generally. It  has authored or contributed to
60several well known libraries for linear programming, polyhedra manipulation
61and optimization in general. It has strong industrial cooperations, notably
62with ST Microelectronics and \thales.
63
64
65%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
66\subsubsection{\tima}
67The TIMA laboratory ("Techniques of Informatics and Microelectronics
68for integrated systems Architecture") is a public research laboratory
69sponsored by Centre National de la Recherche Scientifique (CNRS, UMR5159),
70Grenoble Institute of Technology (Grenoble-INP) and Universit\'{e} Joseph Fourier
71(UJF).
72The research topics cover the specification, design, verification, test,
73CAD tools and design methods for integrated systems, from analog and
74digital components on one end of the spectrum, to multiprocessor
75Systems-on-Chip together with their basic operating system on the other end.
76\parlf
77Currently, the lab employs 124 persons among which 60 PhD candidates, and runs
7832 ongoing French/European funded projects.
79Since its creation in 1984, TIMA funded 7 startups, patented 36 inventions
80and had 243 PhD thesis defended.
81\parlf
82The System Level Synthesis Group (25 people including PhDs) is
83involved in several FP6, FP7, CATRENE and ANR projects.
84Its field of expertise is in CAD and architecture for Multiprocessor
85SoC and Hardware/Software interface.
86
87%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
88\subsubsection{\ubs}
89
90The Lab-STICC (Laboratoire des Sciences et Techniques de l'Information,
91de la Communication, et de la Connaissance), is a French CNRS laboratory
92(UMR 3192) that groups 4 research centers in the west and south
93Brittany: the Universit\'e de Bretagne-Sud (UBS), the Universit\'e de
94Bretagne Occidentale (UBO), and Telecom Bretagne (ENSTB).
95The Lab-STICC is composed of three departments: Microwave and equipments (MOM),
96Digital communications, Architectures and circuits (CACS) and Knowledge,
97information and decision (CID). The Lab-STICC represents a staff of 279
98peoples, including 115 researchers and 113 PhD students.
99The scientific production during the last 4 years represents 20
100books, 200 journal publications, 500 conference publications, 22
101patents, 69 PhDs diploma.
102\parlf
103The UBS/Lab-STICC laboratory is involved in several national research
104projects (e.g. RNTL : SystemC'Mantic, EPICURE - RNRT : MILPAT, ALIPTA,
105A3S - ANR : MoPCoM, SoCLib, Famous, RaaR, AFANA, Open-PEOPLE, ICTER ...),
106CMCU project (COSIP) and regional projects (e.g. ITR projects PALMYRE
107...). It is also involved in European Project (e.g. ITEA/SPICES,
108IST/AETHER ...). These projects are conducted through tight cooperation
109with national and international companies and organizations (e.g. France
110Telecom CNET, MATRA, CEA, ASTRIUM, \thales Com., \thales Avionics, AIRBUS,
111BarCo, STMicroelectronics, Alcatel-Lucent ...). Results of those or former
112projects are for example the high-level synthesis tool GAUT, the UHLS
113syntax and semantics-oriented editor, the DSP power estimation tool
114Soft-explorer or the co-design framework Design Trotter.
115\parlf
116The CACS department of the Lab-STICC (also referred as UBS/Lab-STICC),
117located in Lorient, is involved in COACH.
118The UBS/Lab-STICC is working on the design of complex electronic systems
119and circuits, especially but not exclusively focussing on real-time
120embedded systems, power and energy consumption optimization, high-level
121synthesis and IP design, digital communications, hardware/software
122co-design and ESL methodologies. The application targeted by the
123UBS/Lab-STICC are mainly from telecommunication and multimedia domains
124which enclose signal, image, video, vision, and communication processing.
125
126%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
127\subsubsection{\upmc}
128
129University Pierre et Marie Curie (UPMC)  is the largest university in France (7400
130employees,38000 students).
131The Laboratoire d'Informatique de Paris 6 (LIP6) is the computer science laboratory of
132UPMC, hosting more than 400 researchers, under the umbrella of the CNRS (Centre National
133de la Recherche Scientifique).
134The \og System on Chip \fg Department of LIP6 consists of  80 people, including 40 PHD
135students.
136The research focuses on CAD tools and methods for VLSI and System on Chip design.
137\\
138The annual budget is about 3 M{\texteuro}, and 1.5 M{\texteuro} are from research contracts.
139The SoC department has been involved in several european projects :IDPS, EVEREST, OMI-HIC,
140OMI-MACRAME, OMI-ARCHES, EUROPRO, COSY, Medea SMT, Medea MESA, Medea+ BDREAMS, Medea+
141TSAR.
142\parlf
143The public domain VLSI CAD system ALLIANCE, developped at UPMC is installed in more than
144200 universities worldwide.
145The LIP6 is in charge of the technical coordination of the SoCLib national project, and is
146hosting the SoCLib WEB server.
147The SoCLib DSX component was designed and developped in our laboratory.
148It allows design space exploration and will the base of the $CSG$ COACH tools.
149Moreover, the LIP6 developped during the last 10 years the UGH tool for high level
150synthesis of control-dominated coprocessors.
151This tool will be modified to be integrated in the COACH design flow.
152\parlf
153Even if the preferred dissemination policy for the COACH design flow will be the free
154software policy, (following the SoCLib model), the SoC department is ready to support
155start-ups : Six startup companies (including \zied) have been created by former
156researchers from  the SoC department of LIP6 between 1997 and 2002.
157
158%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
159\subsubsection{\xilinx}
160
161\xilinx is the world leader in the domain of programmable logic circuits (FPGA).
162\xilinx develops on one hand several FPGA architectures (CoolRunner, Spartan and Virtex
163families) and on the other hand a software solution allowing exploiting the
164characteristics of these FPGA.
165\parlf
166The tools proposed allow the designer to describe his architecture from a modeling
167language (VHDL/Verilog) to an optimized architecture implemented to the selected
168technology.
169The team located at Grenoble is responsible of the logic synthesis tool development (XST)
170of the software solution, which aggregates all the steps allowing proceeding from a  HDL
171model to a technological netlist:
172\begin{itemize}
173  \item Compilation of HDL code and model generation at Register Transfer Level (RTL).
174  \item RTL model optimizations.
175  \item Inference and generation of optimized macro blocks (Finite states machine, counter).
176  \item Boolean equations generation for random logic.
177  \item Logical, mapping and timing optimizations.
178\end{itemize}
179\parlf
180The architectures developed by \xilinx offer a collection of technological primitives
181(variable complexity) from simple Boolean generators (LUT) to complex DSP blocks or memory
182and even configurable processor cores (Pico and MicroBlaze families).
183This kind of architecture allows, therefore, the designer to validate different
184hardware/software possibilities in a High Level Synthesis (HLS) framework.
185\parlf
186The classical optimization techniques focus, mainly, on the frequency aspects and on
187available resources use.
188The optimizations, taking into account the consumption criteria, become critical due to
189the fact of the increase of the architecture complexity and due to the use of FPGA
190component for low power applications.
191
192%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
193\subsubsection{\bull}
194
195\bull designs and develops servers and software for an open environment, integrating the
196most advanced technologies. It brings to its customers its expertise and know-how to help
197them in the transformation of their information systems and to optimize their IT
198infrastructure and their applications.
199\parlf
200\bull is particularly present in the public sector, banking, finance, telecommunication
201and industry sectors. Capitalizing on its wide experience, the Group has a thorough
202understanding of the business and specific processes of these sectors, thus enabling it to
203efficiently advise and to accompany its customers. Its distribution network spreads to
204over 100 countries worldwide.
205\parlf
206The team participating to the COACH project is from the Server Development Department
207based in Les Clayes-sous-Bois, France. The SD Department is in charge of developing
208hardware for open servers (e.g. NovaScale) and HPC solutions. Its main activities range
209from architecture specification, ASIC design/verification/prototyping to board design and
210include also specific EDA development to complement standard tools.
211
212%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
213\subsubsection{\thales}
214
215\thales is a world leader for mission critical information systems, with activities in 3
216core businesses: aerospace (with all major aircraft manufacturers as customers), defence,
217and security (including ground transportation solutions). It employs 68000 people
218worldwide, and is present in 50 countries. \thales Research \& Technology operates at the
219corporate level as the technical community network architect, in charge of developing
220upstream and \thales-wide R \& T activities, with vision and visibility. In support of
221\thales applications, TRT's mission is also to anticipate and speed up technology transfer
222from research to development in Divisions by developing collaborations in R\&T. \thales is
223international, but Europe-centered. Research \& Development activities are disseminated,
224and corporate Research and Technology is concentrated in Centres in France, the United
225Kingdom and the Netherlands. A key mission of our R\&T centres is to have a bi-directional
226transfer, or "impedance matching" function between the scientific research network and the
227corresponding businesses. The TRT's Information Science and Technology Group is able to
228develop innovative solutions along the information chain exploiting sensors data, through
229expertise in: computational architectures in embedded systems, typically suitable for
230autonomous system environments, mathematics and technologies for decision involving
231information fusion and cognitive processing, and cooperative technologies including man
232system interaction.
233\parlf
234The Embedded System Laboratory (ESL) of TRT involved in the COACH project is part of the
235Information Science and Technology Group. Like other labs of TRT, ESL is in charge of
236making the link between the needs from \thales business units and the emerging
237technologies, in particular through assessment and de-risking studies. It has a long
238experience on parallel architectures design, in particular on SIMD architectures used for
239image processing and signal processing applications and on reconfigurable architectures.
240ESL is also strongly involved in studies on programming tools for these types of
241architectures and has developed the SpearDE tool used in this project. The laboratory had
242coordinated the FP6 IST MORPHEUS project on reconfigurable technology, being highly
243involved in the associated programming toolset. The team is also involved in the FP6 IST
244FET AETHER project on self-adaptability technologies and coordinates national projects on
245MPSoC architecture and tools like the Ter\verb+@+ops project (P\^{o}le de
246Comp\'{e}titivit\'{e} System\verb+@+tic) dedicated to the design of a MPSoC for intensive
247computing embedded systems.
248
249%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
250\subsubsection{\zied}
251
252\zied is an innovative start-up specialized in the conception of configurable circuits
253and the development of CAD tools. \zied provides a complete front-to-back-end generator
254of "hardware" reprogrammable IP cores that can be embedded in ASIC and ASSP SoC designs.
255\zied solution is based on a patented FPGA architecture delivering an unprecedented
256level of logic density. This high capacity is accessible using a traditional RTL flow from
257Verilog/VHDL synthesis all the way to bitstream generation.
258\parlf
259\zied is a spin-off from LIP6 (Laboratoire Informatique Paris 6) and was awarded at the
260French National Competition for Business Startup and Innovative Technology in 2007 and
2612009 in "emergence" and "creation" categories respectively.
262
263%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
264\subsubsection{\navtel}
265
266\navtel was created in 1994 to develop flexible systems based on FPGAs and currently
267focuses on intelligent signal mining for knowlege based signal processing systems.
268The company main activity covers the following domains: satellite communication,
269aeronautics, imaging and security.
270\navtel dedicates about 70\% of its activity to client projects in satellite, aeronautical
271and imaging systems and 30\% to its own research programmes in collaboration with French
272and international partners.
273\parlf
274The multi disciplinary technical team comprises 6 engineers for signal processing and
275hardware development and one technician.
276\parlf
277\navtel has its own Ph.D program which includes in the past (classification technology
278and MIMO for FPGA implementation) and currently the preparation of a project for remote
279sensing with signal intelligence for satellite application. The company participates in
280national and European level projects contributing to a strategic alliance between academic
281and  industrial partners.\\
282The current research covers particle filter applications for communication and RADAR,
283Cognitive Radio, Satellite communication, embedded super computing and focuses on low
284power algorithms for implementation in FPGA and  soft computing.
285\parlf
286For manufacturing and industrialization, \navtel works with ISO certified partners.
287The company clients include the CNES, Thal\`{e}s Alenia Space, Thal\`{e}s Communication, EADS,
288Eutelsat, AIRBUS, Schlumberger. \navtel participates from the R\&D phase up to the
289system delivery.
290\begin{description}
291\item[Recognitions:]\mbox{}
292\begin{itemize}
293  \item HEC Challenge+  program for innovative projects (promotion 9)
294  \item Innovation and technology development \og Troph\'{e}es R\'{e}gion Centre \fg
295  \item Recognition by the French Senate for company creation  during the
296        \og Semaine de l'entrepreneur \fg 2005.
297\end{itemize}
298\end{description}
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