source: anr-2010/task-3.tex @ 385

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1\begin{taskinfo}
2\let\LIP\leader
3\let\IRISA\enable
4\let\UBS\enable
5\let\UPMC\enable
6\let\TIMA\enable
7\end{taskinfo}
8%
9\begin{objectif}
10The objective of this task is to convert the input specification of
11an hardware accelerator, which must be written in a familiar language
12(C/C++) with as few constraints as possible, into a form suitable for
13the HLS tools (i.e. HAS back-end tools of the COACH project). If the
14target is an ASIP, the frontend has to extract
15patterns from the source code and convert them into the definition
16of an extensible processor. If the target is a process network, the
17front end has to distribute the workload and the data sets as fairly
18as possible, identify communication channels, and output an \xcoach
19description.
20\end{objectif}
21%
22\begin{workpackage}
23  \subtask This sub-task aims at providing compiler support for custom instructions
24  within the HAS front-end. It will take as input the COACH intermediate
25  representation, and will output an annotated COACH IR containing the custom
26  instructions definitions along with their occurrence in the application.
27    \begin{livrable}
28      \itemV{0}{18}{x}{\Sirisa}{ASIP compilation flow}
29        In this first version of the software, the computations patterns corresponding to
30        custom instructions are specified by the user, and then automatically extracted (when
31        beneficial) from the application intermediate representation.
32      \itemL{18}{24}{x}{\Sirisa}{ASIP compilation flow}{6:9:0}
33        In this second version, the software will also be able to automatically identify
34        interesting pattern candidates in the application code, and use them as custom
35        instructions. 
36    \end{livrable}
37 
38 \subtask In this sub-task, we provide micro-architectural template models for the two target
39 processor architectures (NIOS-II and MIPS) supported within the COACH-ASIP design flow.
40 For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL)
41 of the architecture, along with its architectural extensions
42    \begin{livrable}
43      \itemV{0}{12}{x}{\Sirisa}{SystemC for extensible MIPS }
44      { A SystemC simulation model for a simple extensible MIPS architectural template }
45      \itemL{12}{20}{x}{\Sirisa}{SystemC for extensible MIPS}{2:3:0}
46      {A SystemC simulation model for an extensible MIPS with a tight architectural integration of
47      its instruction set extensions}
48      \itemL{0}{12}{x}{\Sirisa}{SystemC for NIOS processor}{2:0:0}
49          { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being
50          already available from \altera}
51      \itemV{3}{18}{h}{\Sirisa}{VHDL for an extensible MIPS}
52      {A synthesizable VHDL model for a simple extensible MIPS architectural template}
53      \itemL{18}{24}{h}{\Sirisa}{VHDL for extensible MIPS}{9:12:0}
54      {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of
55      its instruction set extensions}
56      \itemL{24}{36}{d}{\Sirisa}{Evaluation report }{0:0:2}
57      {An evaluation report with quantitative analysis of the performance/area trade-off induced by
58      the different approaches}
59    \end{livrable}
60
61  \subtask Extraction of parallelism in polyhedral loops and conversion into a process network.
62
63   \begin{livrable}
64    \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition}
65      Description and specification of a process construction method for programs with
66      polyhedral loops.
67    \itemL{30}{36}{d}{\Slip}{Process generation method}{10:0:9}
68      Final assessment of the method and improved version of the specification.
69    \itemV{6}{12}{x}{\Slip}{Process construction}
70      Preliminary implementation in the Syntol framework.
71      At this step the software will just implement a single constructor.
72    \itemV{12}{18}{x}{\Slip} {Arrays and FIFO}
73      Implementation of the array contraction and FIFO construction algorithm.
74      Conversion of the input and output to the \xcoach format.
75    \itemV{18}{30}{d+x}{\Slip}{Non-polyhedral extension}
76      Extension of automatic parallelization and array contraction
77      to non-polyhedral loops. Implementation in the Bee framework.
78    \itemL{30}{36}{x}{\Slip} {Process/FIFO construction}{10:20:12}
79      Final release taking into account the feedbacks from the
80      demonstrator \STs.
81   \end{livrable}
82
83\end{workpackage}
84   
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