source: anr-2010/task-4.tex @ 277

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1\begin{taskinfo}
2\let\UBS\leader
3\let\UPMC\enable
4\let\TIMA\enable
5\let\XILINX\enable
6\end{taskinfo}
7%
8\begin{objectif}
9The objectives of this task are to provide the two HAS back-ends of the COACH project and
10a tool that adapt the coprocessor frequency to the FPGA-SoC frequency as required
11by the processors and the system BUS.
12%pourquoi en majuscule?
13\\
14The HAS back-ends as shown in figure~\ref{archi-hls} reads an \xcoach description and provides an
15\xcoachplus description, i.e. an \xcoach description  annotated with hardware information such as
16variables binding to registers, operations bindings to cells/fonctional units, operation scheduling...
17The \xcoach format being generated by the \novers{\specXcoachToCA} deliverable and the \xcoachplus being treated by
18the \novers{\specXcoachToSystemC} and the \novers{\specXcoachToVhdl} deliverables,
19this task strongly depends on task~1.
20\par
21For the two HAS front-end, this task is based on the already existing HLS tools GAUT and
22UGH. These tools are complementary and not in competition because they cover respectively
23data and control dominated designs.
24The organization of the task is firstly to quickly integrate the existing HLS to the COACH
25framework. Secondly these tools will be improved to allows to treat data dominated application
26with a few control for GAUT and control dominated application with a few data processing
27for UGH. This will enlarge the domain the HLS can cover which is a strong limitation of the
28tools currently avilable \cite{HLSBOOK} \cite{IEEEDT} \cite{CATRENE}.
29\end{objectif}
30
31%FIXMA == {il faudrait fusionner les taches ST5-1 et ST5-2, non ???}
32\begin{workpackage}
33\subtask The goal of this \ST is to integrate the UGH HLS tool to the COACH framework. It
34    consists of suppressing the C compiler and the SystemC and VHDL drivers and replacing
35    them by \xcoach and \xcoachplus drivers i.e. C2X, X2SC and X2VHDL.
36    \begin{livrable}
37    \itemL{6}{12}{x}{\Stima}{UGH integration}{12:0:0}
38        Release of the UGH software that reads \xcoach format.
39    \itemV{12}{18}{x}{\Supmc}{UGH integration}
40        Release of the UGH software that writes \xcoachplus format.
41    \itemL{18}{33}{x}{\Supmc}{UGH integration}{0:2:4.0}
42        Final release of the UGH software.
43    \end{livrable}
44\subtask The goal of this \ST is to integrate the GAUT HLS tool to the COACH framework. It
45    consists of suppressing the C compiler and the SystemC and VHDL drivers and replacing
46    them by \xcoach and \xcoachplus drivers.
47    \begin{livrable}
48    \itemL{6}{12}{x}{\Subs}{GAUT release reading \xcoach}{6:0:0}
49        Release of the GAUT software that is able to read \xcoach format.
50    \itemL{12}{18}{x}{\Subs}{GAUT release writing \xcoachplus}{0:6:0}
51        Release of the GAUT software that is able to read \xcoach format and to write \xcoachplus format.
52    %\itemL{18}{33}{x}{\Subs}{Final release of GAUT}{0:1:6}
53     %   Final release of the GAUT software.
54    \end{livrable}
55\subtask The goal of this \ST is to improve the UGH and GAUT HLS tools.
56    UGH and GAUT experimentations have shown respectively usefull enhancements.
57    \begin{livrable}
58    \itemL{18}{24}{x}{\Stima}{UGH enhancement 1}{0:9:0}
59        Release of the UGH software with support for treating automatically data dominated sections
60        included into a control dominated application.
61    \itemL{21}{27}{x}{\Stima}{UGH enhancement 2}{0:3:6}
62        Release of the UGH software able to generate a micro-architecture without the
63        variable binding currently done by the designer.
64    \itemL{12}{24}{x}{\Subs}{Release of GAUT with \ganttlf enhanced synthesis steps}{0:9:0}
65        Release of the GAUT software that supports the \xcoach model during the binding and the scheduling steps.
66    \itemL{24}{33}{x}{\Subs}{Release of GAUT supporting \ganttlf new const./obj.}{0:0:7}
67        Release of the GAUT software that supports the \xcoach model during the binding and the scheduling steps
68        and also supports new constraints and objectives.
69    \itemV{18}{24}{d}{\Subs}{Micro-architecture Exploration}\setMacroInAuxFile{MAE}
70        Specification of a Design Space Exploration framework for the HAS Back-end:
71        The high level specification tools, such as GAUT, have to be able to use synthesis feed-back
72        informations in order to explore the design space and to generate optimized architectures.
73    \itemL{24}{36}{x}{\Subs}{Micro-architecture Exploration}{0:4:4}
74        Release of the GAUT software that supports the features defined in \MAE
75    \end{livrable}
76\subtask In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors
77    generated by HLS synthesis must respect this frequency. However, the HLS tools can not
78    guarantee that the micro-architectures they generate accurately respect this
79    frequency. This is especially the case when the target is a FPGA device, because the
80    delays are really known only after the RTL synthesis and that estimated delays used
81    by the HLS are very inaccurate. The goal of this \ST is to provide a tool that adapts
82    the coprocessors frequency to the FPGA-SoC frequency after the coprocessor RTL
83    synthesis.
84    \begin{livrable}
85    \itemV{0}{12}{d}{\Supmc}{Frequency calibration}
86        A document describing the set up of the coprocessor frequency calibration.:
87    \itemV{12}{24}{x}{\Supmc}{Frequency calibration}
88        \setMacroInAuxFile{freqCalibrationVhdl}
89        A VHDL description of hardware added to the coprocessor to enable the calibration.
90    \itemL{24}{33}{x}{\Supmc}{Frequency calibration}{2:.5:3.5}
91        The frequency calibration software consists of a driver in the FPGA-SoC operating
92        system and of a control software.
93    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (5)}{0:0:1.5}
94       This deliverable consists in optimizing the VHDL description provided in
95       \novers{\freqCalibrationVhdl}.
96       \upmc will provide the VHDL description, \xilinx will provide back a documentation
97       listing that proposes VHDL generation enhancements.
98    \end{livrable}
99\end{workpackage}
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