source: anr-2010/task-6.tex @ 317

Last change on this file since 317 was 268, checked in by coach, 15 years ago

IA: thales updates

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1\begin{taskinfo}
2\let\BULL\enable
3\let\THALES\leader
4\let\NAVTEL\enable
5\let\ZIED\enable
6\end{taskinfo}
7%
8\begin{objectif}
9This task groups the demonstrators of the COACH project.
10The demonstrators cover various domains and application types to drive
11the specification choices and to check most of the COACH features.
12\end{objectif}
13%
14\begin{workpackage}
15  \subtask
16    The application that \bull proposes is HPC oriented.
17    The domain of the application is the treatment of medical images (image noise
18    reduction and segmentation or registration).
19    Our expectation from COACH project is to enhance the \bull HPC solutions that
20    are currently based on multi-cores and GPUs with fine grain parallelism on FPGA.
21    \begin{livrable}
22      \itemV{0}{6}{d}{\Sbull}{\bull demonstrator}
23        The deliverable is a document that describes the application that will be use as
24        demonstrator.
25      \itemV{6}{12}{x}{\Sbull}{\bull demonstrator}
26        The deliverable is the specification of the demonstrator in COACH input format
27        defined in the {\specGenManual} deliverable.
28      \itemL{12}{36}{d}{\Sbull}{\bull demonstrator}{2:6:10}
29        Validation of the demonstrator, the deliverable is a document
30        describing the result of the experimentations.
31    \end{livrable}
32
33  \subtask
34    The objective of this sub-task is to specify the THALES application and to develop the
35    high level code.  This application is in the domain of surveillance of critical
36    infrastructures. The objective is to detect and classify the presence of humans in the
37    restricted area. The algorithm is based on the work of Viola and
38    Jones~\cite{thales-viola}. It implements in particular a cascade of classifiers
39    operating on Haar like features, where simple weak classifiers at the beginning of the
40    cascade reject a majority of void sub-windows, before more complex classifiers
41    concentrate on potential regions of interest. This application is computation
42    intensive and also makes an intensive use of binary decision trees to cascade the
43    filters, which makes it a good candidate to assess the COACH platform.
44    \\
45    Moreover, the higher levels of computing can involve tracking and data fusion between
46    several camera streams and some other informations.
47    The targeted system will be composed of one camera connected to a PC.
48    All the computing part of the application is executed on a FPGA board connected to the
49    PC.
50    \begin{livrable}
51      \itemV{0}{6}{d}{\Sthales}{\thales demonstrator (step 1)}
52        \setMacroInAuxFile{trtAppSpecification}
53        This deliverable is a document that specifies the application.
54      \itemL{6}{12}{x}{\Sthales}{\thales demonstrator (step 1)}{4:0:0}
55        This deliverable is the code of the application spcecified former
56        deliverable (\trtAppSpecification).
57    \end{livrable}
58
59  \subtask \TRT will use its internal software environment tool SPEAR DE to describe the
60    application. The tool is able to partition and to generate the code for the target. \\
61    In this task, we will adapt SPEAR DE to generate the application description input of
62    COACH framework. We will also describe the three templates of architecture in order to
63    be able to partition the application on the architecture.
64    \begin{livrable}
65      \itemL{6}{18}{x}{\Sthales}{SPEAR-DE adaptation}{6:7:0}
66        \setMacroInAuxFile{trtSpearde}
67        Adaptation of SPEAR-DE for COACH framework.
68    \end{livrable}
69
70  \subtask 
71    In this sub-task, \TRT will evaluate the COACH platform. In particular, \TRT will verify
72    its ability to generate a whole VHDL of an embedded system on FPGA for an application
73    mixing control and data flow aspects. \TRT will evaluate the performance of the
74    generated system in terms of GOPS, and the design time from a high level description.
75    \begin{livrable}
76      \itemV{18}{24}{d+x}{\Sthales}{\thales demonstrator (step 2)}
77        This deliverable is a document describing the result got for the application
78        (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+18.
79        The updated code of the application will be also provide.
80      \itemV{24}{30}{d+x}{\Sthales}{\thales demonstrator (step 2)}
81        This deliverable is a document describing the result got for the application
82        (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+24.
83        The updated code of the application will be also provide.
84      \itemL{30}{36}{d+x}{\Sthales}{\thales demonstrator (step 2)}{0:5:5}
85        This deliverable is a document that validates and evaluates COACH (final release)
86        for the \thales demonstrators (\trtAppSpecification).
87        The updated code of the application will be also provide.
88    \end{livrable}
89
90  \subtask FLEXRAS will design an application based on M-JPEG video standard.
91        FLEXRAS will propose a SoC architecture integrating an embedded FPGA (eFPGA).
92    The architecture is composed essentially of a processor, a bus and several RAMs.
93    The embedded FPGA is connected to the bus and communicates with the other components.
94    The (eFPGA) works in 2 modes:
95    \begin{description}
96      \item[Slave mode]
97        As a DMA, the processor will send the configuration bitstream
98        stored on the RAM to the eFPGA. In this mode, the eFPGA is considered as a
99        writeable memory and is configured by the processor.
100      \item[Master mode]
101        Once the FPGA is programmed, it becomes a coprocessor achieving the aimed task.
102    \end{description}
103      The top architecture of this SoC based-platform will be generated using COACH
104      framework. The application that will be run on the SoC corresponds initially to a
105      graph of software tasks. Critical tasks will be identified and transformed
106      automatically to hardware tasks using COACH high level synthesis feature. While
107      software tasks will be run on the processor, hardware ones will be mapped on eFPGA
108      to take advantage of its optimized resources and parallelism. FLEXRAS provides all
109      the flow from RTL synthesis to bitstream generation.
110    \begin{livrable}
111      \itemL{0}{6}{d}{\Szied}{\zied architecture}{2.4:0:0}
112        FLEXRAS will use IPs provided by LIP6 (vhdl models of SoCLIB) and its eFPGA IP to
113        generate the SoC architecture.
114        This deliverable is a document that describes this architecture.
115      \itemL{6}{18}{h}{\Szied}{eFPGA/VCI component}{3.6:3.6:0}
116        FLEXRAS has to adapt the eFPGA interface to connect it to the VCI bus.
117        This deliverable is a VHDL description.
118%      \itemL{12}{18}{x}{\Szied}{bitstream loader port}{0:3.6:0}
119%        Port of the bitstream loader to the MUTEKH operating system.
120      \itemL{18}{24}{x}{\Szied}{\zied demonstrators}{0:2.4:0}
121        \zied will propose to test COACH framework and the \zied architecture template
122        throught an application based on M-JPEG video standard.
123        This applicattion will containt 3 communicating tasks under the COACH format specified
124        in {\novers{\specGenManual}} deliverable.
125        The first one is a hardware task generated by the HAS tools and transformed into
126        a bit stream by the \zied tools.
127        The second is a bitstream loader that will load the bitstream of the first task on
128        the eFPGA.
129        The third is a software task that communicates with the hw task for testing it.
130      \itemL{24}{30}{x}{\Szied}{eFPGA characterisation}{0:0:2.4}
131        This deliverable is a file under the format defined by the deliverable
132        {\specMacroCell} that characterizes the eFPGA. This will allow the COACH HLS tools
133        to take into account the eFPGA delays.
134      \itemL{30}{36}{d}{\Szied}{\zied evaluation}{0:0:3.6}
135        This deliverable is a document that describes the tests, the validation and the
136        evaluation of COACH with the \zied architecture and tools.
137    \end{livrable}
138
139  \subtask
140  The \navtel Embedded Supper Computing (ESC) project is based on simple hardware but tightly
141  coupled module between %ARM
142  a embedded processor and an FPGA both on a board.
143  By using the COACH environment, \navtel will automatically synthetize two cores: one for software radio
144  through a polyphase resampler and one for an industrial control application through an embedded
145  PID controller.
146  The objective is to sequence the cores in realtime in FPGA using partial configuration methods
147  proposed in the COACH project.
148  This will allow us to gain experience on automatic multi core sequencing at system level. The
149  specification for our first work package will concern this aspect.
150
151  The ESC can function on different topologies: Single, parallel or Grid computing modes for
152  industrial and scientific applications.
153  %The ARM
154  The processor and FPGA configuration also facilitate the co-simulation which allows to  gain
155  time on the development and integration phase.
156  The architecture consists of a wrapper that encapsules computing units depending on the
157  application and a real time kernal for task switching and partial reconfiguration of FPGA
158  on run time environment.
159  \parlf
160  To day \navtel develops these computing units manually.
161  \navtel expects to benefit from the COACH project especially the HLS tools for
162  generating the computing unit.
163  \begin{livrable}
164    \itemL{0}{6}{d}{\Snavtel}{\navtel \ganttlf demonstrator specification}{4:0:0}
165        \setMacroInAuxFile{navtelSpecification}
166        A document that will define the requirements for automatic RTL generation for
167        signal processing units of our market sector such as digital communication,
168        imaging and industrial control.
169        This document will include the description of some already handmade processing units.
170    \itemL{6}{18}{h}{\Snavtel}{\navtel \ganttlf wrapper adaptation}{1:1:0}
171                The adaptation of our wrapper to support coprocessor generated by COACH.
172    \itemL{18}{36}{d}{\Snavtel}{\navtel evaluation}{0:2:4}
173                \navtel will test the COACH HLS tools on the processing units that are described
174        in the {\navtelSpecification} deliverable.
175                A document will be written that describes the results obtained taking into
176        account: 1) the performance in terms of space, 2) the performance in terms of
177        time, 3) the friendlyness of the environment.
178    \end{livrable}
179\end{workpackage}
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