source: anr/anr.bib @ 100

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%% LIP6
% HPC
@InProceedings{hpc06a,
  author    = {{M.B. Gokhale and al.}},
  title     = {{Promises and Pitfalls of Reconfigurable Supercomputing}},
  booktitle = {Systems and Algorithms, CSREA Press},
  pages     = {11-20},
  year      = {2006},
}
@MISC{hpc06b,
  author =       {{D. Buell}},
  title  =   {{Programming Reconfigurable Computers}},
  booktitle = {Summer Institute},
  howpublished = {http://gladiator.ncsa.uiuc.edu/PDFs/rssi06/presentations/00\_Duncan\_Buell.pdf},
  year =         {2006},
}
@InProceedings{hpc07a,
  author =       {{T. Van Court and al.}},
  title  =   {{ Achieving High Performance with FPGA-Based Computing}},
  booktitle = {Computer, vol. 40, no. 3},
  pages     = {50-57},
  month     = {mars},
  year =         {2007},
}
@misc{hpc08,
  title        = {Mitrionics},
  howpublished = {http://www.mitrionics.com/},
  year         = {2009},
}
@misc{hpc09,
  title        = {Gidel},
  howpublished = {http://www.gidel.com/},
  year         = {2009},
}
@misc{hpc10,
  title        = {Convey Computer},
  howpublished = {http://www.conveycomputers.com/},
  year         = {2009},
}
@InProceedings{hpc11,
  author =      {E. El-Araby, I. Gonzalez and T. El-Ghazawi},
  title   = {Virtual Architecture and Design Automation for Partial Reconfiguration },
  booktitle = {HPRCTA},
  year =         {2008},
}
@InProceedings{hpc12,
  author =       {{P. Lysaght and J. Dunlop}},
  title   = {Dynamic Reconfiguration of Field Programmable Gate Arrays},
  booktitle = {Field Programmable Logic and Applications, Oxford, England},
  month     = {Sept},
  year =         {1993},
}


% System design
@misc{soclib,
  title        = {Soclib},
  howpublished = {http://www.soclib.fr/},
  year         = {2009},
}

@misc{system-generateur-for-dsp,
  title        = {{System Generator for DSP}},
  howpublished = {http://www.xilinx.com/tools/sysgen.htm},
  year         = {2009},
}

@misc{spoc-builder,
  title        = {{sopc builder support}},
  howpublished = {http://www.altera.com/support/software/system/sopc/sof-sopc\_builder.html},
  year         = {2009},
}

@InProceedings{disydent05,
  author =       {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, Franï¿œois Donnet and Pascal Gomez}},
  title =        {{Platform-based design from parallel C specifications}},
  booktitle = {IEEE Transaction on CAD of Integrated Circuits and Systems},
  pages     = {1811--1826},
  month     = {December},
  year =         {2005},
}

% HLS
% http://mesl.ucsd.edu/spark/index.shtml
@BOOK{spark04,
  author     = {S. Gupta and al.},
  title      = {SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits},
  publisher  = {Springer},
  year       = {2004},
}


@INBOOK{ugh08,
  author    = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot},
  title     = {User Guided High Level Synthesis},
  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
  publisher = {Springer},
  chapter   = {10},
  year      = {2008},
}

@misc{pico,
  title        = {{PICO}},
  howpublished = {http://www.synfora.com/},
  year         = {2009},
}

@misc{catapult-c,
  title        = {{CATAPULT-C Mentor HLS tool}},
  howpublished = {http://www.mentor.com/products/esl/high\_level\_synthesis/},
  year         = {2009},
}

@misc{cynthetizer,
  title        = {{Forte's CYNTHESIZER}},
  howpublished = {http://www.forteds.com/},
  year         = {2009},
}



%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%% UBS


@INBOOK{gaut08,
  author    = {P. Coussy and al.},
  title     = {GAUT: A High-Level Synthesis Tool for DSP applications},
  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
  publisher = {Springer},
  year      = {2008},
}

@article{DBLP:journals/dt/CoussyT09,
  author    = {Philippe Coussy and
               Andres Takach},
  title     = {Guest Editors' Introduction: Raising the Abstraction Level
               of Hardware Design},
  journal   = {IEEE Design {\&} Test of Computers},
  volume    = {26},
  number    = {4},
  year      = {2009},
  pages     = {4-6},
  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.80},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}


@article{DBLP:journals/dt/CoussyGMT09,
  author    = {Philippe Coussy and
               Daniel D. Gajski and
               Michael Meredith and
               Andres Takach},
  title     = {An Introduction to High-Level Synthesis},
  journal   = {IEEE Design {\&} Test of Computers},
  volume    = {26},
  number    = {4},
  year      = {2009},
  pages     = {8-17},
  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.69},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}


@article{DBLP:journals/vlsisp/ThabetCHM09,
  author    = {Farhat Thabet and
               Philippe Coussy and
               Dominique Heller and
               Eric Martin},
  title     = {Exploration and Rapid Prototyping of DSP Applications using
               SystemC Behavioral Simulation and High-level Synthesis},
  journal   = {Signal Processing Systems},
  volume    = {56},
  number    = {2-3},
  year      = {2009},
  pages     = {167-186},
  ee        = {http://dx.doi.org/10.1007/s11265-008-0235-1},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}



@inproceedings{CHAVET:2007:HAL-00153994:1,
        title = { {A} {M}ethodology for {E}fficient {S}pace-{T}ime {A}dapter {D}esign {S}pace {E}xploration: {A} {C}ase {S}tudy of an {U}ltra {W}ide {B}and {I}nterleaver},
        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
        abstract = {{T}his paper presents a solution to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {T}he {RCG} properties enable an efficient architecture space exploration in order to synthesize a {STAR} component. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
        language = {{A}nglais},
        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
        booktitle = {{P}roceedings of the {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) {T}he {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) },
        publisher = {{L}ibrary of {C}ongress },
        pages = {2946 },
        address = {{N}ew {O}rleans {\'E}tats-{U}nis d'{A}m{\'e}rique },
        editor = {{IEEE} },
        note = {{ISBN}:1-4244-0921-7 },
        audience = {internationale },
    day = {28},
    month = {05},
    year = {2007},
    URL = {http://hal.archives-ouvertes.fr/hal-00153994/en/},
    URL = {http://hal.archives-ouvertes.fr/hal-00153994/PDF/ISCAS_Chavet1992.pdf},
}


@inproceedings{DBLP:conf/iccad/ChavetACCJUM07,
  author    = {Cyrille Chavet and
               Caaliph Andriamisaina and
               Philippe Coussy and
               Emmanuel Casseau and
               Emmanuel Juin and
               Pascal Urard and
               Eric Martin},
  title     = {A design flow dedicated to multi-mode architectures for
               DSP applications},
  booktitle = {ICCAD},
  year      = {2007},
  pages     = {604-611},
  ee        = {http://doi.acm.org/10.1145/1326073.1326199},
  crossref  = {DBLP:conf/iccad/2007},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}


@inproceedings{DBLP:conf/glvlsi/ChavetCUM07,
  author    = {Cyrille Chavet and
               Philippe Coussy and
               Pascal Urard and
               Eric Martin},
  title     = {A design methodology for space-time adapter},
  booktitle = {ACM Great Lakes Symposium on VLSI},
  year      = {2007},
  pages     = {347-352},
  ee        = {http://doi.acm.org/10.1145/1228784.1228868},
  crossref  = {DBLP:conf/glvlsi/2007},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}


@inproceedings{CHAVET:2007:HAL-00154025:1,
        title = { {A}pplication of a design space exploration tool to enhance interleaver generation},
        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
        abstract = {{T}his paper presents a methodology to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {D}esign space exploration is then performed through associated tools, to synthesize a {STAR} component under time-to-market constraints. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
        language = {{A}nglais},
        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
        booktitle = {{P}roceedings of the {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) },
        publisher = {{E}urasip },
        pages = {??? },
        address = {{P}oznan {P}ologne },
        audience = {internationale },
    day = {03},
    month = {09},
    year = {2007},
    URL = {http://hal.archives-ouvertes.fr/hal-00154025/en/},
    URL = {http://hal.archives-ouvertes.fr/hal-00154025/PDF/EUSIPCO_chavet.pdf},
}


@inproceedings{ANDRIAMISAINA:2007:HAL-00153086:1,
        title = { {S}ynthesis of {M}ultimode digital signal processing systems},
        author = {{A}ndriamisaina, {C}aaliph and {C}asseau, {E}mmanuel and {C}oussy, {P}hilippe},
        abstract = {{I}n this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. {T}he inputs of the design flow are the data flow graphs ({DFG}s), representing the different modes (i.e. the different applications to be implemented), with their respective throughput constraints. {W}hile traditional approaches merge {DFG}s together before the synthesis process, we propose to use ad-hoc scheduling and binding steps during the synthesis of each {DFG}. {T}he scheduling, which assigns operations to specific time steps, maximizes the similarity between the control steps and thus decreases the controller complexity. {T}he binding process, which assigns operations to specific functional units and data to specific storage elements, maximizes the similarity between datapaths and thus minimizes steering logic and register overhead. {F}irst results show the interest of the proposed synthesis flow.},
        language = {{A}nglais},
        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {R}2{D}2 - {INRIA} - {IRISA} - {CNRS} : {UMR}6074 - {INRIA} - {I}nstitut {N}ational des {S}ciences {A}ppliqu{\'e}es de {R}ennes - {E}cole {N}ationale {S}up{\'e}rieure des {S}ciences {A}ppliqu{\'e}es et de {T}echnologie - {U}niversit{\'e} de {R}ennes 1 },
        booktitle = {{P}roceeding of {A}daptive {H}ardware and {S}ystems {NASA}/{ESA} {C}onference on {A}daptive {H}ardware and {S}ystems },
        publisher = {{AHS} },
        pages = {7 },
        address = {{E}dinburgh {R}oyaume-{U}ni },
        audience = {internationale },
    year = {2007},
    URL = {http://hal.archives-ouvertes.fr/hal-00153086/en/},
    URL = {http://hal.archives-ouvertes.fr/hal-00153086/PDF/PID411805.pdf},
}


@inproceedings{COUSSY:2005:HAL-00077301:1,
        title = { {A} {M}ore {E}fficient and {F}lexible {DSP} {D}esign {F}low from {MATLAB}-{SIMULINK}},
        author = {{C}oussy, {P}hilippe and {C}orre, {G}wenol{\'e} and {B}omel, {P}ierre and {S}enn, {E}ric and {M}artin, {E}ric},
        abstract = {{T}he design of complex {D}igital {S}ignal {P}rocessing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. {U}nfortunately, the traditional {M}atlab/{S}imulink design flows gather not very flexible hardware blocs. {I}n this paper, we present a methodology and a tool that permit the {H}igh-{L}evel {S}ynthesis of {DSP} applications, under both {I}/{O} timing and memory constraints. {B}ased on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. {T}he efficiency of our approach is demonstrated on the case study of a {FFT} algorithm.},
        keywords = {{DSP} application, synthesis under memory and communication constraints},
        language = {{A}nglais},
        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud },
        booktitle = {{IEEE} {I}nternational {C}onference on {A}coustic, {S}peech and {S}ignal {P}rocessing },
        publisher = {{IEEE} },
        pages = {{V}ol. {V} p. 61-64 },
        editor = {{IEEEE} },
    year = {2005},
    URL = {http://hal.archives-ouvertes.fr/hal-00077301/en/},
    URL = {http://hal.archives-ouvertes.fr/hal-00077301/PDF/coussy_final.pdf},
}



%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%% IRISA
@InProceedings{KluterCodes08,
  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
  title =        {{Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions}},
  booktitle = {ISSS/CODES},
  year =         {2008},
}

@InProceedings{KluterDAC09,
  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
  title =        {{Way Stealing : Cache-assisted Automatic Instruction Set Extensions}},
  booktitle = {Design Automation Conference (DAC)},
  year =         {2009},
}

@InProceedings{YuCodes04,
  author =       {{Pan Yu and Tulika Mitra}},
  title =        {{Scalable Custom Instructions Identification for Instruction Set Extensible Processors}},
  booktitle = {ISSS/CODES},
  year =         {2004},
}

@InProceedings{Dinh08,
  author =       {{Quang Dinh and Deming Chen and Martin D.~F.~Wong}},
  title =        {{Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing}},
  booktitle = {ACM Internatibnal Conference Field Programmable Gate Arrays (FPGA)},
  year =         {2008},
}

@Misc{NIOS2UG,
  title =        {{Nios II Custom Instruction User Guide, Altera Corp.}},
  year =         {2008},
}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%% CITI
@book{Polis,
  author = {Balarin, Felice},
  publisher = {Kluwer Academic Publishers},
  title = {Hardware-software co-design of embedded systems : the POLIS
        approach},
  year = {1997}
}

@INPROCEEDINGS{Coware,
  author = {Ivo Bolsens and Hugo J. De Man and Bill Lin and Karl Van
                Rompaey and Steven Vercauteren and Diederik Verkest},
  title = {Hardware/Software Co-Design of Digital Telecommunication Systems},
  booktitle = {Proceedings of the IEEE},
  year = {1997},
  pages = {391--418}
}

@article{Jantsch,
  author = {Mattias O'Nil and Axel Jantsch},
  title = {Device Driver and DMA Controller Synthesis from HW/SW
                        Communication protocol specifications},
  journal = {Design Automation for Embedded Systems},
  year = {2001},
  volume = {6},
  pages = {177-205}
}

@InProceedings{Park01,
  author =   {Joonseok Park and Pedro C.~Diniz},
  title =    {Synthesis of Pipelined Memory Access Controllers for Streamed
                Data Applications on {FPGA}-Based Computing Engines},
  booktitle =    {International Symposium on System Synthesis (ISSS)},
  pages = {221-226},
  year =     {2001},
}

@article{FR-vlsi,
  author = {Antoine Fraboulet and Tanguy Risset},
  title = {Master Interface for On-Chip Hardware Accelerator Burst Communications},
  journal = {Journal of VLSI Signal Processing},
  publisher = {Springer Science},
  year = {2007},
  volume = {59},
  pages = {73-85}
}

@InProceedings{jerraya,
  author =   {Sungjoo Yoo and Jerraya Ahmed},
  title =    {Introduction to Hardware Abstraction Layers for SoC},
  OPTcrossref =  {},
  OPTkey =   {},
  booktitle = {Design, Automation and Test in Europe Conference and Exhibition},
  pages =    {336 -- 337},
  year =     2003,
  OPTeditor =    {},
  OPTvolume =    {},
  OPTnumber =    {},
  OPTseries =    {},
  OPTaddress =   {},
  OPTmonth =     {},
  OPTorganization = {},
  OPTpublisher = {},
  OPTnote =      {},
  OPTannote =    {}
}

@INPROCEEDINGS{FAUST,
  author = {D. Lattard and  E. Beigne and  C. Bernard and  C. Bour and  F.
        Clermidy and  Y. Durand and  J. Durupt and  D. Varreau and  P. Vivet and
        P. Penard and  A. Bouttier and  F. Berens}, 
  title = "A Telecom Baseband Circuit-Based on an Asynchronous Network-on-Chip", 
  pages = {},
  BOOKTITLE="ISSCC\'2007", 
  year = {2007},
  publisher = {IEEE Computer Society},
  address = {San Francisco, USA},
};

@inproceedings{JerrayaPetrot,
 author = {Ahmed A. Jerraya and Aimen Bouchhima and Fr\'{e}d\'{e}ric P\'{e}trot},
 title = {Programming models and HW-SW interfaces abstraction for multi-processor SoC},
 booktitle = {DAC '06: Proceedings of the 43rd annual conference on Design automation},
 year = {2006},
 isbn = {1-59593-381-6},
 pages = {280--285},
 location = {San Francisco, CA, USA},
 publisher = {ACM},
 address = {New York, NY, USA},
}

@inproceedings{mwmr,
 author = {E. Faure and A. Greiner and D. Genius},
 title = {A generic hardware/software communication mechanism for
          Multi-Processor System on Chip, Targeting Telecommunication Applications},
 booktitle = {ReCoSoC'06},
 year = {2006},
 pages = {237--242},
 address = {Montpellier, France}
 }

@inproceedings{Alberto,
  author    = {Roberto Passerone and
               James A. Rowson and
               Alberto L. Sangiovanni-Vincentelli},
  title     = {Automatic Synthesis of Interfaces Between Incompatible Protocols},
  booktitle = {DAC},
  year      = {1998},
  pages     = {8-13}
}

@article{Avnit,
  author    = {Karin Avnit and
               Vijay D'Silva and
               Arcot Sowmya and
               S. Ramesh and
               Sri Parameswaran},
  title     = {Provably correct on-chip communication: A formal approach
               to automatic protocol converter synthesis},
  journal   = {ACM Trans. Design Autom. Electr. Syst.},
  volume    = {14},
  number    = {2},
  year      = {2009}
}

@inproceedings{smith,
  author    = {James Smith and
               Giovanni De Micheli},
  title     = {Automated Composition of Hardware Components},
  booktitle = {DAC},
  year      = {1998},
  pages     = {14-19}
}

@inproceedings{Narayan,
  author    = {Sanjiv Narayan and
               Daniel Gajski},
  title     = {Interfacing Incompatible Protocols Using Interface Process
               Generation},
  booktitle = {DAC},
  year      = {1995},
  pages     = {468-473}
}

@TECHREPORT{Ptolemy,
  AUTHOR       = { E.A. Lee et al.},
  INSTITUTION  = {University of California, Berkeley},
  NUMBER       = {UCB/ERL No. M99/37},
  TITLE        = {Overview of the Ptolemy Project},
  YEAR         = {1999},
  MONTH        = {july}
}

@article{syntol,
    author={Paul Feautrier},
    title={Scalable and Structured Scheduling},
    journal={Int. J. of Parallel Programming},
    year=2006,
    month=May, number=5, volume=34,
    pages="459--487"
}

@InProceedings{bee,
  author={Christophe Alias and Fabrice Baray and Alain Darte},
  title={Bee+Cl@k: An Implementation of Lattice-Based Array Contraction in the Source-to-Source Translator ROSE},
  booktitle = {LCTES},
  year = {2007},
  publisher = {ACM}
}



%%%%%%%%%%%%% ASIP %%%%%%%%%%%%%%%%

@inproceedings{DAC09,
 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
 title = {Way Stealing: cache-assisted automatic instruction set extensions},
 booktitle = {DAC '09: Proceedings of the 46th Annual Design Automation Conference},
 year = {2009},
 isbn = {978-1-60558-497-3},
 pages = {31--36},
 location = {San Francisco, California},
 doi = {http://doi.acm.org/10.1145/1629911.1629923},
 publisher = {ACM},
 address = {New York, NY, USA},
 }

@inproceedings{CODES08,
 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
 title = {Speculative DMA for architecturally visible storage in instruction set extensions},
 booktitle = {CODES/ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis},
 year = {2008},
 isbn = {978-1-60558-470-6},
 pages = {243--248},
 location = {Atlanta, GA, USA},
 doi = {http://doi.acm.org/10.1145/1450135.1450191},
 publisher = {ACM},
 address = {New York, NY, USA},
 }
 
@article{TVLSI06,
        author = {Cong, Jason and Han, Guoling and Zhang, Zhiru},
 title = {Architecture and compiler optimizations for data bandwidth improvement in configurable processors},
 journal = {IEEE Trans. Very Large Scale Integr. Syst.},
 volume = {14},
 number = {9},
 year = {2006},
 issn = {1063-8210},
 pages = {986--997},
 doi = {http://dx.doi.org/10.1109/TVLSI.2006.884050},
 publisher = {IEEE Educational Activities Department},
 address = {Piscataway, NJ, USA},
}


@Book{NIOS2,
  title =        {{Nios II Processor Reference Handbook}},
  publisher =    {Altera},
  year =         {2009},
}


@inproceedings{ARC08,
 author = {Galuzzi, Carlo and Bertels, Koen},
 title = {The Instruction-Set Extension Problem: A Survey},
 booktitle = {ARC '08: Proceedings of the 4th international workshop on Reconfigurable Computing},
 year = {2008},
 isbn = {978-3-540-78609-2},
 pages = {209--220},
 location = {London, UK},
 doi = {http://dx.doi.org/10.1007/978-3-540-78610-8_21},
 publisher = {Springer-Verlag},
 address = {Berlin, Heidelberg},
 }

@inproceedings{CODES99,
 author = {Charot, Fran\c{c}ois and Mess\'{e}, Vincent},
 title = {{A flexible code generation framework for the design of application specific programmable processors}},
 booktitle = {CODES '99: Proceedings of the seventh international workshop on Hardware/software codesign},
 year = {1999},
 pages = {27--31},
 location = {Rome, Italy},
 publisher = {ACM},
 address = {New York, NY, USA},
 }

@inproceedings{ASAP05,
 author = {L'Hours, Ludovic},
 title = {{Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications}},
 booktitle = {ASAP '05: Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors},
 year = {2005},
 pages = {127--133},
 publisher = {IEEE Computer Society},
 address = {Washington, DC, USA},
}
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