source: anr/anr.bib @ 230

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trois references de plus
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[15]1%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
2%%%%% LIP6
3% HPC
4@InProceedings{hpc06a,
5  author    = {{M.B. Gokhale and al.}},
[56]6  title     = {{Promises and Pitfalls of Reconfigurable Supercomputing}},
[15]7  booktitle = {Systems and Algorithms, CSREA Press},
8  pages     = {11-20},
9  year      = {2006},
10}
11@MISC{hpc06b,
12  author =       {{D. Buell}},
13  title  =   {{Programming Reconfigurable Computers}},
14  booktitle = {Summer Institute},
15  howpublished = {http://gladiator.ncsa.uiuc.edu/PDFs/rssi06/presentations/00\_Duncan\_Buell.pdf},
16  year =         {2006},
17}
18@InProceedings{hpc07a,
19  author =       {{T. Van Court and al.}},
20  title  =   {{ Achieving High Performance with FPGA-Based Computing}},
21  booktitle = {Computer, vol. 40, no. 3},
22  pages     = {50-57},
23  month     = {mars},
24  year =         {2007},
25}
[56]26@misc{hpc08,
27  title        = {Mitrionics},
28  howpublished = {http://www.mitrionics.com/},
29  year         = {2009},
30}
31@misc{hpc09,
32  title        = {Gidel},
33  howpublished = {http://www.gidel.com/},
34  year         = {2009},
35}
36@misc{hpc10,
37  title        = {Convey Computer},
38  howpublished = {http://www.conveycomputers.com/},
39  year         = {2009},
40}
41@InProceedings{hpc11,
42  author =      {E. El-Araby, I. Gonzalez and T. El-Ghazawi},
43  title   = {Virtual Architecture and Design Automation for Partial Reconfiguration },
44  booktitle = {HPRCTA},
45  year =         {2008},
46}
47@InProceedings{hpc12,
48  author =       {{P. Lysaght and J. Dunlop}},
49  title   = {Dynamic Reconfiguration of Field Programmable Gate Arrays},
50  booktitle = {Field Programmable Logic and Applications, Oxford, England},
51  month     = {Sept},
52  year =         {1993},
53}
[15]54
[56]55
[15]56% System design
57@misc{soclib,
58  title        = {Soclib},
59  howpublished = {http://www.soclib.fr/},
60  year         = {2009},
61}
62
63@misc{system-generateur-for-dsp,
64  title        = {{System Generator for DSP}},
65  howpublished = {http://www.xilinx.com/tools/sysgen.htm},
66  year         = {2009},
67}
68
69@misc{spoc-builder,
70  title        = {{sopc builder support}},
71  howpublished = {http://www.altera.com/support/software/system/sopc/sof-sopc\_builder.html},
72  year         = {2009},
73}
74
[135]75@InProceedings{cosy,
76    author = { J.Y Brunel, al },
77    title  = { COSY: a methodology for system design based on reusable hardware \& software IP's},
78    booktitle = { Technologies for the Information Society },
79    publisher = { IOS Press },
80    year      = {1998},
81    pages     = {709-716},
82}
83
[15]84@InProceedings{disydent05,
[93]85  author =       {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, Franï¿œois Donnet and Pascal Gomez}},
[15]86  title =        {{Platform-based design from parallel C specifications}},
87  booktitle = {IEEE Transaction on CAD of Integrated Circuits and Systems},
88  pages     = {1811--1826},
89  month     = {December},
90  year =         {2005},
91}
[135]92@inproceedings{dspin08,
93 author = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain},
94 title = {Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture},
95 booktitle = {NOCS '08: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip},
96 year = {2008},
97 isbn = {978-0-7695-3098-7},
98 pages = {139--148},
99 publisher = {IEEE Computer Society},
100 address = {Washington, DC, USA},
101 }
[15]102
[135]103
[15]104% HLS
105% http://mesl.ucsd.edu/spark/index.shtml
[184]106@INBOOK{spark04,
[15]107  author     = {S. Gupta and al.},
108  title      = {SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits},
109  publisher  = {Springer},
110  year       = {2004},
111}
112
113
114@INBOOK{ugh08,
115  author    = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot},
116  title     = {User Guided High Level Synthesis},
117  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
118  publisher = {Springer},
119  chapter   = {10},
120  year      = {2008},
121}
122
123@misc{pico,
124  title        = {{PICO}},
125  howpublished = {http://www.synfora.com/},
126  year         = {2009},
127}
128
129@misc{catapult-c,
130  title        = {{CATAPULT-C Mentor HLS tool}},
131  howpublished = {http://www.mentor.com/products/esl/high\_level\_synthesis/},
132  year         = {2009},
133}
134
135@misc{cynthetizer,
136  title        = {{Forte's CYNTHESIZER}},
137  howpublished = {http://www.forteds.com/},
138  year         = {2009},
139}
140
[77]141
142
[15]143%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
[77]144%%% UBS
145
[180]146@INBOOK{IEEEDT,
147author = {Philippe Coussy and Andres Takach},
148title = {Special Issue on High-Level Synthesis},
149journal ={IEEE Design and Test of Computers},
150volume = {25},issn = {0740-7475},
151year = {2008},
152pages = {393},doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2008.147},
153publisher = {IEEE Computer Society},
154address = {Los Alamitos, CA, USA},}
[77]155
[180]156
157@INBOOK{HLSBOOK,
158  author    = {P. Coussy and A. Morawiec},
159  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
160  publisher = {Springer},
161  year      = {2008},
162}
163
164@INBOOK{CATRENE,
165  author    = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
166  booktitle = {European Roadmap for EDA},
167  publisher = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
168  year      = {2009},
169}
170
[77]171@INBOOK{gaut08,
172  author    = {P. Coussy and al.},
173  title     = {GAUT: A High-Level Synthesis Tool for DSP applications},
174  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
175  publisher = {Springer},
176  year      = {2008},
177}
178
179@article{DBLP:journals/dt/CoussyT09,
180  author    = {Philippe Coussy and
181               Andres Takach},
182  title     = {Guest Editors' Introduction: Raising the Abstraction Level
183               of Hardware Design},
184  journal   = {IEEE Design {\&} Test of Computers},
185  volume    = {26},
186  number    = {4},
187  year      = {2009},
188  pages     = {4-6},
189  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.80},
190  bibsource = {DBLP, http://dblp.uni-trier.de}
191}
192
193
194@article{DBLP:journals/dt/CoussyGMT09,
195  author    = {Philippe Coussy and
196               Daniel D. Gajski and
197               Michael Meredith and
198               Andres Takach},
199  title     = {An Introduction to High-Level Synthesis},
200  journal   = {IEEE Design {\&} Test of Computers},
201  volume    = {26},
202  number    = {4},
203  year      = {2009},
204  pages     = {8-17},
205  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.69},
206  bibsource = {DBLP, http://dblp.uni-trier.de}
207}
208
209
210@article{DBLP:journals/vlsisp/ThabetCHM09,
211  author    = {Farhat Thabet and
212               Philippe Coussy and
213               Dominique Heller and
214               Eric Martin},
215  title     = {Exploration and Rapid Prototyping of DSP Applications using
216               SystemC Behavioral Simulation and High-level Synthesis},
217  journal   = {Signal Processing Systems},
218  volume    = {56},
219  number    = {2-3},
220  year      = {2009},
221  pages     = {167-186},
222  ee        = {http://dx.doi.org/10.1007/s11265-008-0235-1},
223  bibsource = {DBLP, http://dblp.uni-trier.de}
224}
225
226
227
228@inproceedings{CHAVET:2007:HAL-00153994:1,
229        title = { {A} {M}ethodology for {E}fficient {S}pace-{T}ime {A}dapter {D}esign {S}pace {E}xploration: {A} {C}ase {S}tudy of an {U}ltra {W}ide {B}and {I}nterleaver},
230        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
231        abstract = {{T}his paper presents a solution to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {T}he {RCG} properties enable an efficient architecture space exploration in order to synthesize a {STAR} component. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
232        language = {{A}nglais},
233        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
234        booktitle = {{P}roceedings of the {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) {T}he {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) },
235        publisher = {{L}ibrary of {C}ongress },
236        pages = {2946 },
237        address = {{N}ew {O}rleans {\'E}tats-{U}nis d'{A}m{\'e}rique },
238        editor = {{IEEE} },
239        note = {{ISBN}:1-4244-0921-7 },
240        audience = {internationale },
241    day = {28},
242    month = {05},
243    year = {2007},
244    URL = {http://hal.archives-ouvertes.fr/hal-00153994/en/},
245    URL = {http://hal.archives-ouvertes.fr/hal-00153994/PDF/ISCAS_Chavet1992.pdf},
246}
247
248
249@inproceedings{DBLP:conf/iccad/ChavetACCJUM07,
250  author    = {Cyrille Chavet and
251               Caaliph Andriamisaina and
252               Philippe Coussy and
253               Emmanuel Casseau and
254               Emmanuel Juin and
255               Pascal Urard and
256               Eric Martin},
257  title     = {A design flow dedicated to multi-mode architectures for
258               DSP applications},
259  booktitle = {ICCAD},
260  year      = {2007},
261  pages     = {604-611},
262  ee        = {http://doi.acm.org/10.1145/1326073.1326199},
263  crossref  = {DBLP:conf/iccad/2007},
264  bibsource = {DBLP, http://dblp.uni-trier.de}
265}
266
267
268@inproceedings{DBLP:conf/glvlsi/ChavetCUM07,
269  author    = {Cyrille Chavet and
270               Philippe Coussy and
271               Pascal Urard and
272               Eric Martin},
273  title     = {A design methodology for space-time adapter},
274  booktitle = {ACM Great Lakes Symposium on VLSI},
275  year      = {2007},
276  pages     = {347-352},
277  ee        = {http://doi.acm.org/10.1145/1228784.1228868},
278  crossref  = {DBLP:conf/glvlsi/2007},
279  bibsource = {DBLP, http://dblp.uni-trier.de}
280}
281
282
283@inproceedings{CHAVET:2007:HAL-00154025:1,
284        title = { {A}pplication of a design space exploration tool to enhance interleaver generation},
285        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
286        abstract = {{T}his paper presents a methodology to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {D}esign space exploration is then performed through associated tools, to synthesize a {STAR} component under time-to-market constraints. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
287        language = {{A}nglais},
288        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
289        booktitle = {{P}roceedings of the {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) },
290        publisher = {{E}urasip },
291        pages = {??? },
292        address = {{P}oznan {P}ologne },
293        audience = {internationale },
294    day = {03},
295    month = {09},
296    year = {2007},
297    URL = {http://hal.archives-ouvertes.fr/hal-00154025/en/},
298    URL = {http://hal.archives-ouvertes.fr/hal-00154025/PDF/EUSIPCO_chavet.pdf},
299}
300
301
302@inproceedings{ANDRIAMISAINA:2007:HAL-00153086:1,
303        title = { {S}ynthesis of {M}ultimode digital signal processing systems},
304        author = {{A}ndriamisaina, {C}aaliph and {C}asseau, {E}mmanuel and {C}oussy, {P}hilippe},
305        abstract = {{I}n this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. {T}he inputs of the design flow are the data flow graphs ({DFG}s), representing the different modes (i.e. the different applications to be implemented), with their respective throughput constraints. {W}hile traditional approaches merge {DFG}s together before the synthesis process, we propose to use ad-hoc scheduling and binding steps during the synthesis of each {DFG}. {T}he scheduling, which assigns operations to specific time steps, maximizes the similarity between the control steps and thus decreases the controller complexity. {T}he binding process, which assigns operations to specific functional units and data to specific storage elements, maximizes the similarity between datapaths and thus minimizes steering logic and register overhead. {F}irst results show the interest of the proposed synthesis flow.},
306        language = {{A}nglais},
307        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {R}2{D}2 - {INRIA} - {IRISA} - {CNRS} : {UMR}6074 - {INRIA} - {I}nstitut {N}ational des {S}ciences {A}ppliqu{\'e}es de {R}ennes - {E}cole {N}ationale {S}up{\'e}rieure des {S}ciences {A}ppliqu{\'e}es et de {T}echnologie - {U}niversit{\'e} de {R}ennes 1 },
308        booktitle = {{P}roceeding of {A}daptive {H}ardware and {S}ystems {NASA}/{ESA} {C}onference on {A}daptive {H}ardware and {S}ystems },
309        publisher = {{AHS} },
310        pages = {7 },
311        address = {{E}dinburgh {R}oyaume-{U}ni },
312        audience = {internationale },
313    year = {2007},
314    URL = {http://hal.archives-ouvertes.fr/hal-00153086/en/},
315    URL = {http://hal.archives-ouvertes.fr/hal-00153086/PDF/PID411805.pdf},
316}
317
318
319@inproceedings{COUSSY:2005:HAL-00077301:1,
320        title = { {A} {M}ore {E}fficient and {F}lexible {DSP} {D}esign {F}low from {MATLAB}-{SIMULINK}},
321        author = {{C}oussy, {P}hilippe and {C}orre, {G}wenol{\'e} and {B}omel, {P}ierre and {S}enn, {E}ric and {M}artin, {E}ric},
322        abstract = {{T}he design of complex {D}igital {S}ignal {P}rocessing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. {U}nfortunately, the traditional {M}atlab/{S}imulink design flows gather not very flexible hardware blocs. {I}n this paper, we present a methodology and a tool that permit the {H}igh-{L}evel {S}ynthesis of {DSP} applications, under both {I}/{O} timing and memory constraints. {B}ased on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. {T}he efficiency of our approach is demonstrated on the case study of a {FFT} algorithm.},
323        keywords = {{DSP} application, synthesis under memory and communication constraints},
324        language = {{A}nglais},
325        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud },
326        booktitle = {{IEEE} {I}nternational {C}onference on {A}coustic, {S}peech and {S}ignal {P}rocessing },
327        publisher = {{IEEE} },
328        pages = {{V}ol. {V} p. 61-64 },
329        editor = {{IEEEE} },
330    year = {2005},
331    URL = {http://hal.archives-ouvertes.fr/hal-00077301/en/},
332    URL = {http://hal.archives-ouvertes.fr/hal-00077301/PDF/coussy_final.pdf},
333}
334
335
336
337%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
[15]338%%%%% IRISA
339@InProceedings{KluterCodes08,
340  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
341  title =        {{Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions}},
342  booktitle = {ISSS/CODES},
343  year =         {2008},
344}
345
346@InProceedings{KluterDAC09,
347  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
348  title =        {{Way Stealing : Cache-assisted Automatic Instruction Set Extensions}},
349  booktitle = {Design Automation Conference (DAC)},
350  year =         {2009},
351}
352
353@InProceedings{YuCodes04,
354  author =       {{Pan Yu and Tulika Mitra}},
355  title =        {{Scalable Custom Instructions Identification for Instruction Set Extensible Processors}},
356  booktitle = {ISSS/CODES},
357  year =         {2004},
358}
359
360@InProceedings{Dinh08,
361  author =       {{Quang Dinh and Deming Chen and Martin D.~F.~Wong}},
362  title =        {{Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing}},
363  booktitle = {ACM Internatibnal Conference Field Programmable Gate Arrays (FPGA)},
364  year =         {2008},
365}
366
367@Misc{NIOS2UG,
368  title =        {{Nios II Custom Instruction User Guide, Altera Corp.}},
369  year =         {2008},
370}
371
372%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
373%%% CITI
374@book{Polis,
375  author = {Balarin, Felice},
376  publisher = {Kluwer Academic Publishers},
377  title = {Hardware-software co-design of embedded systems : the POLIS
378        approach},
379  year = {1997}
380}
381
382@INPROCEEDINGS{Coware,
383  author = {Ivo Bolsens and Hugo J. De Man and Bill Lin and Karl Van
384                Rompaey and Steven Vercauteren and Diederik Verkest},
385  title = {Hardware/Software Co-Design of Digital Telecommunication Systems},
386  booktitle = {Proceedings of the IEEE},
387  year = {1997},
388  pages = {391--418}
389}
390
391@article{Jantsch,
392  author = {Mattias O'Nil and Axel Jantsch},
393  title = {Device Driver and DMA Controller Synthesis from HW/SW
394                        Communication protocol specifications},
395  journal = {Design Automation for Embedded Systems},
396  year = {2001},
397  volume = {6},
398  pages = {177-205}
399}
400
401@InProceedings{Park01,
402  author =   {Joonseok Park and Pedro C.~Diniz},
403  title =    {Synthesis of Pipelined Memory Access Controllers for Streamed
404                Data Applications on {FPGA}-Based Computing Engines},
405  booktitle =    {International Symposium on System Synthesis (ISSS)},
406  pages = {221-226},
407  year =     {2001},
408}
409
410@article{FR-vlsi,
411  author = {Antoine Fraboulet and Tanguy Risset},
412  title = {Master Interface for On-Chip Hardware Accelerator Burst Communications},
413  journal = {Journal of VLSI Signal Processing},
414  publisher = {Springer Science},
415  year = {2007},
416  volume = {59},
417  pages = {73-85}
418}
419
420@InProceedings{jerraya,
421  author =   {Sungjoo Yoo and Jerraya Ahmed},
422  title =    {Introduction to Hardware Abstraction Layers for SoC},
423  OPTcrossref =  {},
424  OPTkey =   {},
425  booktitle = {Design, Automation and Test in Europe Conference and Exhibition},
426  pages =    {336 -- 337},
427  year =     2003,
428  OPTeditor =    {},
429  OPTvolume =    {},
430  OPTnumber =    {},
431  OPTseries =    {},
432  OPTaddress =   {},
433  OPTmonth =     {},
434  OPTorganization = {},
435  OPTpublisher = {},
436  OPTnote =      {},
437  OPTannote =    {}
438}
439
440@INPROCEEDINGS{FAUST,
441  author = {D. Lattard and  E. Beigne and  C. Bernard and  C. Bour and  F.
442        Clermidy and  Y. Durand and  J. Durupt and  D. Varreau and  P. Vivet and
443        P. Penard and  A. Bouttier and  F. Berens}, 
444  title = "A Telecom Baseband Circuit-Based on an Asynchronous Network-on-Chip", 
445  pages = {},
446  BOOKTITLE="ISSCC\'2007", 
447  year = {2007},
448  publisher = {IEEE Computer Society},
449  address = {San Francisco, USA},
450};
451
452@inproceedings{JerrayaPetrot,
453 author = {Ahmed A. Jerraya and Aimen Bouchhima and Fr\'{e}d\'{e}ric P\'{e}trot},
454 title = {Programming models and HW-SW interfaces abstraction for multi-processor SoC},
455 booktitle = {DAC '06: Proceedings of the 43rd annual conference on Design automation},
456 year = {2006},
457 isbn = {1-59593-381-6},
458 pages = {280--285},
459 location = {San Francisco, CA, USA},
460 publisher = {ACM},
461 address = {New York, NY, USA},
462}
463
464@inproceedings{mwmr,
465 author = {E. Faure and A. Greiner and D. Genius},
466 title = {A generic hardware/software communication mechanism for
467          Multi-Processor System on Chip, Targeting Telecommunication Applications},
468 booktitle = {ReCoSoC'06},
469 year = {2006},
470 pages = {237--242},
471 address = {Montpellier, France}
472 }
473
474@inproceedings{Alberto,
475  author    = {Roberto Passerone and
476               James A. Rowson and
477               Alberto L. Sangiovanni-Vincentelli},
478  title     = {Automatic Synthesis of Interfaces Between Incompatible Protocols},
479  booktitle = {DAC},
480  year      = {1998},
481  pages     = {8-13}
482}
483
484@article{Avnit,
485  author    = {Karin Avnit and
486               Vijay D'Silva and
487               Arcot Sowmya and
488               S. Ramesh and
489               Sri Parameswaran},
490  title     = {Provably correct on-chip communication: A formal approach
491               to automatic protocol converter synthesis},
492  journal   = {ACM Trans. Design Autom. Electr. Syst.},
493  volume    = {14},
494  number    = {2},
495  year      = {2009}
496}
497
498@inproceedings{smith,
499  author    = {James Smith and
500               Giovanni De Micheli},
501  title     = {Automated Composition of Hardware Components},
502  booktitle = {DAC},
503  year      = {1998},
504  pages     = {14-19}
505}
506
507@inproceedings{Narayan,
508  author    = {Sanjiv Narayan and
509               Daniel Gajski},
510  title     = {Interfacing Incompatible Protocols Using Interface Process
511               Generation},
512  booktitle = {DAC},
513  year      = {1995},
514  pages     = {468-473}
515}
516
517@TECHREPORT{Ptolemy,
518  AUTHOR       = { E.A. Lee et al.},
519  INSTITUTION  = {University of California, Berkeley},
520  NUMBER       = {UCB/ERL No. M99/37},
521  TITLE        = {Overview of the Ptolemy Project},
522  YEAR         = {1999},
523  MONTH        = {july}
524}
525
[61]526@article{syntol,
527    author={Paul Feautrier},
528    title={Scalable and Structured Scheduling},
529    journal={Int. J. of Parallel Programming},
530    year=2006,
531    month=May, number=5, volume=34,
532    pages="459--487"
533}
[87]534
535@InProceedings{bee,
536  author={Christophe Alias and Fabrice Baray and Alain Darte},
537  title={Bee+Cl@k: An Implementation of Lattice-Based Array Contraction in the Source-to-Source Translator ROSE},
538  booktitle = {LCTES},
539  year = {2007},
540  publisher = {ACM}
541}
[93]542
543%%%%%%%%%%%%% ASIP %%%%%%%%%%%%%%%%
544
545@inproceedings{DAC09,
546 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
547 title = {Way Stealing: cache-assisted automatic instruction set extensions},
548 booktitle = {DAC '09: Proceedings of the 46th Annual Design Automation Conference},
549 year = {2009},
550 isbn = {978-1-60558-497-3},
551 pages = {31--36},
552 location = {San Francisco, California},
553 doi = {http://doi.acm.org/10.1145/1629911.1629923},
554 publisher = {ACM},
555 address = {New York, NY, USA},
556 }
557
558@inproceedings{CODES08,
559 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
560 title = {Speculative DMA for architecturally visible storage in instruction set extensions},
561 booktitle = {CODES/ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis},
562 year = {2008},
563 isbn = {978-1-60558-470-6},
564 pages = {243--248},
565 location = {Atlanta, GA, USA},
566 doi = {http://doi.acm.org/10.1145/1450135.1450191},
567 publisher = {ACM},
568 address = {New York, NY, USA},
569 }
570 
571@article{TVLSI06,
572        author = {Cong, Jason and Han, Guoling and Zhang, Zhiru},
573 title = {Architecture and compiler optimizations for data bandwidth improvement in configurable processors},
574 journal = {IEEE Trans. Very Large Scale Integr. Syst.},
575 volume = {14},
576 number = {9},
577 year = {2006},
578 issn = {1063-8210},
579 pages = {986--997},
580 doi = {http://dx.doi.org/10.1109/TVLSI.2006.884050},
581 publisher = {IEEE Educational Activities Department},
582 address = {Piscataway, NJ, USA},
583}
584
585
586@Book{NIOS2,
587  title =        {{Nios II Processor Reference Handbook}},
588  publisher =    {Altera},
589  year =         {2009},
590}
591
592
593@inproceedings{ARC08,
594 author = {Galuzzi, Carlo and Bertels, Koen},
595 title = {The Instruction-Set Extension Problem: A Survey},
596 booktitle = {ARC '08: Proceedings of the 4th international workshop on Reconfigurable Computing},
597 year = {2008},
598 isbn = {978-3-540-78609-2},
599 pages = {209--220},
600 location = {London, UK},
601 doi = {http://dx.doi.org/10.1007/978-3-540-78610-8_21},
602 publisher = {Springer-Verlag},
603 address = {Berlin, Heidelberg},
604 }
605
606@inproceedings{CODES99,
607 author = {Charot, Fran\c{c}ois and Mess\'{e}, Vincent},
608 title = {{A flexible code generation framework for the design of application specific programmable processors}},
609 booktitle = {CODES '99: Proceedings of the seventh international workshop on Hardware/software codesign},
610 year = {1999},
611 pages = {27--31},
612 location = {Rome, Italy},
613 publisher = {ACM},
614 address = {New York, NY, USA},
615 }
616
617@inproceedings{ASAP05,
618 author = {L'Hours, Ludovic},
619 title = {{Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications}},
620 booktitle = {ASAP '05: Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors},
621 year = {2005},
622 pages = {127--133},
623 publisher = {IEEE Computer Society},
624 address = {Washington, DC, USA},
625}
[120]626
627@inproceedings{roma,
628 author = {Menard, Daniel and Casseau, Emmanuel and Khan, Shafqat and Sentieys, Olivier and Chevobbe, St\'{e}phane and Guyetant, St\'{e}phane and David, Raphael},
629 title = {Reconfigurable Operator Based Multimedia Embedded Processor},
630 booktitle = {ARC '09: Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications},
631 year = {2009},
632 pages = {39--49},
633 location = {Karlsruhe, Germany},
634 publisher = {Springer-Verlag},
635 address = {Berlin, Heidelberg},
636 }
637
[123]638%%%%%%%%%%%%% AUTRES %%%%%%%%%%%%%%%%
639
640@inproceedings{thales-viola,
641 author = {Viola, Jones},
642 title = {{Rapid Object Detection using a Boosted Cascade of Simple Feature}},
643 booktitle = {Proceedings of Conference on Computer Vision and Pattern recognition},
644 year = {2001},
645}
[174]646@INPROCEEDINGS{FP:96
647        ,AUTHOR = "Paul Feautrier"
648        ,TITLE = "Automatic Parallelization in the Polytope Model"
649        ,BOOKTITLE = "The Data-Parallel Programming Model"
650        ,YEAR = 1996   
651        ,EDITOR = "Guy-Ren\'e Perrin and Alain Darte"
652        ,PAGES = "79--103"
653        ,VOLUME = "LNCS 1132"
654        ,PUBLISHER = "Springer"
655}
656
657@book{DRV:2000,
658    author={Alain Darte and Yves Robert and Fr\'ed\'eric Vivien},
659    title={Scheduling and automatic Parallelization},
660    publisher={Birkh\"auser}, year=2000
661}
[200]662
663@Article{Feau:92aa,
664  author =       "Paul Feautrier",
665  title =        "Some Efficient Solutions to the Affine Scheduling
666                 Problem, {I}, One Dimensional Time",
667  volume =       "21",
668  number =       "5",
669  month =        Oct,
670  pages =        "313--348",
671  journal =      "Int. J. of Parallel Programming",
672  year =         "1992"
673}
674
675@Article{Feau:92bb,
676  author =       "Paul Feautrier",
677  title =        "Some Efficient Solutions to the Affine Scheduling
678                 Problem, {II}, Multidimensional Time",
679  volume =       "21",
680  number =       "6",
681  journal =      "Int. J. of Parallel Programming",
682  month =        Dec,
683  pages =        "389--420",
684  year =         "1992"
685}
686
687@ARTICLE{Feau:96
688        ,AUTHOR = {Paul Feautrier}
689        ,TITLE = {Distribution Automatique des Donn\'es et des
690         calculs} 
691        ,JOURNAL = {T.S.I.}
692        ,YEAR = 1996, VOLUME = 15, NUMBER = 5, PAGES = {529--557}
693}
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