source: anr/anr.bib @ 292

Last change on this file since 292 was 290, checked in by coach, 14 years ago

Fixed miss spellings.
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1%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
2%%%%% LIP6
3% HPC
4@InProceedings{hpc06a,
5  author    = {{M.B. Gokhale and al.}},
6  title     = {{Promises and Pitfalls of Reconfigurable Supercomputing}},
7  booktitle = {Systems and Algorithms, CSREA Press},
8  pages     = {11-20},
9  year      = {2006},
10}
11@MISC{hpc06b,
12  author =       {{D. Buell}},
13  title  =   {{Programming Reconfigurable Computers}},
14  booktitle = {Summer Institute},
15  howpublished = {http://gladiator.ncsa.uiuc.edu/PDFs/rssi06/presentations/00\_Duncan\_Buell.pdf},
16  year =         {2006},
17}
18@InProceedings{hpc07a,
19  author =       {{T. Van Court and al.}},
20  title  =   {{ Achieving High Performance with FPGA-Based Computing}},
21  booktitle = {Computer, vol. 40, no. 3},
22  pages     = {50-57},
23  month     = {mars},
24  year =         {2007},
25}
26@misc{hpc08,
27  title        = {Mitrionics},
28  howpublished = {http://www.mitrionics.com/},
29  year         = {2009},
30}
31@misc{hpc09,
32  title        = {Gidel},
33  howpublished = {http://www.gidel.com/},
34  year         = {2009},
35}
36@misc{hpc10,
37  title        = {Convey Computer},
38  howpublished = {http://www.conveycomputers.com/},
39  year         = {2009},
40}
41@InProceedings{hpc11,
42  author =      {E. El-Araby, I. Gonzalez and T. El-Ghazawi},
43  title   = {Virtual Architecture and Design Automation for Partial Reconfiguration },
44  booktitle = {HPRCTA},
45  year =         {2008},
46}
47@InProceedings{hpc12,
48  author =       {{P. Lysaght and J. Dunlop}},
49  title   = {Dynamic Reconfiguration of Field Programmable Gate Arrays},
50  booktitle = {Field Programmable Logic and Applications, Oxford, England},
51  month     = {Sept},
52  year =         {1993},
53}
54
55
56% System design
57@misc{soclib,
58  title        = {Soclib},
59  howpublished = {http://www.soclib.fr/},
60  year         = {2009},
61}
62
63@misc{system-generateur-for-dsp,
64  title        = {{System Generator for DSP}},
65  howpublished = {http://www.xilinx.com/tools/sysgen.htm},
66  year         = {2009},
67}
68
69@misc{spoc-builder,
70  title        = {{sopc builder support}},
71  howpublished = {http://www.altera.com/support/software/system/sopc/sof-sopc\_builder.html},
72  year         = {2009},
73}
74
75@InProceedings{cosy,
76    author = { J.Y Brunel, al },
77    title  = { COSY: a methodology for system design based on reusable hardware \& software IP's},
78    booktitle = { Technologies for the Information Society },
79    publisher = { IOS Press },
80    year      = {1998},
81    pages     = {709-716},
82}
83
84@InProceedings{disydent05,
85  author =       {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, Fran\c{c}ois Donnet and Pascal Gomez}},
86  title =        {{Platform-based design from parallel C specifications}},
87  booktitle = {IEEE Transaction on CAD of Integrated Circuits and Systems},
88  pages     = {1811--1826},
89  month     = {December},
90  year =         {2005},
91}
92@inproceedings{dspin08,
93 author = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain},
94 title = {Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture},
95 booktitle = {NOCS '08: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip},
96 year = {2008},
97 isbn = {978-0-7695-3098-7},
98 pages = {139--148},
99 publisher = {IEEE Computer Society},
100 address = {Washington, DC, USA},
101 }
102
103
104% HLS
105% http://mesl.ucsd.edu/spark/index.shtml
106@INBOOK{spark04,
107  author     = {S. Gupta and al.},
108  title      = {SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits},
109  publisher  = {Springer},
110  year       = {2004},
111}
112
113
114@INBOOK{ugh08,
115  author    = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot},
116  title     = {User Guided High Level Synthesis},
117  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
118  publisher = {Springer},
119  chapter   = {10},
120  year      = {2008},
121}
122
123@misc{pico,
124  title        = {{PICO}},
125  howpublished = {http://www.synfora.com/},
126  year         = {2009},
127}
128
129@misc{catapult-c,
130  title        = {{CATAPULT-C Mentor HLS tool}},
131  howpublished = {http://www.mentor.com/products/esl/high\_level\_synthesis/},
132  year         = {2009},
133}
134
135@misc{cynthetizer,
136  title        = {{Forte's CYNTHESIZER}},
137  howpublished = {http://www.forteds.com/},
138  year         = {2009},
139}
140
141@inproceedings{IP-XACT-08,
142 author = {Kruijtzer, Wido and van der Wolf, Pieter and de Kock, Erwin and Stuyt, Jan and Ecker, Wolfgang and Mayer, Albrecht and Hustin, Serge and Amerijckx, Christophe and de Paoli, Serge and Vaumorin, Emmanuel},
143 title = {Industrial IP integration flows based on IP-XACT standards},
144 booktitle = {Proceedings of the conference on Design, automation and test in Europe},
145 series = {DATE '08},
146 year = {2008},
147 isbn = {978-3-9810801-3-1},
148 location = {Munich, Germany},
149 pages = {32--37},
150 numpages = {6},
151 url = {http://doi.acm.org/10.1145/1403375.1403386},
152 doi = {http://doi.acm.org/10.1145/1403375.1403386},
153 acmid = {1403386},
154 publisher = {ACM},
155 address = {New York, NY, USA},
156}
157
158
159%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
160%%% UBS
161
162@INBOOK{IEEEDT,
163author = {Philippe Coussy and Andres Takach},
164title = {Special Issue on High-Level Synthesis},
165journal ={IEEE Design and Test of Computers},
166volume = {25},issn = {0740-7475},
167year = {2008},
168pages = {393},doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2008.147},
169publisher = {IEEE Computer Society},
170address = {Los Alamitos, CA, USA},}
171
172
173@INBOOK{HLSBOOK,
174  author    = {P. Coussy and A. Morawiec},
175  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
176  publisher = {Springer},
177  year      = {2008},
178}
179
180@INBOOK{CATRENE,
181  author    = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
182  booktitle = {European Roadmap for EDA},
183  publisher = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
184  year      = {2009},
185}
186
187@INBOOK{gaut08,
188  author    = {P. Coussy and al.},
189  title     = {GAUT: A High-Level Synthesis Tool for DSP applications},
190  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
191  publisher = {Springer},
192  year      = {2008},
193}
194
195@article{DBLP:journals/dt/CoussyT09,
196  author    = {Philippe Coussy and
197               Andres Takach},
198  title     = {Guest Editors' Introduction: Raising the Abstraction Level
199               of Hardware Design},
200  journal   = {IEEE Design {\&} Test of Computers},
201  volume    = {26},
202  number    = {4},
203  year      = {2009},
204  pages     = {4-6},
205  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.80},
206  bibsource = {DBLP, http://dblp.uni-trier.de}
207}
208
209
210@article{DBLP:journals/dt/CoussyGMT09,
211  author    = {Philippe Coussy and
212               Daniel D. Gajski and
213               Michael Meredith and
214               Andres Takach},
215  title     = {An Introduction to High-Level Synthesis},
216  journal   = {IEEE Design {\&} Test of Computers},
217  volume    = {26},
218  number    = {4},
219  year      = {2009},
220  pages     = {8-17},
221  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.69},
222  bibsource = {DBLP, http://dblp.uni-trier.de}
223}
224
225
226@article{DBLP:journals/vlsisp/ThabetCHM09,
227  author    = {Farhat Thabet and
228               Philippe Coussy and
229               Dominique Heller and
230               Eric Martin},
231  title     = {Exploration and Rapid Prototyping of DSP Applications using
232               SystemC Behavioral Simulation and High-level Synthesis},
233  journal   = {Signal Processing Systems},
234  volume    = {56},
235  number    = {2-3},
236  year      = {2009},
237  pages     = {167-186},
238  ee        = {http://dx.doi.org/10.1007/s11265-008-0235-1},
239  bibsource = {DBLP, http://dblp.uni-trier.de}
240}
241
242
243
244@inproceedings{CHAVET:2007:HAL-00153994:1,
245        title = { {A} {M}ethodology for {E}fficient {S}pace-{T}ime {A}dapter {D}esign {S}pace {E}xploration: {A} {C}ase {S}tudy of an {U}ltra {W}ide {B}and {I}nterleaver},
246        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
247        abstract = {{T}his paper presents a solution to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {T}he {RCG} properties enable an efficient architecture space exploration in order to synthesize a {STAR} component. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
248        language = {{A}nglais},
249        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
250        booktitle = {{P}roceedings of the {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) {T}he {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) },
251        publisher = {{L}ibrary of {C}ongress },
252        pages = {2946 },
253        address = {{N}ew {O}rleans {\'E}tats-{U}nis d'{A}m{\'e}rique },
254        editor = {{IEEE} },
255        note = {{ISBN}:1-4244-0921-7 },
256        audience = {internationale },
257    day = {28},
258    month = {05},
259    year = {2007},
260    URL = {http://hal.archives-ouvertes.fr/hal-00153994/en/},
261    URL = {http://hal.archives-ouvertes.fr/hal-00153994/PDF/ISCAS_Chavet1992.pdf},
262}
263
264
265@inproceedings{DBLP:conf/iccad/ChavetACCJUM07,
266  author    = {Cyrille Chavet and
267               Caaliph Andriamisaina and
268               Philippe Coussy and
269               Emmanuel Casseau and
270               Emmanuel Juin and
271               Pascal Urard and
272               Eric Martin},
273  title     = {A design flow dedicated to multi-mode architectures for
274               DSP applications},
275  booktitle = {ICCAD},
276  year      = {2007},
277  pages     = {604-611},
278  ee        = {http://doi.acm.org/10.1145/1326073.1326199},
279  crossref  = {DBLP:conf/iccad/2007},
280  bibsource = {DBLP, http://dblp.uni-trier.de}
281}
282
283
284@inproceedings{DBLP:conf/glvlsi/ChavetCUM07,
285  author    = {Cyrille Chavet and
286               Philippe Coussy and
287               Pascal Urard and
288               Eric Martin},
289  title     = {A design methodology for space-time adapter},
290  booktitle = {ACM Great Lakes Symposium on VLSI},
291  year      = {2007},
292  pages     = {347-352},
293  ee        = {http://doi.acm.org/10.1145/1228784.1228868},
294  crossref  = {DBLP:conf/glvlsi/2007},
295  bibsource = {DBLP, http://dblp.uni-trier.de}
296}
297
298
299@inproceedings{CHAVET:2007:HAL-00154025:1,
300        title = { {A}pplication of a design space exploration tool to enhance interleaver generation},
301        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
302        abstract = {{T}his paper presents a methodology to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {D}esign space exploration is then performed through associated tools, to synthesize a {STAR} component under time-to-market constraints. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
303        language = {{A}nglais},
304        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
305        booktitle = {{P}roceedings of the {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) },
306        publisher = {{E}urasip },
307        pages = {??? },
308        address = {{P}oznan {P}ologne },
309        audience = {internationale },
310    day = {03},
311    month = {09},
312    year = {2007},
313    URL = {http://hal.archives-ouvertes.fr/hal-00154025/en/},
314    URL = {http://hal.archives-ouvertes.fr/hal-00154025/PDF/EUSIPCO_chavet.pdf},
315}
316
317
318@inproceedings{ANDRIAMISAINA:2007:HAL-00153086:1,
319        title = { {S}ynthesis of {M}ultimode digital signal processing systems},
320        author = {{A}ndriamisaina, {C}aaliph and {C}asseau, {E}mmanuel and {C}oussy, {P}hilippe},
321        abstract = {{I}n this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. {T}he inputs of the design flow are the data flow graphs ({DFG}s), representing the different modes (i.e. the different applications to be implemented), with their respective throughput constraints. {W}hile traditional approaches merge {DFG}s together before the synthesis process, we propose to use ad-hoc scheduling and binding steps during the synthesis of each {DFG}. {T}he scheduling, which assigns operations to specific time steps, maximizes the similarity between the control steps and thus decreases the controller complexity. {T}he binding process, which assigns operations to specific functional units and data to specific storage elements, maximizes the similarity between datapaths and thus minimizes steering logic and register overhead. {F}irst results show the interest of the proposed synthesis flow.},
322        language = {{A}nglais},
323        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {R}2{D}2 - {INRIA} - {IRISA} - {CNRS} : {UMR}6074 - {INRIA} - {I}nstitut {N}ational des {S}ciences {A}ppliqu{\'e}es de {R}ennes - {E}cole {N}ationale {S}up{\'e}rieure des {S}ciences {A}ppliqu{\'e}es et de {T}echnologie - {U}niversit{\'e} de {R}ennes 1 },
324        booktitle = {{P}roceeding of {A}daptive {H}ardware and {S}ystems {NASA}/{ESA} {C}onference on {A}daptive {H}ardware and {S}ystems },
325        publisher = {{AHS} },
326        pages = {7 },
327        address = {{E}dinburgh {R}oyaume-{U}ni },
328        audience = {internationale },
329    year = {2007},
330    URL = {http://hal.archives-ouvertes.fr/hal-00153086/en/},
331    URL = {http://hal.archives-ouvertes.fr/hal-00153086/PDF/PID411805.pdf},
332}
333
334
335@inproceedings{COUSSY:2005:HAL-00077301:1,
336        title = { {A} {M}ore {E}fficient and {F}lexible {DSP} {D}esign {F}low from {MATLAB}-{SIMULINK}},
337        author = {{C}oussy, {P}hilippe and {C}orre, {G}wenol{\'e} and {B}omel, {P}ierre and {S}enn, {E}ric and {M}artin, {E}ric},
338        abstract = {{T}he design of complex {D}igital {S}ignal {P}rocessing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. {U}nfortunately, the traditional {M}atlab/{S}imulink design flows gather not very flexible hardware blocs. {I}n this paper, we present a methodology and a tool that permit the {H}igh-{L}evel {S}ynthesis of {DSP} applications, under both {I}/{O} timing and memory constraints. {B}ased on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. {T}he efficiency of our approach is demonstrated on the case study of a {FFT} algorithm.},
339        keywords = {{DSP} application, synthesis under memory and communication constraints},
340        language = {{A}nglais},
341        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud },
342        booktitle = {{IEEE} {I}nternational {C}onference on {A}coustic, {S}peech and {S}ignal {P}rocessing },
343        publisher = {{IEEE} },
344        pages = {{V}ol. {V} p. 61-64 },
345        editor = {{IEEEE} },
346    year = {2005},
347    URL = {http://hal.archives-ouvertes.fr/hal-00077301/en/},
348    URL = {http://hal.archives-ouvertes.fr/hal-00077301/PDF/coussy_final.pdf},
349}
350
351
352
353%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
354%%%%% IRISA
355@InProceedings{KluterCodes08,
356  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
357  title =        {{Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions}},
358  booktitle = {ISSS/CODES},
359  year =         {2008},
360}
361
362@InProceedings{KluterDAC09,
363  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
364  title =        {{Way Stealing : Cache-assisted Automatic Instruction Set Extensions}},
365  booktitle = {Design Automation Conference (DAC)},
366  year =         {2009},
367}
368
369@InProceedings{YuCodes04,
370  author =       {{Pan Yu and Tulika Mitra}},
371  title =        {{Scalable Custom Instructions Identification for Instruction Set Extensible Processors}},
372  booktitle = {ISSS/CODES},
373  year =         {2004},
374}
375
376@InProceedings{Dinh08,
377  author =       {{Quang Dinh and Deming Chen and Martin D.~F.~Wong}},
378  title =        {{Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing}},
379  booktitle = {ACM Internatibnal Conference Field Programmable Gate Arrays (FPGA)},
380  year =         {2008},
381}
382
383@Misc{NIOS2UG,
384  title =        {{Nios II Custom Instruction User Guide, Altera Corp.}},
385  year =         {2008},
386}
387
388%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
389%%% CITI
390@book{Polis,
391  author = {Balarin, Felice},
392  publisher = {Kluwer Academic Publishers},
393  title = {Hardware-software co-design of embedded systems : the POLIS
394        approach},
395  year = {1997}
396}
397
398@INPROCEEDINGS{Coware,
399  author = {Ivo Bolsens and Hugo J. De Man and Bill Lin and Karl Van
400                Rompaey and Steven Vercauteren and Diederik Verkest},
401  title = {Hardware/Software Co-Design of Digital Telecommunication Systems},
402  booktitle = {Proceedings of the IEEE},
403  year = {1997},
404  pages = {391--418}
405}
406
407@article{Jantsch,
408  author = {Mattias O'Nil and Axel Jantsch},
409  title = {Device Driver and DMA Controller Synthesis from HW/SW
410                        Communication protocol specifications},
411  journal = {Design Automation for Embedded Systems},
412  year = {2001},
413  volume = {6},
414  pages = {177-205}
415}
416
417@InProceedings{Park01,
418  author =   {Joonseok Park and Pedro C.~Diniz},
419  title =    {Synthesis of Pipelined Memory Access Controllers for Streamed
420                Data Applications on {FPGA}-Based Computing Engines},
421  booktitle =    {International Symposium on System Synthesis (ISSS)},
422  pages = {221-226},
423  year =     {2001},
424}
425
426@article{FR-vlsi,
427  author = {Antoine Fraboulet and Tanguy Risset},
428  title = {Master Interface for On-Chip Hardware Accelerator Burst Communications},
429  journal = {Journal of VLSI Signal Processing},
430  publisher = {Springer Science},
431  year = {2007},
432  volume = {59},
433  pages = {73-85}
434}
435
436@InProceedings{jerraya,
437  author =   {Sungjoo Yoo and Jerraya Ahmed},
438  title =    {Introduction to Hardware Abstraction Layers for SoC},
439  OPTcrossref =  {},
440  OPTkey =   {},
441  booktitle = {Design, Automation and Test in Europe Conference and Exhibition},
442  pages =    {336 -- 337},
443  year =     2003,
444  OPTeditor =    {},
445  OPTvolume =    {},
446  OPTnumber =    {},
447  OPTseries =    {},
448  OPTaddress =   {},
449  OPTmonth =     {},
450  OPTorganization = {},
451  OPTpublisher = {},
452  OPTnote =      {},
453  OPTannote =    {}
454}
455
456@INPROCEEDINGS{FAUST,
457  author = {D. Lattard and  E. Beigne and  C. Bernard and  C. Bour and  F.
458        Clermidy and  Y. Durand and  J. Durupt and  D. Varreau and  P. Vivet and
459        P. Penard and  A. Bouttier and  F. Berens}, 
460  title = "A Telecom Baseband Circuit-Based on an Asynchronous Network-on-Chip", 
461  pages = {},
462  BOOKTITLE="ISSCC\'2007", 
463  year = {2007},
464  publisher = {IEEE Computer Society},
465  address = {San Francisco, USA},
466};
467
468@inproceedings{JerrayaPetrot,
469 author = {Ahmed A. Jerraya and Aimen Bouchhima and Fr\'{e}d\'{e}ric P\'{e}trot},
470 title = {Programming models and HW-SW interfaces abstraction for multi-processor SoC},
471 booktitle = {DAC '06: Proceedings of the 43rd annual conference on Design automation},
472 year = {2006},
473 isbn = {1-59593-381-6},
474 pages = {280--285},
475 location = {San Francisco, CA, USA},
476 publisher = {ACM},
477 address = {New York, NY, USA},
478}
479
480@inproceedings{mwmr,
481 author = {E. Faure and A. Greiner and D. Genius},
482 title = {A generic hardware/software communication mechanism for
483          Multi-Processor System on Chip, Targeting Telecommunication Applications},
484 booktitle = {ReCoSoC'06},
485 year = {2006},
486 pages = {237--242},
487 address = {Montpellier, France}
488 }
489
490@inproceedings{Alberto,
491  author    = {Roberto Passerone and
492               James A. Rowson and
493               Alberto L. Sangiovanni-Vincentelli},
494  title     = {Automatic Synthesis of Interfaces Between Incompatible Protocols},
495  booktitle = {DAC},
496  year      = {1998},
497  pages     = {8-13}
498}
499
500@article{Avnit,
501  author    = {Karin Avnit and
502               Vijay D'Silva and
503               Arcot Sowmya and
504               S. Ramesh and
505               Sri Parameswaran},
506  title     = {Provably correct on-chip communication: A formal approach
507               to automatic protocol converter synthesis},
508  journal   = {ACM Trans. Design Autom. Electr. Syst.},
509  volume    = {14},
510  number    = {2},
511  year      = {2009}
512}
513
514@inproceedings{smith,
515  author    = {James Smith and
516               Giovanni De Micheli},
517  title     = {Automated Composition of Hardware Components},
518  booktitle = {DAC},
519  year      = {1998},
520  pages     = {14-19}
521}
522
523@inproceedings{Narayan,
524  author    = {Sanjiv Narayan and
525               Daniel Gajski},
526  title     = {Interfacing Incompatible Protocols Using Interface Process
527               Generation},
528  booktitle = {DAC},
529  year      = {1995},
530  pages     = {468-473}
531}
532
533@TECHREPORT{Ptolemy,
534  AUTHOR       = { E.A. Lee et al.},
535  INSTITUTION  = {University of California, Berkeley},
536  NUMBER       = {UCB/ERL No. M99/37},
537  TITLE        = {Overview of the Ptolemy Project},
538  YEAR         = {1999},
539  MONTH        = {july}
540}
541
542@article{syntol,
543    author={Paul Feautrier},
544    title={Scalable and Structured Scheduling},
545    journal={Int. J. of Parallel Programming},
546    year=2006,
547    month=May, number=5, volume=34,
548    pages="459--487"
549}
550
551@InProceedings{bee,
552  author={Christophe Alias and Fabrice Baray and Alain Darte},
553  title={Bee+Cl@k: An Implementation of Lattice-Based Array Contraction in the Source-to-Source Translator ROSE},
554  booktitle = {LCTES},
555  year = {2007},
556  publisher = {ACM}
557}
558
559%%%%%%%%%%%%% ASIP %%%%%%%%%%%%%%%%
560
561@inproceedings{DAC09,
562 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
563 title = {Way Stealing: cache-assisted automatic instruction set extensions},
564 booktitle = {DAC '09: Proceedings of the 46th Annual Design Automation Conference},
565 year = {2009},
566 isbn = {978-1-60558-497-3},
567 pages = {31--36},
568 location = {San Francisco, California},
569 doi = {http://doi.acm.org/10.1145/1629911.1629923},
570 publisher = {ACM},
571 address = {New York, NY, USA},
572 }
573
574@inproceedings{CODES08,
575 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
576 title = {Speculative DMA for architecturally visible storage in instruction set extensions},
577 booktitle = {CODES/ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis},
578 year = {2008},
579 isbn = {978-1-60558-470-6},
580 pages = {243--248},
581 location = {Atlanta, GA, USA},
582 doi = {http://doi.acm.org/10.1145/1450135.1450191},
583 publisher = {ACM},
584 address = {New York, NY, USA},
585 }
586 
587@article{TVLSI06,
588        author = {Cong, Jason and Han, Guoling and Zhang, Zhiru},
589 title = {Architecture and compiler optimizations for data bandwidth improvement in configurable processors},
590 journal = {IEEE Trans. Very Large Scale Integr. Syst.},
591 volume = {14},
592 number = {9},
593 year = {2006},
594 issn = {1063-8210},
595 pages = {986--997},
596 doi = {http://dx.doi.org/10.1109/TVLSI.2006.884050},
597 publisher = {IEEE Educational Activities Department},
598 address = {Piscataway, NJ, USA},
599}
600
601
602@Book{NIOS2,
603  title =        {{Nios II Processor Reference Handbook}},
604  publisher =    {Altera},
605  year =         {2009},
606}
607
608
609@inproceedings{ARC08,
610 author = {Galuzzi, Carlo and Bertels, Koen},
611 title = {The Instruction-Set Extension Problem: A Survey},
612 booktitle = {ARC '08: Proceedings of the 4th international workshop on Reconfigurable Computing},
613 year = {2008},
614 isbn = {978-3-540-78609-2},
615 pages = {209--220},
616 location = {London, UK},
617 doi = {http://dx.doi.org/10.1007/978-3-540-78610-8_21},
618 publisher = {Springer-Verlag},
619 address = {Berlin, Heidelberg},
620 }
621
622@inproceedings{CODES99,
623 author = {Charot, Fran\c{c}ois and Mess\'{e}, Vincent},
624 title = {{A flexible code generation framework for the design of application specific programmable processors}},
625 booktitle = {CODES '99: Proceedings of the seventh international workshop on Hardware/software codesign},
626 year = {1999},
627 pages = {27--31},
628 location = {Rome, Italy},
629 publisher = {ACM},
630 address = {New York, NY, USA},
631 }
632
633@inproceedings{ASAP05,
634 author = {L'Hours, Ludovic},
635 title = {{Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications}},
636 booktitle = {ASAP '05: Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors},
637 year = {2005},
638 pages = {127--133},
639 publisher = {IEEE Computer Society},
640 address = {Washington, DC, USA},
641}
642
643@inproceedings{roma,
644 author = {Menard, Daniel and Casseau, Emmanuel and Khan, Shafqat and Sentieys, Olivier and Chevobbe, St\'{e}phane and Guyetant, St\'{e}phane and David, Raphael},
645 title = {Reconfigurable Operator Based Multimedia Embedded Processor},
646 booktitle = {ARC '09: Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications},
647 year = {2009},
648 pages = {39--49},
649 location = {Karlsruhe, Germany},
650 publisher = {Springer-Verlag},
651 address = {Berlin, Heidelberg},
652 }
653
654%%%%%%%%%%%%% AUTRES %%%%%%%%%%%%%%%%
655
656@inproceedings{thales-viola,
657 author = {Viola, Jones},
658 title = {{Rapid Object Detection using a Boosted Cascade of Simple Feature}},
659 booktitle = {Proceedings of Conference on Computer Vision and Pattern recognition},
660 year = {2001},
661}
662@INPROCEEDINGS{FP:96
663        ,AUTHOR = "Paul Feautrier"
664        ,TITLE = "Automatic Parallelization in the Polytope Model"
665        ,BOOKTITLE = "The Data-Parallel Programming Model"
666        ,YEAR = 1996   
667        ,EDITOR = "Guy-Ren\'e Perrin and Alain Darte"
668        ,PAGES = "79--103"
669        ,VOLUME = "LNCS 1132"
670        ,PUBLISHER = "Springer"
671}
672
673@book{DRV:2000,
674    author={Alain Darte and Yves Robert and Fr\'ed\'eric Vivien},
675    title={Scheduling and automatic Parallelization},
676    publisher={Birkh\"auser}, year=2000
677}
678
679@Article{Feau:92aa,
680  author =       "Paul Feautrier",
681  title =        "Some Efficient Solutions to the Affine Scheduling
682                 Problem, {I}, One Dimensional Time",
683  volume =       "21",
684  number =       "5",
685  month =        Oct,
686  pages =        "313--348",
687  journal =      "Int. J. of Parallel Programming",
688  year =         "1992"
689}
690
691@Article{Feau:92bb,
692  author =       "Paul Feautrier",
693  title =        "Some Efficient Solutions to the Affine Scheduling
694                 Problem, {II}, Multidimensional Time",
695  volume =       "21",
696  number =       "6",
697  journal =      "Int. J. of Parallel Programming",
698  month =        Dec,
699  pages =        "389--420",
700  year =         "1992"
701}
702
703@ARTICLE{Feau:96
704        ,AUTHOR = {Paul Feautrier}
705        ,TITLE = {Distribution Automatique des Donn\'es et des
706         calculs} 
707        ,JOURNAL = {T.S.I.}
708        ,YEAR = 1996, VOLUME = 15, NUMBER = 5, PAGES = {529--557}
709}
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