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1%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
2%%%%% MDS
3%Stuyt Jan, Wolfgang Ecker, Mayer Albrecht, Hustin Serge, Amerijckx Christophe,
4%de Paoli Serge and Vaumorin Emmanuel
5@inproceedings{mds1,
6  author    = {Kruijtzer Wido, Van der Wolf Pieter, de Kock Erwin and All},
7  title     = {Industrial IP integration flows based on IP-XACT standards},
8  booktitle = {Proceedings of the conference on Design, automation and test in Europe},
9  series    = {DATE'08},
10  year      = {2008},
11  isbn      = {978-3-9810801-3-1},
12  location  = {Munich, Germany},
13  pages     = {32--37},
14  numpages  = {6},
15  url       = {http://doi.acm.org/10.1145/1403375.1403386},
16  doi       = {http://doi.acm.org/10.1145/1403375.1403386},
17  acmid     = {1403386},
18  publisher = {ACM},
19  address   = {New York, NY, USA},
20} 
21
22@misc{mds2,
23  author       = {E. Vaumorin, M. Palus, F. Clermidy and J. Martin},
24  title        = {SPIRIT IP-XACT Controlled ESL Design Tool Applied to a Network-on-Chip Platform},
25  howpublished = {\url{http://www.design-reuse.com/articles/18613/ip-xact-esl-noc.html}},
26  year         = {2008},
27}
28
29@misc{socketflow,
30  author       = {L. Maillet-Contoz, R. Lucas and E. Vaumorin},
31  title        = {SocKET design flow and Application on industrial use cases},
32  howpublished = {\url{http://socket.imag.fr/Presentations-socket/Vendredi15/Presentation_flot.pdf}},
33  note         = {home site: \url{http://socket.imag.fr/}},
34  year         = {2010},
35}
36
37@misc{dandr,
38  author       = {Marc van Hintum, Paul Williams},
39  title        = {The Value of High Quality IP-XACT XML},
40  howpublished = {\url{http://www.design-reuse.com/articles/19895/ip-xact-xml.html}},
41  year         = {2010},
42}
43
44@techreport{rapport-ministere,
45 author      = {Eric Bant\'egnie, Claude Lepape, Jean-Luc Dormoy},
46 title       = {Briques g\'en\'eriques du logiciel embarqu\'e},
47 year        = {2010},
48 institution = {Mininist\'ere de l'industrie},
49}
50
51%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
52%%%%% LIP6
53% HPC
54@InProceedings{hpc06a,
55  author    = {{M.B. Gokhale and al.}},
56  title     = {{Promises and Pitfalls of Reconfigurable Supercomputing}},
57  booktitle = {Systems and Algorithms, CSREA Press},
58  pages     = {11-20},
59  year      = {2006},
60}
61@MISC{hpc06b,
62  author =       {{D. Buell}},
63  title  =   {{Programming Reconfigurable Computers}},
64  booktitle = {Summer Institute},
65  howpublished = {http://gladiator.ncsa.uiuc.edu/PDFs/rssi06/presentations/00\_Duncan\_Buell.pdf},
66  year =         {2006},
67}
68@InProceedings{hpc07a,
69  author =       {{T. Van Court and al.}},
70  title  =   {{ Achieving High Performance with FPGA-Based Computing}},
71  booktitle = {Computer, vol. 40, no. 3},
72  pages     = {50-57},
73  month     = {mars},
74  year =         {2007},
75}
76@misc{hpc08,
77  title        = {Mitrionics},
78  howpublished = {http://www.mitrionics.com/},
79  year         = {2009},
80}
81@misc{hpc09,
82  title        = {Gidel},
83  howpublished = {http://www.gidel.com/},
84  year         = {2009},
85}
86@misc{hpc10,
87  title        = {Convey Computer},
88  howpublished = {http://www.conveycomputers.com/},
89  year         = {2009},
90}
91@InProceedings{hpc11,
92  author =      {E. El-Araby, I. Gonzalez and T. El-Ghazawi},
93  title   = {Virtual Architecture and Design Automation for Partial Reconfiguration },
94  booktitle = {HPRCTA},
95  year =         {2008},
96}
97@InProceedings{hpc12,
98  author =       {{P. Lysaght and J. Dunlop}},
99  title   = {Dynamic Reconfiguration of Field Programmable Gate Arrays},
100  booktitle = {Field Programmable Logic and Applications, Oxford, England},
101  month     = {Sept},
102  year =         {1993},
103}
104
105
106% System design
107@misc{soclib,
108  title        = {Soclib},
109  howpublished = {http://www.soclib.fr/},
110  year         = {2009},
111}
112
113@misc{system-generateur-for-dsp,
114  title        = {{System Generator for DSP}},
115  howpublished = {http://www.xilinx.com/tools/sysgen.htm},
116  year         = {2009},
117}
118
119@misc{spoc-builder,
120  title        = {{sopc builder support}},
121  howpublished = {http://www.altera.com/support/software/system/sopc/sof-sopc\_builder.html},
122  year         = {2009},
123}
124
125@InProceedings{cosy,
126    author = { J.Y Brunel and A. San Giovanni-Vincentelli and R. Krees and W. Kruijtzer },
127    title  = { COSY: a methodology for system design based on reusable hardware \& software IP's},
128    booktitle = { Technologies for the Information Society },
129    publisher = { IOS Press },
130    year      = {1998},
131    pages     = {709-716},
132}
133
134@InProceedings{disydent05,
135  author =       {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, Fran\c{c}ois Donnet and Pascal Gomez}},
136  title =        {{Platform-based design from parallel C specifications}},
137  booktitle = {IEEE Transaction on CAD of Integrated Circuits and Systems},
138  pages     = {1811--1826},
139  month     = {December},
140  year =         {2005},
141}
142@inproceedings{dspin08,
143 author = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain},
144 title = {Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture},
145 booktitle = {NOCS '08: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip},
146 year = {2008},
147 isbn = {978-0-7695-3098-7},
148 pages = {139--148},
149 publisher = {IEEE Computer Society},
150 address = {Washington, DC, USA},
151 }
152
153
154% HLS
155% http://mesl.ucsd.edu/spark/index.shtml
156@INBOOK{spark04,
157  author     = {S. Gupta and al.},
158  title      = {SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits},
159  publisher  = {Springer},
160  year       = {2004},
161}
162
163
164@INBOOK{ugh08,
165  author    = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot},
166  title     = {User Guided High Level Synthesis},
167  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
168  publisher = {Springer},
169  year      = {2008},
170  chapter   = {10},
171  pages     = {139-148},
172}
173  %editor    = { Philippe Coussy and Adam Moriawiec},
174
175@misc{pico,
176  title        = {{PICO}},
177  howpublished = {http://www.synfora.com/},
178  year         = {2009},
179}
180
181@misc{catapult-c,
182  title        = {{CATAPULT-C Mentor HLS tool}},
183  howpublished = {http://www.mentor.com/products/esl/high\_level\_synthesis/},
184  year         = {2009},
185}
186
187@misc{cynthetizer,
188  title        = {{Forte's CYNTHESIZER}},
189  howpublished = {http://www.forteds.com/},
190  year         = {2009},
191}
192
193@inproceedings{IP-XACT-08,
194 author = {Kruijtzer, Wido and van der Wolf, Pieter and de Kock, Erwin and Stuyt, Jan and Ecker, Wolfgang and Mayer, Albrecht and Hustin, Serge and Amerijckx, Christophe and de Paoli, Serge and Vaumorin, Emmanuel},
195 title = {Industrial IP integration flows based on IP-XACT standards},
196 booktitle = {Proceedings of the conference on Design, automation and test in Europe},
197 series = {DATE '08},
198 year = {2008},
199 isbn = {978-3-9810801-3-1},
200 location = {Munich, Germany},
201 pages = {32--37},
202 numpages = {6},
203 url = {http://doi.acm.org/10.1145/1403375.1403386},
204 doi = {http://doi.acm.org/10.1145/1403375.1403386},
205 acmid = {1403386},
206 publisher = {ACM},
207 address = {New York, NY, USA},
208}
209
210
211%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
212%%% UBS
213
214@INBOOK{IEEEDT,
215author = {Philippe Coussy and Andres Takach},
216title = {Special Issue on High-Level Synthesis},
217journal ={IEEE Design and Test of Computers},
218volume = {25},issn = {0740-7475},
219year = {2008},
220pages = {393},doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2008.147},
221publisher = {IEEE Computer Society},
222address = {Los Alamitos, CA, USA},}
223
224
225@BOOK{HLSBOOK,
226  author    = {P. Coussy and A. Morawiec},
227  title = {High-Level Synthesis: From Algorithm to Digital Circuits},
228  publisher = {Springer},
229  year      = {2008},
230}
231
232@BOOK{CATRENE,
233  author    = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
234  title = {European Roadmap for EDA},
235  publisher = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
236  year      = {2009},
237}
238
239@INBOOK{gaut08,
240  author    = {P. Coussy and al.},
241  title     = {GAUT: A High-Level Synthesis Tool for DSP applications},
242  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
243  publisher = {Springer},
244  year      = {2008},
245}
246
247@article{DBLP:journals:dt:CoussyT09,
248  author    = {Philippe Coussy and
249               Andres Takach},
250  title     = {Guest Editors' Introduction: Raising the Abstraction Level
251               of Hardware Design},
252  journal   = {IEEE Design {\&} Test of Computers},
253  volume    = {26},
254  number    = {4},
255  year      = {2009},
256  pages     = {4-6},
257  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.80},
258  bibsource = {DBLP, http://dblp.uni-trier.de}
259}
260
261
262@article{DBLP:journals:dt:CoussyGMT09,
263  author    = {Philippe Coussy and
264               Daniel D. Gajski and
265               Michael Meredith and
266               Andres Takach},
267  title     = {An Introduction to High-Level Synthesis},
268  journal   = {IEEE Design {\&} Test of Computers},
269  volume    = {26},
270  number    = {4},
271  year      = {2009},
272  pages     = {8-17},
273  ee        = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.69},
274  bibsource = {DBLP, http://dblp.uni-trier.de}
275}
276
277
278@article{DBLP:journals:vlsisp:ThabetCHM09,
279  author    = {Farhat Thabet and
280               Philippe Coussy and
281               Dominique Heller and
282               Eric Martin},
283  title     = {Exploration and Rapid Prototyping of DSP Applications using
284               SystemC Behavioral Simulation and High-level Synthesis},
285  journal   = {Signal Processing Systems},
286  volume    = {56},
287  number    = {2-3},
288  year      = {2009},
289  pages     = {167-186},
290  ee        = {http://dx.doi.org/10.1007/s11265-008-0235-1},
291  bibsource = {DBLP, http://dblp.uni-trier.de}
292}
293
294
295
296@inproceedings{CHAVET:2007:HAL-00153994:1,
297        title = { {A} {M}ethodology for {E}fficient {S}pace-{T}ime {A}dapter {D}esign {S}pace {E}xploration: {A} {C}ase {S}tudy of an {U}ltra {W}ide {B}and {I}nterleaver},
298        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
299        abstract = {{T}his paper presents a solution to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {T}he {RCG} properties enable an efficient architecture space exploration in order to synthesize a {STAR} component. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
300        language = {{A}nglais},
301        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
302        booktitle = {{P}roceedings of the {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) {T}he {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) },
303        publisher = {{L}ibrary of {C}ongress },
304        pages = {2946 },
305        address = {{N}ew {O}rleans {\'E}tats-{U}nis d'{A}m{\'e}rique },
306        editor = {{IEEE} },
307        note = {{ISBN}:1-4244-0921-7 },
308        audience = {internationale },
309    day = {28},
310    month = {05},
311    year = {2007},
312    URL = {http://hal.archives-ouvertes.fr/hal-00153994/en/},
313    URL = {http://hal.archives-ouvertes.fr/hal-00153994/PDF/ISCAS_Chavet1992.pdf},
314}
315
316
317@inproceedings{DBLP:conf:iccad:ChavetACCJUM07,
318  author    = {Cyrille Chavet and
319               Caaliph Andriamisaina and
320               Philippe Coussy and
321               Emmanuel Casseau and
322               Emmanuel Juin and
323               Pascal Urard and
324               Eric Martin},
325  title     = {A design flow dedicated to multi-mode architectures for
326               DSP applications},
327  booktitle = {ICCAD},
328  year      = {2007},
329  pages     = {604-611},
330  ee        = {http://doi.acm.org/10.1145/1326073.1326199},
331  bibsource = {DBLP, http://dblp.uni-trier.de}
332}
333%crossref  = {DBLP:conf:iccad:2007},
334
335
336@inproceedings{DBLP:conf:glvlsi:ChavetCUM07,
337  author    = {Cyrille Chavet and
338               Philippe Coussy and
339               Pascal Urard and
340               Eric Martin},
341  title     = {A design methodology for space-time adapter},
342  booktitle = {ACM Great Lakes Symposium on VLSI},
343  year      = {2007},
344  pages     = {347-352},
345  ee        = {http://doi.acm.org/10.1145/1228784.1228868},
346  bibsource = {DBLP, http://dblp.uni-trier.de}
347}
348%crossref  = {DBLP:conf:glvlsi:2007},
349
350
351@inproceedings{CHAVET:2007:HAL-00154025:1,
352        title = { {A}pplication of a design space exploration tool to enhance interleaver generation},
353        author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric},
354        abstract = {{T}his paper presents a methodology to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {D}esign space exploration is then performed through associated tools, to synthesize a {STAR} component under time-to-market constraints. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.},
355        language = {{A}nglais},
356        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics },
357        booktitle = {{P}roceedings of the {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) },
358        publisher = {{E}urasip },
359        pages = {??? },
360        address = {{P}oznan {P}ologne },
361        audience = {internationale },
362    day = {03},
363    month = {09},
364    year = {2007},
365    URL = {http://hal.archives-ouvertes.fr/hal-00154025/en/},
366    URL = {http://hal.archives-ouvertes.fr/hal-00154025/PDF/EUSIPCO_chavet.pdf},
367}
368
369
370@inproceedings{ANDRIAMISAINA:2007:HAL-00153086:1,
371        title = { {S}ynthesis of {M}ultimode digital signal processing systems},
372        author = {{A}ndriamisaina, {C}aaliph and {C}asseau, {E}mmanuel and {C}oussy, {P}hilippe},
373        abstract = {{I}n this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. {T}he inputs of the design flow are the data flow graphs ({DFG}s), representing the different modes (i.e. the different applications to be implemented), with their respective throughput constraints. {W}hile traditional approaches merge {DFG}s together before the synthesis process, we propose to use ad-hoc scheduling and binding steps during the synthesis of each {DFG}. {T}he scheduling, which assigns operations to specific time steps, maximizes the similarity between the control steps and thus decreases the controller complexity. {T}he binding process, which assigns operations to specific functional units and data to specific storage elements, maximizes the similarity between datapaths and thus minimizes steering logic and register overhead. {F}irst results show the interest of the proposed synthesis flow.},
374        language = {{A}nglais},
375        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {R}2{D}2 - {INRIA} - {IRISA} - {CNRS} : {UMR}6074 - {INRIA} - {I}nstitut {N}ational des {S}ciences {A}ppliqu{\'e}es de {R}ennes - {E}cole {N}ationale {S}up{\'e}rieure des {S}ciences {A}ppliqu{\'e}es et de {T}echnologie - {U}niversit{\'e} de {R}ennes 1 },
376        booktitle = {{P}roceeding of {A}daptive {H}ardware and {S}ystems {NASA}/{ESA} {C}onference on {A}daptive {H}ardware and {S}ystems },
377        publisher = {{AHS} },
378        pages = {7 },
379        address = {{E}dinburgh {R}oyaume-{U}ni },
380        audience = {internationale },
381    year = {2007},
382    URL = {http://hal.archives-ouvertes.fr/hal-00153086/en/},
383    URL = {http://hal.archives-ouvertes.fr/hal-00153086/PDF/PID411805.pdf},
384}
385
386
387@inproceedings{COUSSY:2005:HAL-00077301:1,
388        title = { {A} {M}ore {E}fficient and {F}lexible {DSP} {D}esign {F}low from {MATLAB}-{SIMULINK}},
389        author = {{C}oussy, {P}hilippe and {C}orre, {G}wenol{\'e} and {B}omel, {P}ierre and {S}enn, {E}ric and {M}artin, {E}ric},
390        abstract = {{T}he design of complex {D}igital {S}ignal {P}rocessing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. {U}nfortunately, the traditional {M}atlab/{S}imulink design flows gather not very flexible hardware blocs. {I}n this paper, we present a methodology and a tool that permit the {H}igh-{L}evel {S}ynthesis of {DSP} applications, under both {I}/{O} timing and memory constraints. {B}ased on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. {T}he efficiency of our approach is demonstrated on the case study of a {FFT} algorithm.},
391        keywords = {{DSP} application, synthesis under memory and communication constraints},
392        language = {{A}nglais},
393        affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud },
394        booktitle = {{IEEE} {I}nternational {C}onference on {A}coustic, {S}peech and {S}ignal {P}rocessing },
395        publisher = {{IEEE} },
396        pages = {{V}ol. {V} p. 61-64 },
397        editor = {{IEEEE} },
398    year = {2005},
399    URL = {http://hal.archives-ouvertes.fr/hal-00077301/en/},
400    URL = {http://hal.archives-ouvertes.fr/hal-00077301/PDF/coussy_final.pdf},
401}
402
403@ARTICLE{5605303,
404  author={Andriamisaina, C. and Coussy, P. and Casseau, E. and Chavet, C.},
405  journal={Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, title={High-Level Synthesis for Designing Multimode Architectures},
406  year={2010},
407  month={nov.},
408  volume={29},
409  number={11},
410  pages={1736 -1749},
411  keywords={GAUT;associated high-level synthesis tool;controller complexity;digital signal processing;image processing;joint-scheduling algorithm;monomode architectures;multimode architecture design;single register transfer level hardware architecture;specific binding approach;high level synthesis;reconfigurable architectures;scheduling;},
412  doi={10.1109/TCAD.2010.2062751},
413  ISSN={0278-0070},
414}
415
416
417%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
418%%%%% IRISA
419@InProceedings{KluterCodes08,
420  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
421  title =        {{Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions}},
422  booktitle = {ISSS/CODES},
423  year =         {2008},
424}
425
426@InProceedings{KluterDAC09,
427  author =       {{Theo Kluter and  Philip Brisk and  Paolo Ienne and  and Edoardo Charbon}},
428  title =        {{Way Stealing : Cache-assisted Automatic Instruction Set Extensions}},
429  booktitle = {Design Automation Conference (DAC)},
430  year =         {2009},
431}
432
433@InProceedings{YuCodes04,
434  author =       {{Pan Yu and Tulika Mitra}},
435  title =        {{Scalable Custom Instructions Identification for Instruction Set Extensible Processors}},
436  booktitle = {ISSS/CODES},
437  year =         {2004},
438}
439
440@InProceedings{Dinh08,
441  author =       {{Quang Dinh and Deming Chen and Martin D.~F.~Wong}},
442  title =        {{Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing}},
443  booktitle = {ACM Internatibnal Conference Field Programmable Gate Arrays (FPGA)},
444  year =         {2008},
445}
446
447@Misc{NIOS2UG,
448  title =        {{Nios II Custom Instruction User Guide, Altera Corp.}},
449  year =         {2008},
450}
451
452%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
453%%% CITI
454@book{Polis,
455  author = {Balarin, Felice},
456  publisher = {Kluwer Academic Publishers},
457  title = {Hardware-software co-design of embedded systems : the POLIS
458        approach},
459  year = {1997}
460}
461
462@INPROCEEDINGS{Coware,
463  author = {Ivo Bolsens and Hugo J. De Man and Bill Lin and Karl Van
464                Rompaey and Steven Vercauteren and Diederik Verkest},
465  title = {Hardware/Software Co-Design of Digital Telecommunication Systems},
466  booktitle = {Proceedings of the IEEE},
467  year = {1997},
468  pages = {391--418}
469}
470
471@article{Jantsch,
472  author = {Mattias O'Nil and Axel Jantsch},
473  title = {Device Driver and DMA Controller Synthesis from HW/SW
474                        Communication protocol specifications},
475  journal = {Design Automation for Embedded Systems},
476  year = {2001},
477  volume = {6},
478  pages = {177-205}
479}
480
481@InProceedings{Park01,
482  author =   {Joonseok Park and Pedro C.~Diniz},
483  title =    {Synthesis of Pipelined Memory Access Controllers for Streamed
484                Data Applications on {FPGA}-Based Computing Engines},
485  booktitle =    {International Symposium on System Synthesis (ISSS)},
486  pages = {221-226},
487  year =     {2001},
488}
489
490@article{FR-vlsi,
491  author = {Antoine Fraboulet and Tanguy Risset},
492  title = {Master Interface for On-Chip Hardware Accelerator Burst Communications},
493  journal = {Journal of VLSI Signal Processing},
494  publisher = {Springer Science},
495  year = {2007},
496  volume = {59},
497  pages = {73-85}
498}
499
500@InProceedings{jerraya,
501  author =   {Sungjoo Yoo and Jerraya Ahmed},
502  title =    {Introduction to Hardware Abstraction Layers for SoC},
503  OPTcrossref =  {},
504  OPTkey =   {},
505  booktitle = {Design, Automation and Test in Europe Conference and Exhibition},
506  pages =    {336 -- 337},
507  year =     2003,
508  OPTeditor =    {},
509  OPTvolume =    {},
510  OPTnumber =    {},
511  OPTseries =    {},
512  OPTaddress =   {},
513  OPTmonth =     {},
514  OPTorganization = {},
515  OPTpublisher = {},
516  OPTnote =      {},
517  OPTannote =    {}
518}
519
520@INPROCEEDINGS{FAUST,
521  author = {D. Lattard and  E. Beigne and  C. Bernard and  C. Bour and  F.
522        Clermidy and  Y. Durand and  J. Durupt and  D. Varreau and  P. Vivet and
523        P. Penard and  A. Bouttier and  F. Berens}, 
524  title = "A Telecom Baseband Circuit-Based on an Asynchronous Network-on-Chip", 
525  pages = {},
526  BOOKTITLE="ISSCC\'2007", 
527  year = {2007},
528  publisher = {IEEE Computer Society},
529  address = {San Francisco, USA},
530};
531
532@inproceedings{JerrayaPetrot,
533 author = {Ahmed A. Jerraya and Aimen Bouchhima and Fr\'{e}d\'{e}ric P\'{e}trot},
534 title = {Programming models and HW-SW interfaces abstraction for multi-processor SoC},
535 booktitle = {DAC '06: Proceedings of the 43rd annual conference on Design automation},
536 year = {2006},
537 isbn = {1-59593-381-6},
538 pages = {280--285},
539 location = {San Francisco, CA, USA},
540 publisher = {ACM},
541 address = {New York, NY, USA},
542}
543
544@inproceedings{mwmr,
545 author = {E. Faure and A. Greiner and D. Genius},
546 title = {A generic hardware/software communication mechanism for
547          Multi-Processor System on Chip, Targeting Telecommunication Applications},
548 booktitle = {ReCoSoC'06},
549 year = {2006},
550 pages = {237--242},
551 address = {Montpellier, France}
552 }
553
554@inproceedings{Alberto,
555  author    = {Roberto Passerone and
556               James A. Rowson and
557               Alberto L. Sangiovanni-Vincentelli},
558  title     = {Automatic Synthesis of Interfaces Between Incompatible Protocols},
559  booktitle = {DAC},
560  year      = {1998},
561  pages     = {8-13}
562}
563
564@article{Avnit,
565  author    = {Karin Avnit and
566               Vijay D'Silva and
567               Arcot Sowmya and
568               S. Ramesh and
569               Sri Parameswaran},
570  title     = {Provably correct on-chip communication: A formal approach
571               to automatic protocol converter synthesis},
572  journal   = {ACM Trans. Design Autom. Electr. Syst.},
573  volume    = {14},
574  number    = {2},
575  year      = {2009}
576}
577
578@inproceedings{smith,
579  author    = {James Smith and
580               Giovanni De Micheli},
581  title     = {Automated Composition of Hardware Components},
582  booktitle = {DAC},
583  year      = {1998},
584  pages     = {14-19}
585}
586
587@inproceedings{Narayan,
588  author    = {Sanjiv Narayan and
589               Daniel Gajski},
590  title     = {Interfacing Incompatible Protocols Using Interface Process
591               Generation},
592  booktitle = {DAC},
593  year      = {1995},
594  pages     = {468-473}
595}
596
597@TECHREPORT{Ptolemy,
598  AUTHOR       = { E.A. Lee et al.},
599  INSTITUTION  = {University of California, Berkeley},
600  NUMBER       = {UCB/ERL No. M99/37},
601  TITLE        = {Overview of the Ptolemy Project},
602  YEAR         = {1999},
603  MONTH        = {july}
604}
605
606@article{syntol,
607    author={Paul Feautrier},
608    title={Scalable and Structured Scheduling},
609    journal={Int. J. of Parallel Programming},
610    year=2006,
611    month=May, number=5, volume=34,
612    pages="459--487"
613}
614
615@InProceedings{bee,
616  author={Christophe Alias and Fabrice Baray and Alain Darte},
617  title={Bee+Cl@k: An Implementation of Lattice-Based Array Contraction in the Source-to-Source Translator ROSE},
618  booktitle = {LCTES},
619  year = {2007},
620  publisher = {ACM}
621}
622
623%%%%%%%%%%%%% ASIP %%%%%%%%%%%%%%%%
624
625@inproceedings{DAC09,
626 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
627 title = {Way Stealing: cache-assisted automatic instruction set extensions},
628 booktitle = {DAC '09: Proceedings of the 46th Annual Design Automation Conference},
629 year = {2009},
630 isbn = {978-1-60558-497-3},
631 pages = {31--36},
632 location = {San Francisco, California},
633 doi = {http://doi.acm.org/10.1145/1629911.1629923},
634 publisher = {ACM},
635 address = {New York, NY, USA},
636 }
637
638@inproceedings{CODES08,
639 author = {Kluter, Theo and Brisk, Philip and Ienne, Paolo and Charbon, Edoardo},
640 title = {Speculative DMA for architecturally visible storage in instruction set extensions},
641 booktitle = {CODES/ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis},
642 year = {2008},
643 isbn = {978-1-60558-470-6},
644 pages = {243--248},
645 location = {Atlanta, GA, USA},
646 doi = {http://doi.acm.org/10.1145/1450135.1450191},
647 publisher = {ACM},
648 address = {New York, NY, USA},
649 }
650 
651@article{TVLSI06,
652        author = {Cong, Jason and Han, Guoling and Zhang, Zhiru},
653 title = {Architecture and compiler optimizations for data bandwidth improvement in configurable processors},
654 journal = {IEEE Trans. Very Large Scale Integr. Syst.},
655 volume = {14},
656 number = {9},
657 year = {2006},
658 issn = {1063-8210},
659 pages = {986--997},
660 doi = {http://dx.doi.org/10.1109/TVLSI.2006.884050},
661 publisher = {IEEE Educational Activities Department},
662 address = {Piscataway, NJ, USA},
663}
664
665
666@Book{NIOS2,
667  title =        {{Nios II Processor Reference Handbook}},
668  publisher =    {Altera},
669  year =         {2009},
670}
671
672
673@inproceedings{ARC08,
674 author = {Galuzzi, Carlo and Bertels, Koen},
675 title = {The Instruction-Set Extension Problem: A Survey},
676 booktitle = {ARC '08: Proceedings of the 4th international workshop on Reconfigurable Computing},
677 year = {2008},
678 isbn = {978-3-540-78609-2},
679 pages = {209--220},
680 location = {London, UK},
681 doi = {http://dx.doi.org/10.1007/978-3-540-78610-8_21},
682 publisher = {Springer-Verlag},
683 address = {Berlin, Heidelberg},
684 }
685
686@inproceedings{CODES99,
687 author = {Charot, Fran\c{c}ois and Mess\'{e}, Vincent},
688 title = {{A flexible code generation framework for the design of application specific programmable processors}},
689 booktitle = {CODES '99: Proceedings of the seventh international workshop on Hardware/software codesign},
690 year = {1999},
691 pages = {27--31},
692 location = {Rome, Italy},
693 publisher = {ACM},
694 address = {New York, NY, USA},
695 }
696
697@inproceedings{ASAP05,
698 author = {L'Hours, Ludovic},
699 title = {{Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications}},
700 booktitle = {ASAP '05: Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors},
701 year = {2005},
702 pages = {127--133},
703 publisher = {IEEE Computer Society},
704 address = {Washington, DC, USA},
705}
706
707@inproceedings{roma,
708 author = {Menard, Daniel and Casseau, Emmanuel and Khan, Shafqat and Sentieys, Olivier and Chevobbe, St\'{e}phane and Guyetant, St\'{e}phane and David, Raphael},
709 title = {Reconfigurable Operator Based Multimedia Embedded Processor},
710 booktitle = {ARC '09: Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications},
711 year = {2009},
712 pages = {39--49},
713 location = {Karlsruhe, Germany},
714 publisher = {Springer-Verlag},
715 address = {Berlin, Heidelberg},
716 }
717
718%%%%%%%%%%%%% AUTRES %%%%%%%%%%%%%%%%
719
720@inproceedings{thales-viola,
721 author = {Viola, Jones},
722 title = {{Rapid Object Detection using a Boosted Cascade of Simple Feature}},
723 booktitle = {Proceedings of Conference on Computer Vision and Pattern recognition},
724 year = {2001},
725}
726@INPROCEEDINGS{FP:96
727        ,AUTHOR = "Paul Feautrier"
728        ,TITLE = "Automatic Parallelization in the Polytope Model"
729        ,BOOKTITLE = "The Data-Parallel Programming Model"
730        ,YEAR = 1996   
731        ,EDITOR = "Guy-Ren\'e Perrin and Alain Darte"
732        ,PAGES = "79--103"
733        ,VOLUME = "LNCS 1132"
734        ,PUBLISHER = "Springer"
735}
736
737@book{DRV:2000,
738    author={Alain Darte and Yves Robert and Fr\'ed\'eric Vivien},
739    title={Scheduling and automatic Parallelization},
740    publisher={Birkh\"auser}, year=2000
741}
742
743@Article{Feau:92aa,
744  author =       "Paul Feautrier",
745  title =        "Some Efficient Solutions to the Affine Scheduling
746                 Problem, {I}, One Dimensional Time",
747  volume =       "21",
748  number =       "5",
749  month =        Oct,
750  pages =        "313--348",
751  journal =      "Int. J. of Parallel Programming",
752  year =         "1992"
753}
754
755@Article{Feau:92bb,
756  author =       "Paul Feautrier",
757  title =        "Some Efficient Solutions to the Affine Scheduling
758                 Problem, {II}, Multidimensional Time",
759  volume =       "21",
760  number =       "6",
761  journal =      "Int. J. of Parallel Programming",
762  month =        Dec,
763  pages =        "389--420",
764  year =         "1992"
765}
766
767@ARTICLE{Feau:96
768        ,AUTHOR = {Paul Feautrier}
769        ,TITLE = {Distribution Automatique des Donn\'es et des
770         calculs} 
771        ,JOURNAL = {T.S.I.}
772        ,YEAR = 1996, VOLUME = 15, NUMBER = 5, PAGES = {529--557}
773}
774
775%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
776%%% IA
777
778@PHDTHESIS{ia-hdr-phd,
779  author    = {Ivan Aug\'{e}},
780  title     = {Th\`ese d'Habilitation \`a Diriger des Recherches:
781               Synth\`ese de haut niveau \& Int\'egration
782               des syst\`emes mat\'eriel/logiciel},
783  school    = {Universit\'e Pierre et Marie Curie},
784  year      = {2009},
785  month     = {12},
786}
787
788@MISC{ia-hdr,
789  author    = {Ivan Aug\'{e}},
790  title     = {Th\`ese d'Habilitation \`a Diriger des Recherches:
791               Synth\`ese de haut niveau \& Int\'egration
792               des syst\`emes mat\'eriel/logiciel},
793  howpublished = {Universit\'e Pierre et Marie Curie},
794  year      = {2009},
795  month     = {12},
796}
797
798@INBOOK{ia-ugh08,
799  author    = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot},
800  title     = {User Guided High Level Synthesis},
801  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
802  publisher = {Springer},
803  chapter   = {10},
804  year      = {2008},
805  pages     = {139-148},
806}
807  %editor    = {Philippe Coussy and Adam Moriawiec},
808
809@misc{ia-ugh-09-aspdac,
810  author   = {Fr\'ed\'eric P\'etrot and Ivan Aug\'e},
811  title    = {User Guided High Level Synthesis},
812  booktitle= {Workshop "High-Level Synthesis: Next Step to Efficient ESL Design",
813                      in conjunction with ASP-DAC},
814  year     = {2009},
815}
816
817@misc{ia-ugh-08-date,
818  author =  {Fr\'ed\'eric P\'etrot and Ivan Aug\'e},
819  title = {User Guided High Level Synthesis},
820  booktitle= { Workshop "The New Wave of the High-Level Synthesis",
821                      in conjunction with DATE},
822  year       = {2008},
823}
824
825%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
826%%% AG
827
828@article{ag-1,
829    author = {Zhen Zhang and Alain Greiner and Mounir Benabdenbi},
830    title = {Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components},
831    journal ={On-Line Testing Symposium, IEEE International},
832    volume = {0},
833    isbn = {978-1-4244-7724-1},
834    year = {2010},
835    pages = {194-196},
836    doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2010.5560209},
837    publisher = {IEEE Computer Society},
838    address = {Los Alamitos, CA, USA},
839}
840
841@inproceedings{ag-2,
842    author    = {Greiner Alain and Faure Etienne and Pouillon Nicolas and Genius Dani\'ela},
843    title     = {A Generic Hardware/Software Communication Middleware for
844                 Streaming Applications on Shared Memory Multi Processor Systems-on-Chip},
845    booktitle = {Forum on Specification \& Design Languages (FDL 2009)},
846    isbn      = { 978-2-9530504-1-7},
847    month     = {September},
848    year      = {2009},
849    address   = {Nice, France},
850}
851
852@inproceedings{ag-3,
853    author    = {Porquet, Jo\"{e}l and Schwarz, Christian and Greiner, Alain},
854    title     = {Multi-compartment: A new architecture for secure
855                 co-hosting on SoC },
856    booktitle = {Proceedings of the 11th international conference on System-on-chip},
857    series    = {SOC'09},
858    month     = {October},
859    year      = {2009},
860    isbn      = {978-1-4244-4466-3},
861    location  = {Tampere, Finland},
862    pages     = {124-127},
863    numpages  = {4},
864    url       = {http://portal.acm.org/citation.cfm?id=1736530.1736555},
865    publisher = {IEEE Press},
866    address   = {Piscataway, NJ, USA},
867}
868
869@inproceedings{ag-4,
870    author    = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain},
871    title     = {Physical Implementation of the DSPIN Network-on-Chip in the
872                 FAUST Architecture},
873    booktitle = {Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip},
874    series    = {NOCS'08},
875    year      = {2008},
876    month     = {April},
877    isbn      = {978-0-7695-3098-7},
878    location  = {Newcastle, UK},
879    pages     = {139-148},
880    numpages = {10},
881    url = {http://portal.acm.org/citation.cfm?id=1397757.1397994},
882    publisher = {IEEE Computer Society},
883    address   = {Washington, DC, USA},
884}
885
886@inproceedings{mutek,
887        author = {Fr\'ed\'eric P\'etrot and Pascal Gomez},
888        title = {Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect},
889        booktitle = {Proceedings of the conference on Design, Automation and Test in Europe},
890        year = {2003},
891        isbn = {0-7695-1870-2-2},
892        pages = {20051},
893        publisher = {IEEE Computer Society},
894        address_hide = {Washington, DC, USA},
895}
896@inproceedings{dna,
897Author = {Xavier Gu\'erin and Fr\'ed\'eric P\'etrot},
898booktitle={IEEE International Conf. on Application -specific Systems, Architectures and Processors},
899Title = {A {S}ystem {F}ramework for the {D}esign of {E}mbedded {S}oftware {T}argeting {H}eterogeneous {M}ulti-{C}ore {S}o{C}s},
900Year = {2009},
901    pages     = {153-160},
902}
903
904%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
905%%% CA
906
907@InProceedings{ca:arc,
908  author =       {Christophe Alias and Bogdan Pasca and Alexandru Plesco},
909  title =        {Automatic Generation of {FPGA}-Specific Pipelined Accelerators},
910  booktitle =    {7th International Symposium on Applied Reconfigurable Computing (ARC)},
911  year =         {2011},
912  publisher =    {Springer LNCS}
913}
914
915@InProceedings{ca:chuba,
916  author =       {Christophe Alias and Alain Darte and Alexandru Plesco},
917  title =        {Optimizing {DDR-SDRAM} Communications at {C}-level for Automatically-Generated Hardware Accelerators. {A}n Experience With the {A}ltera {C2H HLS} Tool},
918  booktitle =    {IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)},
919  year =         {2010}
920}
921
922@InProceedings{ca:nuca,
923  author =       {Qingda Lu and Christophe Alias and Uday Bondhugula and Sriram Krishnamoorthy and J. Ramanujam and Atanas Rountev and P. Sadayappan and Yongjian Chen and Haibo Lin and Tin-fook Ngai},
924  title =        {Data Layout Transformation for Enhancing Locality on {NUCA} Chip Multiprocessors},
925  booktitle =    {ACM/IEEE Conference on Parallel Architectures and Compilation Techniques (PACT)},
926  year =         {2009}
927}
928
929
930%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
931%%% FC
932
933@InProceedings{    Martin09c,
934 author        = {Martin, K. and Wolinski, Ch. and Kuchcinski, K. and Floch, A. and Charot, F.},
935 title          = {Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system},
936 address       = {Boston, MA, USA}, 
937month         = jul,
938 year           = 2009,
939booktitle ={Proc. of the 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors},
940pages = {145-152},
941publisher = {IEEE Computer Society},
942        x-proceedings = {yes}, 
943        x-international-audience = {yes}, 
944        x-editorial-board = {yes}, 
945        x-invited-conference = {no},
946        x-hal = {no}
947}
948
949@InProceedings{Martin09d,
950 author        = {Martin, K. and Wolinski, Ch. and Kuchcinski, K. and Floch, A. and Charot, F.},
951 title          = {Constraint-Driven Identification of Application Specific Instructions in the DURASE system},
952 booktitle     = {Proc. of Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)},
953 address = {Samos, Greece},
954month         = jul,
955 year           = 2009,
956volume = {5657},
957series = {Lecture Notes in Computer Science},
958pages = {194-203},
959publisher = {Springer},
960        x-proceedings = {yes}, 
961        x-international-audience = {yes}, 
962        x-editorial-board = {yes}, 
963        x-invited-conference = {no}, 
964        x-hal = {no}
965}
966@InProceedings{    Wolinski09a,
967 author        = {Wolinski, Ch. and Kuchcinski, K. and Raffin, E. and Charot, F.},
968 title          = {Architecture-Driven Synthesis of Reconfigurable Cells},
969booktitle = {{Proc. of the 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD)}},
970 address       = {Patras, Greece}, 
971month         = sep,
972 year           = 2009,
973pages = {531 - 538 },
974doi={10.1109/DSD.2009.183},
975        x-proceedings = {yes}, 
976        x-international-audience = {yes}, 
977        x-editorial-board = {yes}, 
978        x-invited-conference = {no}, 
979        x-hal = {no}
980}
981@inproceedings{RAFFIN:2010:INRIA-00539874:1,
982    HAL_ID = {inria-00539874},
983    URL = {http://hal.inria.fr/inria-00539874/en/},
984    title = { {S}cheduling, {B}inding and {R}outing {S}ystem for a {R}un-{T}ime {R}econfigurable {O}perator {B}ased {M}ultimedia {A}rchitecture},
985    author = {{R}affin, {E}rwan and {W}olinski, {C}hristophe and {C}harot, {F}ran{\c{c}}ois and {K}uchcinski, {K}rzysztof and {G}uyetant, {S}t{\'e}phane and {C}hevobbe, {S}t{\'e}phane and {C}asseau, {E}mmanuel},
986    booktitle = {Conference on {D}esign and {A}rchitectures for {S}ignal and {I}mage {P}rocessing ({DASIP} 2010)},
987    address = {{E}dinburgh {R}oyaume-{U}ni },
988    audience = {internationale },
989    month = oct,
990    year = {2010},
991    URL = {http://hal.inria.fr/inria-00539874/PDF/dasip2010.pdf},
992    x-hal={inria-00539874},
993}
994
995@INBOOK{sd:mmalpha,
996  chapter = {High-Level Synthesis of Loops Using the Polyhedral Model: The MMAlpha Software},
997  pages = {215-230},
998  title = {High-Level Synthesis From Algorithm to Digital Circuit},
999  publisher = {Springer Netherlands},
1000  year = {2008},
1001  editor = {Philippe Coussy and Adam Morawiec},
1002  author = {Steven Derrien and Sanjay Rajopadhye and Patrice Quinton and Tanguy Risset},
1003  doi = {10.1007/978-1-4020-8588-8},
1004  x-international-audience = {yes}, 
1005  x-editorial-board = {yes},
1006  x-proceedings = {yes},
1007        x-hal = {no}
1008}
1009
1010
1011@article{sd:rdisk,
1012    author= {Stéphane Guyetant and  Mathieu Giraud and  Ludovic L'Hours and  Steven Derrien and  Stephane Rubini and  Dominique Lavenier and  Frédéric Raimbault },
1013    title= {{Cluster of Reconfigurable Nodes for Scanning Large Genomic Banks}},
1014    journal= {Parallel Computing},
1015    year ={2005}
1016}
1017
1018@inproceedings{sd:lomita,
1019    author= {M. Adeel Pasha and Steven Derrien and Olivier Sentieys},
1020    title= {{A complete design-flow for the generation of ultra low-power wsn node architectures based on micro- tasking}},
1021    booktitle = {Proceedings of the IEEE/ACM Design Automation Conference},
1022    year= {2010}
1023}
1024
1025@article{sd:hmmer,
1026    author= {Steven Derrien and  Patrice Quinton},
1027    title= {{ Hardware Acceleration of HMMER on FPGAs}},
1028    journal= {Journal of Signal Processing Systems },
1029    year ={2010},
1030}
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